74FST3253QSR

74FST3253 Dual 4:1 Multiplexer/ Demultiplexer Bus Switch The ON Semiconductor 74FST3253 is a dual 4:1, high performance multiplexer/demultiplexer bus switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. • RON  4  Typical • Less Than 0.25 ns–Max Delay Through Switch • Nearly Zero Standby Current • No Circuit Bounce • Control Inputs are TTL/CMOS Compatible • Pin–For–Pin Compatible With QS3253, FST3253, CBT3253 • All Popular Packages: QSOP–16, TSSOP–16, SOIC–16 http://onsemi.com MARKING DIAGRAMS 16 16 FST3253 AWLYWW 1 SO–16 D SUFFIX CASE 751B 1 16 16 FST 3253 ALYW 1 OE1 S1 1B4 1B3 1B2 1B1 1A GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE2 S0 2B4 2B3 2B2 2B1 2A S1 S0 OE1 OE2 X X L L H H X X L H L H Figure 1. 16–Lead Pinout H X L L L L X H L L L L TSSOP–16 DT SUFFIX CASE 948F Function Disconnect 1A Disconnect 2A A = B1 A = B2 A = B3 A = B4 1 16 16 S3253 ALYW 1 Figure 2. Truth Table QSOP–16 QS SUFFIX CASE 492 A L, WL Y W, WW 1 = = = = Assembly Location Wafer Lot Year Work Week PIN NAMES Pin OE1, OE2 Description Bus Switch Enables S0, S1 Select Inputs A Bus A B1, B2, B3, B4 Bus B ORDERING INFORMATION  Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 1 1 Device Package Shipping 74FST3253D SO–16 48 Units/Rail 74FST3253DR2 SO–16 2500 Units/Reel 74FST3253DT TSSOP–16 96 Units/Rail 74FST3253DTR2 TSSOP–16 2500 Units/Reel 74FST3253QS QSOP–16 96 Units/Rail 74FST3253QSR QSOP–16 2500 Units/Reel Publication Order Number: 74FST3253/D 74FST3253 1A 1B1 1B2 1B3 1B4 2B1 2A 2B2 2B3 2B4 FLOW CONTROL OE1 OE2 S0 S1 Figure 3. Logic Diagram http://onsemi.com 2 74FST3253 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage 0.5 to 7.0 V VI DC Input Voltage 0.5 to 7.0 V VO DC Output Voltage 0.5 to 7.0 V IIK DC Input Diode Current VI  GND 50 mA IOK DC Output Diode Current VO  GND 50 mA IO DC Output Sink Current 128 mA ICC DC Supply Current per Supply Pin
100 mA IGND DC Ground Current per Ground Pin
100 mA TSTG Storage Temperature Range 65 to 150
C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias JA Thermal Resistance MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) 2000 200 N/A V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 85
C (Note 4)
500 mA SOIC TSSOP QSOP 260
C 150
C 125 170 200
C/W Level 1 Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. Tested to EIA/JESD22–A114–A. 2. Tested to EIA/JESD22–A115–A. 3. Tested to JESD22–C101–A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free–Air Temperature
t/
V Input Transition Rise or Fall Rate Switch I/O Operating, Data Retention Only Min Max Unit 4.0 5.5 V (Note ) 0 5.5 V (HIGH or LOW State) 0 5.5 V 40 85
C DC 5 ns/V 0 Switch Control Input VCC = 5.0 V
0.5 V 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 3 74FST3253 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions IIN = 18mA VCC TA = 40
C to
85
C (V) Min Typ* 4.5 Max Unit 1.2 V VIK Clamp Diode Resistance VIH High–Level Input Voltage VIL Low–Level Input Voltage 4.0 to 5.5 0.8 V II Input Leakage Current 0  VIN  5.5 V 5.5
1.0 A IOZ OFF–STATE Leakage Current 0  A, B  VCC 5.5
1.0 A RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7  VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 4.0 to 5.5 2.0 V VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 A
ICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25
C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. AC ELECTRICAL CHARACTERISTICS TA = 40
C to
85
C CL = 50 pF, RU = RD = 500  VCC = 4.5–5.5 V Symbol tPHL, tPLH Parameter Prop Delay Bus to Bus (Note 7) Conditions Min Prop Delay, Select to Bus A tPZH, tPZL tPHZ, tPLZ Max Unit 0.25 0.25 ns 1.0 5.3 6.3 VI = OPEN Max VCC = 4.0 V Min Output Enable Time, Select to Bus B VI = 7 V for tPZL 1.0 5.3 6.0 Output Enable Time, IOE to Bus A, B VI = OPEN for tPZH 1.0 5.3 6.2 Output Disable Time, Select to Bus B VI = 7 V for tPLZ 1.0 5.8 6.2 Output Disable Time, IOE to Bus A, B VI = OPEN for tPHZ 1.0 5.5 6.2 ns ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O A Port Input/Output Capacitance VCC, OE = 5.0 V 13 pF CI/O B Port Input/Output Capacitance VCC, OE = 5.0 V 5 pF 8. TA = 25
C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 4 74FST3253 AC Loading and Waveforms VI 500  FROM OUTPUT UNDER TEST CL * 500  NOTES: 1. Input driven by 50  source terminated in 50 . 2. CL includes load and stray capacitance. *CL = 50 pF Figure 4. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 3.0 V 90 % 1.5 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V 1.5 V OUTPUT VOL Figure 5. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % tPZL OUTPUT 3.0 V GND tPZL 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 6. Enable/Disable Delays http://onsemi.com 5 VOH – 0.3 V 74FST3253 PACKAGE DIMENSIONS SO–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K DIM A B C D F G J K M P R F X 45
C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B A S S MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0
7
5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0
7
0.229 0.244 0.010 0.019 TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE DETAIL E H D G http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0
8
INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0
8
74FST3253 PACKAGE DIMENSIONS QSOP–16 QS SUFFIX CASE 492–01 ISSUE O –A– Q R H x 45
U RAD. 0.013 X 0.005 DP. MAX –B– MOLD PIN MARK RAD. 0.005–0.010 TYP G L 0.25 (0.010) M P T DETAIL E V K C N 8 PL –T– D 16 PL 0.25 (0.010) SEATING PLANE M T B S A S J M F DETAIL E http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.189 0.196 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0
8
N 0
7
P 0.007 0.011 Q 0.020 DIA R 0.025 0.035 U 0.025 0.035 8
V 0
MILLIMETERS MAX MIN 4.80 4.98 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0
8
0
7
0.18 0.28 0.51 DIA 0.64 0.89 0.64 0.89 0
8
74FST3253 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 74FST3253/D