74HC02

74HC02 Quad 2−Input NOR Gate High−Performance Silicon−Gate CMOS The 74HC02 is identical in pinout to the LS02. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features http://onsemi.com MARKING DIAGRAMS 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 HC02G AWLYWW • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 40 FETs or 10 Equivalent Gates These are Pb−Free Devices LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 2 3 5 6 8 9 11 12 PIN 14 = VCC PIN 7 = GND 1 Y1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 HC 02 ALYW G G 4 Y2 Y=A+B HC02 = Device Code A = Assembly Location WL or L = Wafer Lot Y = Year WW or W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) 10 Y3 13 Y4 FUNCTION TABLE Inputs A L L H H B L H L H Output Y H L L L PIN ASSIGNMENT Y1 A1 B1 Y2 A2 B2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC Y4 B4 A4 Y3 B3 A3 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: 74HC02/D 74HC02 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol VCC Vin Iin Iout ICC PD Tstg TL Vout Parameter Value Unit V V V mA mA mA mW _C _C 260 DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) – 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ±20 ±25 ±50 500 450 – 65 to + 150 DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 – 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns http://onsemi.com 2 74HC02 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 ±1.0 20 Symbol VIH Parameter Test Conditions VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 3.0 4.5 6.0 6.0 6.0 – 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 ±0.1 2.0 v 125°C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.20 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 ±1.0 40 mA mA V Unit V Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL V VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND |Iout| = 0 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 — – 55 to 25_C 75 30 15 13 75 30 15 13 10 v 85_C 95 40 19 16 95 40 19 16 10 v 125_C 110 55 22 19 110 55 22 19 10 Unit ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) ns Cin Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Gate)* 2f 22 pF * Used to determine the no −load dynamic power consumption: PD = CPD VCC ON Semiconductor High−Speed CMOS Data Book (DL129/D). + ICC VCC. For load considerations, see Chapter 2 of the http://onsemi.com 3 74HC02 ORDERING INFORMATION Device 74HC02DR2G 74HC02DTR2G Package SOIC−14 (Pb−Free) TSSOP−14* Shipping † 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. tf INPUT A OR B 90% 50% 10% tPLH OUTPUT Y tTLH 90% 50% 10% tr TEST POINT VCC GND tPHL DEVICE UNDER TEST OUTPUT C L* tTHL *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit A Y B Figure 3. Expanded Logic Diagram (1/4 of the Device) http://onsemi.com 4 74HC02 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H − A− 14 8 − B− P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C −T− SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 74HC02 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V N S 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B − U− N F DETAIL E K 0.15 (0.006) T U S J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 14X 14X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ K1 0.65 PITCH DIMENSIONS: MILLIMETERS 74HC02 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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