74HCT14

74HCT14 Hex Schmitt−Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The 74HCT14 may be used as a level converter for interfacing TTL or NMOS outputs to high−speed CMOS inputs. The HCT14 is useful to “square up” slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the HCT14 finds applications in noisy environments. Features 14 1 http://onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 1 HCT14G AWLYWW • • • • • • • • • Output Drive Capability: 10 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance With the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are Pb−Free Devices 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 HCT 14 ALYW G G HCT14 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: 74HCT14/D 74HCT14 PIN ASSIGNMENT A1 Y1 A2 Y2 A3 Y3 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A6 Y6 A5 Y5 A4 Y4 A4 9 8 Y4 A3 5 6 Y3 A2 LOGIC DIAGRAM A1 1 2 Y1 3 4 Y2 FUNCTION TABLE Input A L H Output Y H L A5 11 10 Y5 A6 13 12 Y6 Y=A PIN 14 = VCC PIN 7 = GND ORDERING INFORMATION Device 74HCT14DR2G 74HCT14DTR2G Package SOIC−14 (Pb−Free) TSSOP−14* Shipping † 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74HCT14 MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD ILatchup DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Latchup Performance Oxygen Index: 30% − 35% Human Body Model (Note 1) Machine Model (Note 2) Above VCC and Below GND at 85_C (Note 3) SOIC TSSOP SOIC TSSOP Parameter (Referenced to GND) (Referenced to GND) (Referenced to GND) Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 to VCC )0.5 $20 $25 $25 $50 $50 *65 to )150 260 )150 125 170 500 450 Level 1 UL 94 V−0 @ 0.125 in >2000 >200 $300 V mA Unit V V V mA mA mA mA mA _C _C _C _C/W mW Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to EIA/JESD78. 4. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC VI, VO TA tr, tf DC Supply Voltage DC Input Voltage, Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Parameter (Referenced to GND) (Referenced to GND) Min 4.5 0 *55 − Max 5.5 VCC )125 (Note 5) Unit V V _C ns 5. No Limit when VI [ 50% VCC, ICC > 1 mA. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 3 74HCT14 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Temperature Limit VCC Symbol VT)max VT)min VT*max VT*min VH max VH min VOH Parameter Maximum Positive−Going Input Threshold Voltage Minimum Positive−Going Input Threshold Voltage Maximum Negative−Going Input Threshold Voltage Minimum Negative−Going Input Threshold Voltage Maximum Hysteresis Voltage Minimum Hysteresis Voltage Minimum High−Level Output Voltage Test Conditions VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VO = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VI < VT*min |Iout| v 20 mA VI < VT*min |Iout| v 4.0 mA VOL Maximum Low−Level Output Voltage VI ≥ VT)max |Iout| v 20 mA VI ≥ VT)max |Iout| v 4.0 mA IIK ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per package) VI = VCC or GND VI = VCC or GND Iout = 0 mA (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 0.4 0.4 4.4 5.4 3.98 0.1 0.1 0.26 $0.1 2.0 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.84 0.1 0.1 0.33 $1.0 20 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 04 4.4 5.4 3.7 0.1 0.1 0.4 $1.0 40 mA mA V V *55_C to 25_C Min Max 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 v85_C Min Max 1.9 2.1 1.2 1.4 1.2 1.4 v125_C Min Max 1.9 2.1 Unit V V w*55_C DICC Additional Quiescent Supply Current VI = 2.4 V, Any One Input VI = VCC or GND, Other Inputs lout = 0 mA 5.5 2.9 25_C to 125_C 2.4 mA 7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns) Guaranteed Limit *55_C to 25_C Symbol Parameter Test Conditions Figures Min Max v85_C Min Max v125_C Min Max Unit tPLH, tPHL tTLH, tTHL Maximum Propagation Delay, Input A to Output Y (L to H) Maximum Output Transition Time, Any Output VCC = 5.0 V $10% CL = 50 pF, Input tr = tf = 6.0 ns VCC = 5.0 V $10% CL = 50 pF, Input tr = tf = 6.0 ns 1&2 32 40 48 ns 1&2 15 19 22 ns 8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance, per Inverter (Note 9) 2f 32 pF 9. Used to determine the no−load dynamic power consumption: P D = CPD VCC Semiconductor High−Speed CMOS Data Book (DL129/D). + ICC VCC . For load considerations, see the ON http://onsemi.com 4 74HCT14 tf INPUT A 2.7 V 1.3 V 0.3 V tr 3V GND tPLH 90% 1.3 V 10% tPHL OUTPUT Y tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance. Figure 2. Test Circuit http://onsemi.com 5 74HCT14 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H − A− 14 8 − B− P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C −T− SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 74HCT14 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V N S 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B − U− N F DETAIL E K K1 J J1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ S A −V− SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 14X 14X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ 0.65 PITCH DIMENSIONS: MILLIMETERS 74HCT14 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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