74HCT157DR2G

74HCT157 Quad 2−Input Data Selectors / Multiplexers High−Performance Silicon−Gate CMOS The 74HCT157 is identical in pinout to the LS157. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninverted form. A high level on the Output Enable input sets all four Y outputs to a low level. Features 16 1 http://onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F 1 74HCT157 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) HCT 157 ALYWG G HCT157G AWLYWW • • • • • • • • • • Output Drive Capability: 10 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 82 FETs or 20.5 Equivalent Gates These are Pb−Free Devices ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: 74HCT157/D 74HCT157 A0 NIBBLE A INPUTS A1 A2 A3 B0 NIBBLE B INPUTS B1 B2 B3 SELECT OUTPUT ENABLE 2 5 11 14 3 6 10 13 1 15 PIN 16 = VCC PIN 8 = GND 4 7 9 12 Y0 Y1 Y2 Y3 DATA OUTPUTS SELECT A0 B0 Y0 A1 B1 Y1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OUTPUT ENABLE A3 B3 Y3 A2 B2 Y2 Figure 1. Pin Assignment Figure 2. Logic Diagram FUNCTION TABLE Inputs Output Enable H L L Select X L H Outputs Y0 − Y3 L A0 − A3 B0 − B3 X = don’t care A0 − A3, B0 − B3 = the levels of the respective Data−Word Inputs. ORDERING INFORMATION Device 74HCT157DR2G 74HCT157DTR2G Package SOIC−16 (Pb−Free) TSSOP−16* Shipping † 2500 Units / Reel 2500 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74HCT157 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol VCC Vin Iin Iout ICC PD Tstg TL Vout Parameter Value Unit V V V mA mA mA mW _C _C DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) – 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ±20 ±25 ±50 500 450 – 65 to + 150 260 DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 4.5 0 – 55 0 0 0 Max 5.5 VCC + 125 1000 500 400 Unit V V _C ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH VIL VOH Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage Condition Vout = 0.1V |Iout| ≤ 20mA Vout = VCC − 0.1V |Iout| ≤ 20mA Vin = VIL |Iout| ≤ 20mA Vin = VIL VOL Maximum Low−Level Output Voltage Vin = VIH |Iout| ≤ 20mA Vin = VIH Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current Vin = VCC or GND Vin = VCC or GND Iout = 0mA Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0mA |Iout| ≤ 4.0mA |Iout| ≤ 4.0mA VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 Guaranteed Limit −55 to 25°C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 4.0 ≤85°C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 40 ≤125°C 2.0 2.0 0.8 0.8 4.4 5.4 3.70 0.1 0.1 0.40 ±1.0 40 mA mA V Unit V V V DICC ≥ −55°C 5.5 2.9 25 to 125°C 2.4 mA 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + ΣDICC. http://onsemi.com 3 74HCT157 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 4) Maximum Propagation Delay, Select to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance VCC (V) 4.5 4.5 4.5 4.5 − – 55 to 25_C 21 22 20 15 10 v 85_C 26 28 25 19 10 v 125_C 32 33 30 22 10 Unit ns ns ns ns pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 2f + I CC 33 pF * Used to determine the no −load dynamic power consumption: PD = CPD VCC ON Semiconductor High−Speed CMOS Data Book (DL129/D). VCC . For load considerations, see Chapter 2 of the http://onsemi.com 4 74HCT157 PIN DESCRIPTIONS INPUTS A0, A1, A2, A3 (Pins 2, 5, 11, 14) Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form. B0, B1, B2, B3 (Pins 3, 6, 10, 13) The data present on these pins is in its noninverted form. For the Output Enable input at a high level, the outputs are at a low level. CONTROL INPUTS Select (Pin 1) Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form. OUTPUTS Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12) Nibble select. This input determines the data word to be transferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs. Output Enable (Pin 15) Output Enable input. A low level on this input allows the selected input data to be presented at the outputs. A high level on this input sets all outputs to a low level. Data outputs. The selected input Nibble is presented at these outputs when the Output Enable input is at a low level. SWITCHING WAVEFORMS tr INPUT A OR B tPLH OUTPUT Y tTLH 90% 50% 10% tTHL 90% 50% 10% tf VCC tPHL GND tr SELECT tPLH OUTPUT Y tTLH 90% 50% 10% tTHL 90% 50% 10% tf VCC tPHL GND Figure 3. HCT157 tr OUTPUT ENABLE tPHL OUTPUT Y tTHL 90% 50% 10% 90% 50% 10% Figure 4. Y versus Selected, Noninverted tf VCC GND tPLH tTLH Figure 5. HCT157 TEST POINT OUTPUT DEVICE UNDER TEST C L* *Includes all probe and jig capacitance Figure 6. Test Circuit http://onsemi.com 5 74HCT157 EXPANDED LOGIC DIAGRAM A0 B0 A1 B1 A2 B2 A3 B3 OUTPUT ENABLE SELECT 2 3 5 6 11 10 14 13 15 1 12 Y3 9 Y2 7 Y1 DATA OUTPUTS 4 Y0 NIBBLE OUTPUTS http://onsemi.com 6 74HCT157 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K − A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 − B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S SOLDERING FOOTPRINT* 6.40 16X 8X 1.12 16 1 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 74HCT157 PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K 2X L/2 16 9 J1 B − U− SECTION N−N J N L PIN 1 IDENT. 1 8 0.15 (0.006) T U S A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 16X 16X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ 0.25 (0.010) M K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −W− 0.65 PITCH DIMENSIONS: MILLIMETERS 74HCT157 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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