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74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26: Series Resistors
General Description
Features
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit operation.
■ 5V tolerant inputs and outputs
The LCX162374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment. The 26: series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
■ Supports live insertion/withdrawal (Note 1)
■ 2.3V–3.6V VCC specifications provided
■ Equivalent 26: series resistor on outputs
■ 7.0 ns tPD max (VCC
3.3V), 20 PA ICC max
■ Power down high impedance inputs and outputs
■ r12 mA output drive (VCC
3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX162374GX
(Note 2)
Package Number
BGA54A
(Preliminary)
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCX162374MEA
(Note 3)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500442
www.fairchildsemi.com
74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
February 2001
Revised May 2005
74LCX162374
Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
I0–I15
Inputs
O0–O15
Outputs
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC
OE1
CP1
NC
I0
B
O2
O1
NC
NC
I1
I2
C
O4
O3
VCC
VCC
I3
I4
D
O6
O5
GND
GND
I5
I6
E
O8
O7
GND
GND
I7
I8
F
O10
O9
GND
GND
I9
I10
I12
G
O12
O11
VCC
VCC
I11
H
O14
O13
NC
NC
I13
I14
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Pin Assignment for FBGA
Inputs
Outputs
OE1
I0–I7
O0–O7
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
CP1
Inputs
CP2
(Top Thru View)
H
L
X
Z
O0
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2
Outputs
OE2
I8–I15
O8–O15
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Previous O0 before HIGH-to-LOW of CP
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LCX162374
Functional Description
74LCX162374
Absolute Maximum Ratings(Note 4)
Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Value
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
0.5 to VCC 0.5
50
50
50
r50
r100
r100
65 to 150
Units
V
V
3-STATE
Output in HIGH or LOW State (Note 5)
VI GND
V
mA
VO GND
mA
VO ! VCC
mA
mA
mA
qC
Recommended Operating Conditions (Note 6)
Symbol
VCC
Parameter
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
Supply Voltage
Output Current
TA
Free-Air Operating Temperature
't/'V
Input Edge Rate, VIN
0.8V–2.0V, VCC
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC
3.0V 3.6V
VCC
2.7V 3.0V
VCC
2.3V 2.7V
3.0V
r12
r8
r4
Units
V
V
V
mA
40
85
qC
0
10
ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
TA
40qC to 85qC
(V)
Min
2.3 2.7
1.7
2.7 3.6
2.0
Max
Units
V
2.3 2.7
0.7
2.7 3.6
0.8
V
IOH
100 PA
2.3 3.6
VCC 0.2
IOH
4 mA
2.3
1.8
IOH
4 mA
2.7
2.2
IOH
6 mA
3.0
2.4
IOH
8 mA
2.7
2.0
IOH
12 mA
3.0
2.0
IOL
100 PA
2.3 3.6
0.2
IOL
4 mA
2.3
0.6
IOL
4 mA
2.7
0.4
IOL
6 mA
3.0
0.55
IOL
8 mA
2.7
0.6
IOL
12 mA
3.0
0.8
2.3 3.6
r5.0
PA
2.3 3.6
r5.0
PA
II
Input Leakage Current
0 d VI d 5.5V
IOZ
3-STATE Output Leakage
0 d VO d 5.5V
VI
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VCC
VIH or VIL
4
V
V
Symbol
(Continued)
Parameter
VCC
Conditions
(V)
IOFF
Power-Off Leakage Current
VI or VO
ICC
Quiescent Supply Current
VI
5.5V
V CC or GND
3.6V d VI, VO d 5.5V (Note 7)
'ICC
Increase in ICC per Input
VIH
VCC 0.6V
40qC to 85qC
TA
Min
Units
Max
0
10
2.3 3.6
20
2.3 3.6
r20
2.3 3.6
500
PA
PA
PA
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA
Symbol
Parameter
VCC
50 pF
CL
Min
CL
2.7V
50 pF
500:
VCC
CL
2.5V r 0.2V
Min
Max
Min
Max
1.5
7.0
1.5
7.3
1.5
8.4
CP to On
1.5
7.0
1.5
7.3
1.5
8.4
Output Enable time
1.5
6.9
1.5
7.1
1.5
9.0
1.5
6.9
1.5
7.1
1.5
9.0
1.5
6.0
1.5
6.2
1.5
7.2
1.5
6.0
1.5
6.2
1.5
7.2
Maximum Clock Frequency
170
tPHL
Propagation Delay
tPLH
tPZL
tPZH
Output Disable Time
tPHZ
Units
30 pF
Max
fMAX
tPLZ
40q to 85qC, RL
3.3V r 0.3V
VCC
MHz
ns
ns
ns
tS
Setup Time
2.5
2.5
3.0
ns
tH
Hold Time
1.5
1.5
2.0
ns
tW
Pulse Width
3.0
3.0
3.5
ns
tOSHL
Output to Output Skew (Note 8)
1.0
ns
1.0
tOSLH
Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
Conditions
TA
25qC
(V)
Typical
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.35
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.25
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.35
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.25
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, VI
COUT
Output Capacitance
VCC
3.3V, VI
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, VI
0V or VCC, f
5
0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
20
pF
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74LCX162374
DC Electrical Characteristics
74LCX162374
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V, and 2.7V
VCC x 2 at VCC 2.5 r 0.2V
tPZH, tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
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VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
6
74LCX162374
Schematic Diagram Generic for LCX Family
7
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74LCX162374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
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8
74LCX162374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
9
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74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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10
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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