74LCX16500G

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This literature is subject to all applicable copyright laws and is not for resale in any manner. Revised June 2002 74LCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs General Description Features These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. ■ 5V tolerant inputs and outputs Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LCX16500 is designed for low voltage (2.5V or 3.3V) VCC applications with the capability of interfacing to a 5V signal environment. The LCX16500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power. ■ 2.3V–3.6V VCC specifications provided ■ 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Uses proprietary noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX16500G (Note 2)(Note 3) Package Number BGA54A 74LCX16500MEA (Note 3) MS56A 74LCX16500MTD (Note 3) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS012407 www.fairchildsemi.com 74LCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs March 1995 74LCX16500 Connection Diagrams Pin Descriptions Pin Names Pin Assignment for SSOP and TSSOP Description A1 - A18 Data Register A Inputs/3-STATE Outputs B1 - B18 Data Register B Inputs/3-STATE Outputs CLKAB, CLKBA Clock Pulse Inputs LEAB, LEBA Latch Enable Inputs OEBA, OEBA Output Enable Inputs FBGA Pin Assignments 1 2 3 4 5 6 A A2 A1 OEAB GND B1 B2 B A4 A3 LEAB CLKAB B3 B4 C A6 A5 VCC VCC B5 B6 D A8 A7 GND GND B7 B8 E A10 A9 GND GND B9 B10 F A12 A11 GND GND B11 B12 G A14 A13 VCC VCC B13 B14 H A16 A15 OEBA CLKBA B15 B16 J A17 A18 LEBA B18 B17 GND Truth Table (Note 4) Inputs OEAB Pin Assignment for FBGA LEAB Output CLKAB An Bn Z L X X X H H X L L H H X H H H L ↓ L L H L ↓ H H H L H X B0 (Note 5) H L L X B0 (Note 6) Note 4: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. Functional Description For A-to-B data flow, the LCX16500 operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-HIGH. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high impedance state. (Top Thru View) Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). www.fairchildsemi.com 2 74LCX16500 Logic Diagram 3 www.fairchildsemi.com 74LCX16500 Absolute Maximum Ratings(Note 7) Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 8) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 9) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Max 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 Output Current ∆t/∆V Min Operating VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 7: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 8: IO Absolute Maximum Rating must be observed. Note 9: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 Units V VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = VIH or VIL IOFF Power-Off Leakage Current www.fairchildsemi.com VI or VO = 5.5V 4 Symbol (Continued) Parameter VCC Conditions (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input TA = −40°C to +85°C Min Units Max VI = V CC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 10) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 10: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 1.5 6.0 1.5 7.0 1.5 7.2 Bus to Bus 1.5 6.0 1.5 7.0 1.5 7.2 fMAX Maximum Clock Frequency 170 tPHL Propagation Delay tPLH MHz tPHL Propagation Delay 1.5 6.7 1.5 8.0 1.5 8.4 tPLH Clock to Bus 1.5 6.7 1.5 8.0 1.5 8.4 tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 tPLH LE to Bus 1.5 7.0 1.5 8.0 1.5 8.4 tPZL Output Enable Time 1.5 7.2 1.5 8.2 1.5 9.4 1.5 7.2 1.5 8.2 1.5 9.4 1.5 7.0 1.5 8.0 1.5 8.4 1.5 7.0 1.5 8.0 1.5 8.4 tPZH tPLZ Output Disable Time tPHZ Units ns ns ns ns ns tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew 1.0 tOSLH (Note 11) 1.0 ns Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH =2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH =2.5V, VIL = 0V 2.5 −0.6 Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF 5 www.fairchildsemi.com 74LCX16500 DC Electrical Characteristics 74LCX16500 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 6 74LCX16500 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCX16500 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8 74LCX16500 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 9 www.fairchildsemi.com 74LCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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