Revised March 2005
74LCX240
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Description
Features
The LCX240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver. The
device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
The LCX240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V VCC specifications provided
■ 6.5 ns tPD max (VCC
3.3V), 10 PA ICC max
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ r24 mA output drive (VCC
3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package
Package Description
Number
74LCX240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX240SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX240MSA
MSA20
74LCX240MTC
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX240MTCX_NL
(Note 2)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
© 2005 Fairchild Semiconductor Corporation
Connection Diagram
DS011993
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74LCX240 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
February 1994
74LCX240
Pin Descriptions
Pin Names
Description
OE1, OE2
3-STATE Output Enable Inputs
I0–I7
Inputs
O0–O7
Outputs
Truth Tables
Inputs
Outputs
OE1
In
(Pins 12, 14, 16, 18)
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE2
In
(Pins 3, 5, 7, 9)
L
L
H
L
H
L
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
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Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Value
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
0.5 to VCC 0.5
50
50
50
r50
r100
r100
65 to 150
Units
V
V
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
VI GND
V
mA
VO GND
mA
VO ! VCC
mA
mA
mA
qC
Recommended Operating Conditions (Note 5)
Symbol
VCC
Parameter
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
Supply Voltage
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
Output Current
TA
Free-Air Operating Temperature
't/'V
Input Edge Rate, VIN
0.8V–2.0V, VCC
VCC
3.0V 3.6V
VCC
2.7V 3.0V
VCC
2.3V 2.7V
r24
r12
r8
Units
V
V
V
mA
40
85
qC
0
10
ns/V
3.0V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
IOH
100PA
IOH = -8 mA
VOL
LOW Level Output Voltage
40qC to 85qC
Min
2.3 2.7
1.7
2.7 3.6
2.0
0.7
0.8
2.3 3.6
VCC - 0.2
2.3
1.8
2.2
IOH
18 mA
3.0
2.4
3.0
2.2
24 mA
IOL
100PA
0.2
IOL = 8mA
2.3
0.6
IOL
12 mA
2.7
0.4
IOL
16 mA
3.0
0.4
IOL
24 mA
IOFF
Power-Off Leakage Current
VI or VO
ICC
Quiescent Supply Current
VI
3.0
0.55
r5.0
PA
10
PA
2.3 3.6
10
3.6V d VI, VO d 5.5V (Note 6)
2.3 3.6
r10
VIH
2.3 3.6
500
VCC
0.6V
3
V
2.3 3.6
5.5V
VCC or GND
V
V
2.3 3.6
0 d VI d 5.5V
Units
V
2.7 3.6
2.7
IOH
Max
2.3 2.7
12 mA
Input Leakage Current
Increase in ICC per Input
TA
(V)
IOH
II
'ICC
VCC
PA
PA
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74LCX240
Absolute Maximum Ratings(Note 3)
74LCX240
DC Electrical Characteristics
(Continued)
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA
Symbol
tPHL
Parameter
Propagation Delay
tPLH
tPZL
Output Enable Time
tPZH
tPLZ
Output Disable Time
tPHZ
tOSHL
VCC
CL
40qC to 85qC, RL
3.3V r 0.3V
50 pF
VCC
2.7V
CL
50 pF
500:
VCC
CL
2.5V r 0.2V
30 pF
Min
Max
Min
Max
Min
Max
1.5
6.5
1.5
7.5
1.5
7.8
1.5
6.5
1.5
7.5
1.5
7.8
1.5
8.0
1.5
9.0
1.5
10.0
1.5
8.0
1.5
9.0
1.5
10.0
1.5
7.0
1.5
8.0
1.5
8.4
1.5
7.0
1.5
8.0
1.5
8.4
Output to Output Skew (Note 7)
1.0
tOSLH
Units
ns
ns
ns
ns
1.0
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
Conditions
TA
25qC
(V)
Typical
0.8
CL
50 pF, VIH
3.3V, VIL
0V
3.3
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, VI
COUT
Output Capacitance
VCC
3.3V, VI
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, VI
0V or VCC, f
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4
0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
25
pF
74LCX240
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V
VCC x 2 at VCC 2.5 r 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns)
Symbol
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
5
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74LCX240
Schematic Diagram Generic for LCX Family
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6
74LCX240
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74LCX240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74LCX240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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74LCX240 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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