74LCX373MTCX

74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Features General Description ■ 5V tolerant inputs and outputs The LCX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage applications with capability of interfacing to a 5V signal environment. ■ 2.3V–3.6V VCC specifications provided ■ 8.0ns tPD max (VCC = 3.3V), 10µA ICC max ■ Power down high impedance inputs and outputs The LCX373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ Supports live insertion/withdrawal1 ■ ±24mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance – Human body model > 2000V – Machine model > 200V ■ Leadless Pb-Free DQFN package Ordering Information Order Number Package Number Package Description 74LCX373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX373SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX373BQX2 MLP020B 74LCX373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX373MTCX_NL3 MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Notes: 1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. 2. DQFN package available in Tape and Reel only. 3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. ©2006 Fairchild Semiconductor Corporation 74LCX373 Rev. 2.0.0 1 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs February 2006 Pin Descriptions Pin Names Description D0 D1 D2 D3 D4 D5 D6 D7 LE D0–D7 Data Inputs OE O0 O1 O2 O3 O4 O5 O6 O7 LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs IEEE/IEC OE LE EN C1 D0 D1 D2 D3 D4 D5 D6 D7 1D Truth Table Inputs O0 O1 O2 O3 O4 O5 O6 O7 Pin Assignments for SOIC, SOP, SSOP, TSSOP 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Dn On X H X Z H L L L H L H H L L X O0 The LCX373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. OE VCC 20 O0 2 19 O7 D0 3 18 D7 D1 4 17 D6 O1 5 16 O6 O2 6 15 O5 D2 7 14 D5 D3 8 13 D4 O3 9 12 O4 10 OE Functional Description VCC O7 D7 D6 O6 O5 D5 D4 O4 LE Pad Assignments for DQFN 1 LE H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Connection Diagrams OE O0 D0 D1 O1 O2 D2 D3 O3 GND Outputs 11 GND LE (Top View) 2 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Logic Symbols D0 D1 D D2 D G O D3 D G O D4 D G O D5 D G O D6 D G O D7 D G O D G O G O LE OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Logic Diagram The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Symbol Parameter Conditions Value Units VCC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 to +7.0 V VO DC Output Voltage −0.5 to +7.0 V Output in 3-STATE Output in HIGH or LOW State4 −0.5 to VCC + 0.5 IIK DC Input Diode Current VI < GND −50 mA IOK DC Output Diode Current VO < GND −50 mA VO > VCC +50 IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions5 Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH / IOL Output Current TA Free-Air Operating Temperature ∆t / ∆V Input Edge Rate Min. Max. Units Operating Conditions 2.0 3.6 V Data Retention 1.5 3.6 0 5.5 V HIGH or LOW State 0 VCC V 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 VIN = 0.8V − 2.0V, VCC = 3.0V mA −40 85 °C 0 10 ns /V Notes: 4. IO Absolute Maximum Rating must be observed. 5. Unused inputs must be held HIGH or LOW. They may not float. 4 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Absolute Maximum Ratings TA = −40°C to +85°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL HIGH Level Output Voltage LOW Level Output Voltage Conditions IOH = −100 µA VCC (V) Min. 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max. Units V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA V V 2.3 − 3.6 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 5.5V, VI = VIH or VIL 2.3 − 3.6 ±5.0 µA IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA ICC Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 10 µA 3.6V ≤ VI, VO ≤ 2.3 − 3.6 ±10 2.3 − 3.6 500 ∆ICC Increase in ICC per Input 5.5V6 VIH = VCC −0.6V µA AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5 ± 0.2V CL = 50pF CL = 50pF CL = 30pF Parameter Min. Max. Min. Max. Min. Max. Units tPHL, tPLH Propagation Delay, Dn to On 1.5 8.0 1.5 9.0 1.5 9.6 ns tPHL, tPLH Propagation Delay, LE to On 1.5 8.5 1.5 9.5 1.5 10.5 ns tPZL, tPZH Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns tPLZ, tPHZ Output Disable Time 1.5 7.5 1.5 8.5 1.5 9.0 ns tS Setup Time, Dn to LE 2.5 2.5 4.0 ns tH Hold Time, Dn to LE 1.5 1.5 2.0 ns tW LE Pulse Width 3.3 3.3 4.0 ns Symbol tOSHL, tOSLH Output to Output Skew7 1.0 ns Notes: 6. Outputs disabled or 3-STATE only. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL) or LOW-to-HIGH (tOSLH). 5 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs DC Electrical Characteristics TA = 25°C Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions VCC (V) Typical Units V CL = 50pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30pF, VI = 2.5V, VIL = 0V 2.5 0.6 CL = 50pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30pF, VI = 2.5V, VIL = 0V 2.5 −0.6 V Capacitance Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25 pF 6 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Dynamic Switching Characteristics 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs AC Loading and Waveforms (Generic for LCX Family) VCC OPEN 500Ω TEST SIGNAL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ GND DUT VI CL 500Ω Figure 1. AC Test Circuit (CL includes probe and jig capacitance) DATA IN Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND VCC Vmi tpxx OUTPUT CONTROL GND DATA OUT DATA OUT Vmo tW DATA IN VCC Vmi tS tPLH Vmo Vmo OUTPUT CONTROL Vmi tPZL tPLZ Vmo VCC GND VCC GND trec MR OR CLEAR Vmi Setup Time, Hold Time and Recovery Time for Logic Propagation Delay, Pulse Width and trec Waveforms DATA OUT Vmi tS tPHL tH CONTROL INPUT Vmi OUTPUT Vmi GND trec CLOCK VOH VY Vmo 3-STATE Output High Enable and Disable Times for Logic Waveform for Inverting and Non-Inverting Functions CONTROL IN GND tPHZ tPZH tpxx VCC Vmi tr VCC tf GND ANY OUTPUT VX VOL 90% 90% 10% 10% VOH VOL trise and tfall 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC / 2 Vmo 1.5V 1.5V VCC / 2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 7 74LCX373 Rev. 2.0.0 www.fairchildsemi.com Input Stage P2 P1 VCC Data ESD P5 D2 N+/P– X1 VDD N1 N2 GTO™ Output Input Stage D6 N+/P– P4 P3 N5 Enable N4 ESD D4 N+/P– N3 8 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Schematic Diagram (Generic for LCX Family) Tape Format for DQFN Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (typ) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12 mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) 9 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Tape and Reel Specification 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 10 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 11 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B 12 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 13 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 14 74LCX373 Rev. 2.0.0 www.fairchildsemi.com The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I18 15 74LCX373 Rev. 2.0.0 www.fairchildsemi.com 74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs TRADEMARKS