74LCX540MTC

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This literature is subject to all applicable copyright laws and is not for resale in any manner. 74LCX540 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Features General Description ■ 5V tolerant input and outputs The LCX540 is an octal buffer/line driver designed to be employed as a memory and address driver, clock driver and bus oriented transmitter/receiver. ■ 2.3V–3.6V VCC specifications provided ■ 6.5ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal(1) ■ Implements proprietary noise/ EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance – Human body model > 2000V – Machine model > 200V ■ Leadless DQFN package Note: 1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is similar in function to the LCX240 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. The LCX540 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX540 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Information Package Number Package Description 74LCX540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74LCX540BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 74LCX540MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs December 2013 Logic Symbol Pin Assignments for SOIC, SOP, SSOP, TSSOP OE1 I0 I1 I2 I3 I4 I5 I6 I7 GND 1 20 2 19 3 18 4 17 5 16 6 7 15 14 8 13 9 12 10 11 IEEE/IEC VCC OE2 O0 O1 O2 O3 O4 O5 O6 O7 EN I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7 Truth Table Pad Assignment for DQFN Inputs OE1 VCC 1 & OE1 OE2 20 OE1 OE2 I On L L H L H X X Z X H X Z L L L H I0 2 19 OE2 I1 3 18 O0 I2 4 17 O1 I3 5 16 O2 I4 6 15 O3 I5 7 14 O4 L = LOW Voltage Level I6 8 13 O5 X = Immaterial I7 9 12 O6 Z = High Impedance 10 Outputs H = HIGH Voltage Level 11 GND O7 (Bottom View) (Top View) Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs DAP No Connect Note: DAP (Die Attach Pad) ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 2 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Connection Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Value Units Supply Voltage –0.5 to +7.0 V VI DC Input Voltage –0.5 to +7.0 V VO DC Output Voltage –0.5 to +7.0 V VCC Parameter Conditions Output in 3-STATE Output in HIGH or LOW State(3) –0.5 to VCC + 0.5 IIK DC Input Diode Current VI < GND –50 mA IOK DC Output Diode Current VO < GND –50 mA VO > VCC +50 IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature –65 to +150 °C Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH / IOL Output Current Conditions Min. Max. Units Operating 2.0 3.6 V Data Retention 1.5 3.6 0 5.5 V HIGH or LOW State 0 VCC V 3-STATE 0 5.5 VCC = 3.0V – 3.6V ±24 VCC = 2.7V – 3.0V ±12 VCC = 2.3V – 2.7V TA ∆t / ∆V Free-Air Operating Temperature Input Edge Rate VIN = 0.8V – 2.0V, VCC = 3.0V mA ±8 –40 85 °C 0 10 ns / V Notes: 3. IO Absolute Maximum Rating must be observed. 4. Unused inputs or I/O’s must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 3 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Absolute Maximum Ratings TA = –40°C to +85°C Symbol VIH VIL VOH VOL Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage VCC (V) Conditions Min. 2.3–2.7 1.7 2.7–3.6 2.0 Max. V 2.3–2.7 0.7 2.7–3.6 0.8 2.3–3.6 IOH = –100µA V VCC – 0.2 2.3 IOH = –8mA 1.8 2.7 IOH = –12mA 2.2 3.0 IOH = –18mA 2.4 IOH = –24mA 2.2 V IOL = 100µA 0.2 2.3 IOL = 8mA 0.6 2.7 IOL = 12mA 0.4 3.0 IOL = 16mA 0.4 IOL = 24mA 0.55 2.3–3.6 Units V Input Leakage Current 2.3–3.6 0 ≤ VI ≤ 5.5V ±5.0 µA IOZ 3-STATE Output Voltage 2.3–3.6 0 ≤ VO ≤ 5.5V, VI = VIH or VIL ±5.0 µA IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA ICC Quiescent Supply Current µA II ∆ICC Increase in ICC per Input 2.3–3.6 2.3–3.6 VI = VCC or GND 10 3.6V ≤ VI, VO ≤ 5.5V(5) ±10 VIH = VCC – 0.6V 500 µA AC Electrical Characteristics TA = –40°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.3V, CL = 50pF Symbol Parameter VCC = 2.7V, CL = 50pF VCC = 2.5V ± 0.2V, CL = 30pF Min. Max. Min. Max. Min. Max. Units tPHL, tPLH Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns tPZL, tPZH Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns tPLZ, tPHZ Output Disable Time 1.5 7.5 1.5 8.5 1.5 9.0 ns tOSHL, tOSLH Output to Output Skew(6) 1.0 ns Notes: 5. Outputs disabled or 3-STATE only. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 4 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs DC Electrical Characteristics TA = 25°C Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL VCC (V) Conditions Typical Units V 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 Conditions Typical Units V Capacitance Symbol Parameter CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 5 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Dynamic Switching Characteristics VCC OPEN 500Ω TEST SIGNAL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ GND DUT VI CL 500Ω Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL tPZL, tPLZ tPZH, tPHZ DATA IN VCC Vmi tpxx Open 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V GND 3-STATE Output High Enable and GND OUTPUT CONTROL tpxx DATA OUT tPZH Vmo tW CONTROL IN DATA IN tS tPHL MR OR CLEAR Vmo tPZL DATA OUT VCC GND Vmi tf GND tPLZ Vmo GND trec tr VCC Vmi VCC Setup Time, Hold Time and Recovery Time for Logic Propagation Delay, Pulse Width and trec Waveforms OUTPUT CONTROL Vmi tS tPLH Vmo tH CONTROL INPUT Vmi OUTPUT Vmi GND trec CLOCK VOH VY Vmo Disable Times for Logic VCC Vmi GND tPHZ DATA OUT Waveform for Inverting and Non-Inverting Functions VCC Vmi ANY OUTPUT VX VOL 90% 10% 90% 10% VOH VOL trise and tfall 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) Symbol 3.3V ± 0.3V VCC 2.7V Vmi Vmo Vx Vy 1.5V 1.5V VOL + 0.3V VOH – 0.3V 1.5V 1.5V VOL + 0.3V VOH – 0.3V ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 2.5V ± 0.2V VCC / 2 VCC / 2 VOL + 0.15V VOH – 0.15V www.fairchildsemi.com 6 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs AC Loading and Waveforms (Generic for LCX Family) Input Stage P2 P1 VCC Data ESD P5 D2 N+/P– X1 VDD N1 N2 GTO™ Output Input Stage D6 N+/P– P4 P3 N5 Enable N4 ESD D4 N+/P– N3 ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 7 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Schematic Diagram (Generic for LCX Family) Tape Format for DQFN Package Designator BQX Tape Section Number Cavities Cavity Status Cover Tape Status Leader (Start End) 125 (typ) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B 12mm 13.0 (330.0) 0.059 (1.50) ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 C D N 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) W1 W2 0.488 (12.4) 0.724 (18.4) www.fairchildsemi.com 8 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Tape and Reel Specification 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 9 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 10 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 11 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 12 74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74LCX540 Rev. 1.7.1 www.fairchildsemi.com 13 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 © Fairchild Semiconductor Corporation www.fairchildsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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