74LVQ00SJX

Revised April 2001 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQ00 contains four 2-input NAND gates. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LVQ00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description An, Bn Inputs On Outputs © 2001 Fairchild Semiconductor Corporation DS011341 www.fairchildsemi.com 74LVQ00 Low Voltage Quad 2-Input NAND Gate February 1992 74LVQ00 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) 2.0V to 3.6V VI = −0.5V −20 mA Input Voltage (VI) 0V to VCC VI = VCC + 0.5V +20 mA Output Voltage (VO) 0V to VCC DC Input Voltage (VI) −0.5V to VCC + 0.5V Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V DC Output Voltage (VO) −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) −0.5V to VCC + 0.5V ±50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current ±200 mA (ICC or IGND) −65°C to +150°C Storage Temperature (TSTG) 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float. ±100 mA DC Latch-Up Source or Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current TA = +25°C VCC TA = −40°C to +85°C Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 2.58 2.48 0.1 0.1 3.0 0.36 0.44 3.6 ±0.1 ±1.0 3.0 3.0 Guaranteed Limits 0.002 IOLD Minimum Dynamic 3.6 36 IOHD Output Current (Note 4) 3.6 −25 ICC Maximum Quiescent Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage Units (V) 3.6 2.0 20.0 Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA V VIN = VIL or VIH IOH = −12 mA (Note 3) IOUT = 50 µA V VIN = VIL or VIH IOL = 12 mA (Note 3) µA mA µA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND 3.3 0.6 1.0 V (Note 6)(Note 7) 3.3 −0.5 −1.0 V (Note 6)(Note 7) 3.3 1.5 2.0 V (Note 6)(Note 8) 3.3 1.5 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 TA = +25°C Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay tOSHL, Output to Output Skew tOSLH (Note 9) TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Min Typ Max Min Max 2.7 2.0 8.4 13.4 2.0 14.0 3.3 ± 0.3 2.0 7.0 9.5 2.0 10.0 2.7 1.5 6.6 11.3 1.0 12.0 3.3 ± 0.3 1.5 5.5 8.0 1.0 8.5 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Symbol CIN Parameter Input Capacitance CPD (Note 10) Power Dissipation Capacitance Typ Units 4.5 pF VCC = Open Conditions 22 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ00 AC Electrical Characteristics 74LVQ00 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 74LVQ00 Low Voltage Quad 2-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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