74LVQ157SJX

Revised June 2001 74LVQ157 Low Voltage Quad 2-Input Multiplexer General Description Features The LVQ157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true (non inverted) form. The LVQ157 can also be used as a function generator. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Guaranteed incident wave switching into 75Ω. Ordering Code: Order Number Package Number Package Description 74LVQ157SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions © 2001 Fairchild Semiconductor Corporation DS011352 Pin Names Description I0a–I0d Source 0 Data Inputs I1a–I1d Source 1 Data Inputs E Enable Input S Select Input Za–Zd Outputs www.fairchildsemi.com 74LVQ157 Low Voltage Quad 2-Input Multiplexer February 1992 74LVQ157 Truth Table Functional Description Inputs The LVQ157 is a quad 2-input multiplexer. It selects four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is active-LOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The LVQ157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Outputs E S I0 I1 Z H X X X L L H X L L L H X H H L L L X L L L H X H Za = E • (I1a • S + I0a • S) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Zb = E • (I1b • S + I0b • S) Zc = E • (I1c • S + I0c • S) Zd = E • (I1d • S + I0d • S) A common use of the LVQ157 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator. The LVQ157 can generate any four of the sixteen different functions of two variables with one variable common. This is useful for implementing gating functions. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions (Note 2) −0.5V to +7.0V DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA Input Voltage (VI) VI = VCC + 0.5V +20 mA Output Voltage (VO) DC Input Voltage (VI) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±50 mA or Sink Current (IO) DC VCC or Ground Current ±200 mA (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) DC Output Diode Current (IOK) DC Output Voltage (VO) 2.0V to 3.6V −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±100 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current VCC TA = +25°C TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 3.0 0.002 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.6 ±0.1 ±1.0 µA IOLD Minimum Dynamic 3.6 36 mA IOHD Output Current (Note 4) 3.6 −25 mA ICC Maximum Quiescent Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage Conditions Guaranteed Limits 3.6 4.0 40.0 µA VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND 3.3 0.7 0.8 V (Note 6)(Note 7) 3.3 −0.4 −0.8 V (Note 6)(Note 7) 3.3 1.7 2.0 V (Note 6)(Note 8) 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74LVQ157 Absolute Maximum Ratings(Note 1) 74LVQ157 AC Electrical Characteristics TA = +25°C Symbol tPLH Parameter Propagation Delay S to Zn tPHL Propagation Delay S to Zn Propagation Delay tPLH E to Zn tPHL Propagation Delay E to Zn tPLH Propagation Delay In to Zn Propagation Delay tPHL In to Zn tOSHL, Output to Output Skew (Note 9) tOSLH Data to Output TA = −40°C to +85°C CL = 50 pF VCC (V) Min CL = 50 pF Typ Max Min Max 2.7 1.5 84 16.2 1.5 19.0 3.3 ± 0.3 1.5 7.0 11.5 1.5 13.0 2.7 1.5 7.8 15.5 1.5 17.0 3.3 ± 0.3 1.5 6.5 11.0 1.5 12.0 2.7 1.5 8.4 16.2 1.5 19.0 3.3 ± 0.3 1.5 7.0 11.5 1.5 13.0 2.7 1.5 7.8 15.5 1.5 17.0 3.3 ± 0.3 1.5 6.5 11.0 1.5 12.0 2.7 1.5 6.0 12.0 1.0 13.0 3.3 ± 0.3 1.5 5.0 8.5 1.0 9.0 2.7 1.5 6.0 11.3 1.0 13.0 3.3 ± 0.3 1.5 5.0 8.0 1.0 9.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VC = Open CPD (Note 10) Power Dissipation Capacitance 34.0 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 Conditions 74LVQ157 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74LVQ157 Low Voltage Quad 2-Input Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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