74LVQ373SCX

Revised June 2001 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. ■ Ideal for low power/low noise 3.3V applications ■ Implements patented EMI reduction circuitry ■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity ■ Guaranteed incident wave switching into 75Ω ■ 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ373SC 74LVQ373SJ 74LVQ373QSC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Inputs Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs © 2001 Fairchild Semiconductor Corporation Outputs LE OE Dn On X H X Z H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable DS011359 www.fairchildsemi.com 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs February 1992 74LVQ373 Functional Description HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. The LVQ373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA Input Voltage (VI) VI = VCC + 0.5V +20 mA Output Voltage (VO) DC Input Voltage (VI) −0.5V to VCC + 0.5V 0V to VCC 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V DC Output Voltage (VO) 2.0V to 3.6V 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±50 mA or Sink Current (IO) DC VCC or Ground Current ±400 mA (ICC or IGND) −65°C to +150°C Storage Temperature (TSTG) Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±300 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current TA = +25°C VCC TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.6 ±0.1 ±1.0 µA 3.0 0.002 IOLD Minimum Dynamic 3.6 36 mA IOHD Output Current (Note 4) 3.6 −25 mA ICC Maximum Quiescent Supply Current IOZ 3.6 4.0 40.0 µA 3.6 ±0.25 ±2.5 µA VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND VI (OE) = VIL, VIH Maximum 3-STATE Leakage Current Conditions Guaranteed Limits VI = VCC, GND VO = VCC, GND VOLP Quiet Output Maximum Dynamic VOL 3.3 0.4 0.8 V (Note 6)(Note 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.8 V (Note 6)(Note 7) VIHD Maximum High Level Dynamic Input Voltage 3.3 1.7 2.0 V (Note 6)(Note 8) VILD Maximum Low Level Dynamic Input Voltage 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74LVQ373 Absolute Maximum Ratings(Note 1) 74LVQ373 AC Electrical Characteristics TA = +25°C Symbol Parameter tPHL Propagation Delay tPLH Dn to On tPLH Propagation Delay tPHL LE to On tPZL Output Enable Time tPZH tPHZ Output Disable Time tPLZ tOSHL Output to Output Skew tOSLH (Note 9) TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Min Typ Max Min Max 2.7 2.5 9.6 14.8 2.5 16.0 3.3 ± 0.3 2.5 8.0 10.5 2.5 11.0 2.7 2.5 9.6 16.9 2.5 18.0 3.3 ± 0.3 2.5 8.0 12.0 2.5 12.5 2.7 2.5 10.2 18.3 2.5 19.0 3.3 ± 0.3 2.5 8.5 13.0 2.5 13.5 2.7 1.0 10.8 20.4 1.0 21.0 3.3 ± 0.3 1.0 9.0 14.5 1.0 15.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements TA = +25°C Symbol Parameter (V) tS Setup Time, HIGH or LOW tH Hold Time, HIGH or LOW LE Pulse Width, tW HIGH TA = −40°C to +85°C CL = 50 pF VCC Typ CL = 50 pF 2.7 0 4.0 4.5 3.3 ± 0.3 0 3.0 3.0 2.7 0 1.5 1.5 3.3 ± 0.3 0 1.5 1.5 2.7 2.4 5.0 6.0 3.3 ± 0.3 2.0 4.0 4.0 Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 39 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 Units Guaranteed Minimum Conditions ns ns ns 74LVQ373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVQ373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com