74LVQ374QSC

Revised June 2001 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVQ374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. ■ Ideal for low power/low noise 3.3V applications ■ Implements patented EMI reduction circuitry ■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity ■ Guaranteed incident wave switching into 75Ω ■ 4 kV minimum ESD immunity ■ Buffered positive edge-triggered clock ■ 3-STATE outputs drive bus lines or buffer memory address registers Ordering Code: Order Number Package Number 74LVQ374SC 74LVQ374SJ 74LVQ374QSC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Inputs Pin Descriptions Pin Names Dn Description H D0–D7 Data Inputs L CP Clock Pulse Input X OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs © 2001 Fairchild Semiconductor Corporation DS011360   CP X H = HIGH Voltage Level X = Immaterial = LOW-to-HIGH Transition  Outputs OE On L H L L H Z L = LOW Voltage Level Z = High Impedance www.fairchildsemi.com 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs February 1992 74LVQ374 Functional Description With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. The LVQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions (Note 2) −0.5V to +7.0V DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA Input Voltage (VI) VI = VCC + 0.5V +20 mA Output Voltage (VO) DC Input Voltage (VI) −0.5V to VCC + 0.5V 0V to VCC 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V DC Output Voltage (VO) 2.0V to 3.6V 125 mV/ns −0.5V to VCC + 0.5V DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±400 mA (ICC or IGND) Storage Temperature (TSTG) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C DC Latch-Up Source or ±300 mA Sink Current Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage TA = +25°C VCC TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V ±0.1 3.0 Conditions Guaranteed Limits 0.002 VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA IIN Maximum Input Leakage Current 3.6 ±1.0 µA VI = VCC, GND IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA ICC Maximum Quiescent Supply Current IOZ 3.6 4.0 40.0 µA 3.6 ±0.25 ±2.5 µA or GND VI (OE) = VIL, VIH Maximum 3-STATE Leakage Current VOHD = 2.0V Min (Note 5) VIN = VCC VI = VCC, GND VO = VCC, GND VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V (Note 6)(Note 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.8 V (Note 6)(Note 7) VIHD Maximum High Level Dynamic Input Voltage 3.3 1.7 2.0 V (Note 6)(Note 8) VILD Maximum Low Level Dynamic Input Voltage 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74LVQ374 Absolute Maximum Ratings(Note 1) 74LVQ374 AC Electrical Characteristics TA = +25°C Symbol Parameter (V) Maximum Clock Frequency fMAX tPLH Propagation Delay tPHL CP to On tPZL Output Enable Time tPZH tPHZ Output Disable Time tPLZ tOSHL Output to Output Skew (Note 9) tOSLH CP to On TA = −40°C to +85°C CL = 50 pF VCC Min CL = 50 pF Typ Max Min 2.7 55 50 3.3 ± 0.3 75 70 Units Max MHz 2.7 3.0 11.4 18.3 3.0 19.0 3.3 ± 0.3 3.0 9.5 13.0 3.0 13.5 2.7 3.0 11.4 18.3 3.0 19.0 3.3 ± 0.3 3.0 9.5 13.0 3.0 13.5 2.7 1.0 11.4 20.4 1.0 21.0 3.3 ± 0.3 1.0 9.5 14.5 1.0 15.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements TA = +25°C Symbol Parameter (V) tS Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW CP Pulse Width, HIGH or LOW TA = 40°C− to +85°C CL = 50 pF VCC CL = 50 pF Typ 2.7 0 4.0 4.5 3.3 ± 0.3 0 3.0 3.0 2.7 0 1.5 1.5 3.3 ± 0.3 0 1.5 1.5 2.7 2.4 5.0 6.0 3.3 ± 0.3 2.0 4.0 4.0 ns ns ns Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 39 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 Units Guaranteed Minimum Conditions 74LVQ374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVQ374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com