74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
Features
General Description
■ Input and output interface capability to systems at
The LVTH125 contains four independent non-inverting
buffers with 3-STATE outputs.
■
■
■
■
■
■
■
5V VCC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 125
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model > 2000V
– Machine model > 200V
– Charged-device model > 1000V
These buffers are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH125 is fabricated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining a low power dissipation.
Ordering Information
Order Number
74LVTH125M
74LVTH125SJ
74LVTH125MTC
Package
Number
Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
January 2008
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
Truth Table
Description
An, Bn
Inputs
On
3-STATE Outputs
Inputs
Output
An
Bn
On
L
L
L
L
H
H
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Rating
Supply Voltage
–0.5V to +4.6V
VI
DC Input Voltage
–0.5V to +7.0V
VO
DC Output Voltage
Output in 3-STATE
–0.5V to +7.0V
State(1)
Output in HIGH or LOW
–0.5V to +7.0V
DC Input Diode Current, VI < GND
–50mA
IOK
DC Output Diode Current, VO < GND
–50mA
IO
DC Output Current, VO > VCC
IIK
Output at HIGH State
64mA
Output at LOW State
128mA
ICC
DC Supply Current per Supply Pin
±64mA
IGND
DC Ground Current per Ground Pin
±128mA
TSTG
Storage Temperature
–65°C to +150°C
Note:
1. IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VI
Parameter
Min
Max
Units
Supply Voltage
2.7
3.6
V
Input Voltage
0
5.5
V
IOH
HIGH-Level Output Current
–32
mA
IOL
LOW-Level Output Current
64
mA
TA
Free-Air Operating Temperature
–40
85
°C
0
10
ns/V
∆t / ∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
3
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Absolute Maximum Ratings
TA = –40°C to +85°C
Min.
Symbol
Parameter
VCC (V)
2.7
Input Clamp Diode Voltage
Input HIGH Voltage
VIL
Input LOW Voltage
2.7–3.6
VO ≤ 0.1V or
VO ≥ VCC – 0.1V
VOH
Output HIGH Voltage
2.7–3.6
IOH = –100µA
–1.2
2.0
0.8
VCC – 0.2
3.0
IOH = –32mA
2.0
2.7
IOL = 100µA
0.2
IOL = 24mA
0.5
IOL = 16mA
0.4
IOL = 32mA
0.5
IOL = 64mA
II(HOLD)
II(OD)
II
3.0
VI = 0.8V
Bushold Input Over-Drive
Current to Change State
3.0
VI =
(3)
Input Current
3.6
Bushold Input Minimum Drive
2.0V
(4)
IPU/PD
µA
–75
500
µA
–500
VI = 5.5V
10
Control Pins
3.6
VI = 0V or VCC
±1
Data Pins
3.6
VI = 0V
–5
Power Off Leakage Current
Power up/down 3-STATE
Output Current
0
0–1.5
V
0.55
75
VI = VCC
IOFF
V
V
2.4
3.0
V
V
IOH = –8mA
2.7
Output LOW Voltage
Units
II = –18mA
VIK
VOL
Max.
Conditions
VIH
2.7–3.6
Typ.(2)
µA
1
0V ≤ VI or VO ≤ 5.5V
±100
µA
VO = 0.5V to 3.0V,
VI = GND or VCC
±100
µA
IOZL
3-STATE Output Leakage Current
3.6
VO = 0.5V
–5
µA
IOZH
3-STATE Output Leakage Current
3.6
VO = 3.0V
5
µA
IOZH+
3-STATE Output Leakage Current
3.6
VCC < VO ≤ 5.5V
10
µA
ICCH
Power Supply Current
3.6
Outputs HIGH
0.19
mA
ICCL
Power Supply Current
3.6
Outputs LOW
5
mA
ICCZ
Power Supply Current
3.6
Outputs Disabled
0.19
mA
ICCZ+
Power Supply Current
3.6
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
0.19
mA
∆ICC
Increase in Power Supply
Current(5)
3.6
One Input at VCC – 0.6V,
Other Inputs at VCC or
GND
0.2
mA
Notes:
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
5. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
4
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
DC Electrical Characteristics
TA = 25°C
Conditions
Symbol
Parameter
VCC (V) CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum
Dynamic VOL
3.3
(7)
VOLV
Quiet Output Minimum
Dynamic VOL
3.3
(7)
Min.
Typ.
Max.
Units
0.8
V
–0.8
V
Notes:
6. Characterized in SOIC package. Guaranteed parameter, but not tested.
7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = –40°C to +85°C,
CL = 50pF, RL = 500Ω
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Propagation Delay, Data to Output
tPHL
tPZH
Output Enable Time
tPZL
tPHZ
Output Disable Time
tPLZ
tOSHL, tOSLH
Typ.(8)
Max.
VCC = 2.7V
Min.
Max.
Units
ns
1.0
3.5
1.0
4.5
1.0
3.9
1.0
4.9
1.0
4.0
1.0
5.5
1.1
4.0
1.1
5.4
1.5
4.5
1.5
5.7
1.3
4.5
1.3
4.0
Output to Output Skew(9)
1.0
ns
ns
1.0
ns
Notes:
8. All typical values are at VCC = 3.3V, TA = 25°C.
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance(10)
Symbol
CIN
COUT
Parameter
Conditions
Typical
Units
Input Capacitance
VCC = 0V, VI = 0V or VCC
4
pF
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
8
pF
Note:
10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
5
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Dynamic Switching Characteristics(6)
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
PIN ONE
INDICATOR
1
1.70
7
0.51
0.35
1.27
0.25
1.27
LAND PATTERN RECOMMENDATION
M
C B A
(0.33)
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.25
0.19
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50 X 45°
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
6
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
7
0.65
0.43 TYP
1.65
6.10
0.45
12.00° TOP
& BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
8
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions (Continued)
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
PDP-SPM™
Power220®
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Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
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SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
FPS™
FRFET®
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Green FPS™
Green FPS™e-Series™
GTO™
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IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
Fairchild®
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FACT Quiet Series™
FACT®
FAST®
FastvCore™
FlashWriter® *
®
SupreMOS™
SyncFET™
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The Power Franchise®
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µSerDes™
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Ultra FRFET™
UniFET™
VCX™
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
9
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
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