74LVTH162374MEX

74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs tm Features General Description ■ Input and output interface capability to systems at 5V The LVTH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ ■ ■ ■ ■ ■ ■ ■ VCC Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power Up/Power Down high impedance provides glitch-free bus loading Outputs include equivalent series resistance of 25Ω to make external termination resistors unnecessary and reduce overshoot and undershoot Functionally compatible with the 74 series 16374 Latch-up performance exceeds 500mA ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) The LVTH162374 is designed with equivalent 25Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162374 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Ordering Information Order Number Package Number Pb-Free Package Description Supplied As 74LVTH162374GX(1) BGA54A (Preliminary) Yes 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Tape and Reel 74LVTH162374MEA MS48A Yes 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Tubes 74LVTH162374MEX MS48A Yes 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Tape and Reel 74LVTH162374MTD MTD48 Yes 48-Lead Thin Shrink Small Outline Package Tubes (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162374MTX MTD48 Yes 48-Lead Thin Shrink Small Outline Package Tape and Reel (TSSOP), JEDEC MO-153, 6.1mm Wide Notes: 1. BGA package available in Tape and Reel only. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs July 2007 FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Pin Assignments for SSOP and TSSOP Logic Symbol Truth Tables Inputs Pin Assignment for FPGA CP1 Outputs OE1 I0–I7 O0–O7 L H H L L L L L X Oo X H X Z Inputs OE2 I8–I15 O8–O15 L H H L L L L L X Oo X H X Z CP2 (Top Thru View) Pin Description Outputs H = HIGH Voltage Level Pin Name Description OEn Output Enable Input (Active LOW) X = Immaterial CPn Clock Pulse Input Z = HIGH Impedance Inputs Oo = Previous Oo before LOW-to-HIGH of CP I0–I15 O0–O15 NC L = LOW Voltage Level 3-STATE Outputs No Connect ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 2 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Connection Diagrams flip-flop will store the state of their indi-vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. The LVTH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 3 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Functional Description Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Value Units Supply Voltage -0.5 to +4.6 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to +7.0 V VCC Parameter Conditions Output in 3-STATE Output in HIGH or LOW State(2) -0.5 to +7.0 IIK DC Input Diode Current VI < GND -50 mA IOK DC Output Diode Current VO < GND -50 mA IO DC Output Current VO > VCC Output at HIGH State 64 mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature -65 to +150 °C VO > VCC Output at LOW State 128 Note: 2. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Min. Supply Voltage Max. Units 2.7 3.6 V 0 5.5 V HIGH Level Output Current -12 mA IOL LOW Level Output Current 12 mA TA Free-Air Operating Temperature VI Input Voltage IOH ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 -40 85 °C 0 10 ns/V www.fairchildsemi.com 4 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Absolute Maximum Ratings TA = -40°C to +85°C Symbol Parameter VCC (V) Conditions VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VO ≤ 0.1V or VO ≥ VCC – 0.1V VOH Output HIGH Voltage 2.7–3.6 IOH = -100µA VCC – 0.2V 3.0 IOH = -12mA 2.0 2.7 IOL = 100µA 3.0 IOL = 12mA 3.0 VI = 0.8V 75 VI = 2.0V -75 (3) 500 (4) -500 VOL II(HOLD) II(OD) II Output LOW Voltage Bushold Input Minimum Drive 2.7 MIn. Bushold Input Over-Drive Current to Change State 3.0 Input Current 3.6 II = -18mA Control Pins Data Pins -1.2 2.0 Power Off Leakage Current 0 IPU/PD Power Up/Down 3-STATE Output Current 0–1.5 V V 0.8 V V 0.2 V 0.8 µA µA VI = 5.5V 10 VI = 0V or VCC ±1 VI = 0V -5 VI = VCC IOFF Max. Units µA 1 0V ≤ VI or VO ≤ 5.5V ±100 µA VO = 0.5V to 3.0V, VI = GND or VCC ±100 µA IOZL 3-STATE Output Leakage Current 3.6 VO = 0.5V -5 µA IOZH 3-STATE Output Leakage Current 3.6 VO = 3.0V 5 µA IOZH+ 3-STATE Output Leakage Current 3.6 VCC < VO ≤ 5.5V 10 µA ICCH Power Supply Current 3.6 Outputs HIGH 0.19 mA ICCL Power Supply Current 3.6 Outputs LOW 5 mA ICCZ Power Supply Current 3.6 Outputs Disabled 0.19 mA ICCZ+ Power Supply Current 3.6 VCC ≤ VO ≤ 5.5V, Outputs Disabled 0.19 mA ∆ICC Increase in Power Supply Current(5) 3.6 One Input at VCC – 0.6V Other Inputs at VCC or GND 0.2 mA Notes: 3. An external driver must source at least the specified current to switch from LOW-to-HIGH. 4. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 5 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs DC Electrical Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Conditions CL = 50pF, RL = 500Ω TA = -40°C to +85°C 3.3 (7) 0.8 V 3.3 (7) -0.8 V VCC (V) Min. Typ. Max Units Note: 6. Characterized in SSOP package. Guaranteed parameter, but not tested. 7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = -40°C to +85°C, CL = 50pF, RL = 500Ω VCC = 3.3V ±0.3V Symbol Parameter Min. Max. VCC = 2.7V Min. Max. fMAX Maximum Clock Frequency 160 tPHL tPLH Propagation Delay, CP to On 2.0 1.6 5.1 5.3 2.0 1.6 5.3 6.2 ns tPZL tPZH Output Enable Time 1.8 1.2 5.0 5.6 1.8 1.2 6.0 6.9 ns tPLZ tPHZ Output Disable Time 1.9 2.0 5.0 5.4 1.9 2.0 5.1 5.7 ns tS Setup Time 1.8 tH Hold Time 0.8 0.1 ns tW Pulse Width 3.0 3.0 ns tOSHL tOSLH Output to Output Skew(8) 150 Units MHz 2.0 1.0 1.0 ns 1.0 1.0 ns Note: 8. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance(9) Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN, VI = 0V or VCC 4 pF CPD Power Dissipation Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note: 9. Capcitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 6 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Dynamic Switching Characteristics(6) 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 7 Figure 2. 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 8 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MDT48 ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 9 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I30 ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 10 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs TRADEMARKS