74LVTH273SJ

74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Features General Description ■ Input and output interface capability to systems at The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear (CLR) are common to all flip-flops. ■ ■ ■ ■ ■ 5V VCC Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs Outputs source/sink –32mA/+64mA Functionally compatible with the 74 series 273 Latch-up performance exceeds 500mA ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop's output. The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Information Order Number Package Number 74LVTH273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH273MTC MTC20 Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear January 2008 Logic Symbols IEEE/IEC Pin Description Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input CLR Clear O0–O7 Outputs Truth Table Functional Description CLR Outputs On H H H L H L Dn The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW. Inputs CP X H or L H Oo X X L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 2 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Connection Diagram Symbol VCC VI Parameter Rating Supply Voltage –0.5V to +4.6V DC Input Voltage VO DC Output Voltage, Output –0.5V to +7.0V in HIGH or LOW State(1) –0.5V to +7.0V IIK DC Input Diode Current, VI < GND –50mA IOK DC Output Diode Current, VO < GND –50mA IO DC Output Current, VO > VCC ICC Output at HIGH State 64mA Output at LOW State 128mA DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature ±64mA ±128mA –65°C to +150°C Note: 1. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Min Max Units Supply Voltage 2.7 3.6 V VI Input Voltage 0 5.5 V IOH HIGH-Level Output Current –32 mA IOL LOW-Level Output Current 64 mA TA Free-Air Operating Temperature –40 85 °C 0 10 ns/V VCC ∆t / ∆V Parameter Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 3 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VIK Input Clamp Diode Voltage VIH Input HIGH Voltage TA =–40°C to +85°C VCC (V) 2.7 Conditions II = –18mA 2.7–3.6 VO ≤ 0.1V or VIL Input LOW Voltage 2.7–3.6 VO ≥ VCC – 0.1V VOH Output HIGH Voltage 2.7–3.6 IOH = –100µA VOL Output LOW Voltage II(OD) II –1.2 2.0 0.8 VCC – 0.2 2.4 3.0 IOH = –32mA 2.0 2.7 IOL = 100µA 0.2 IOL = 24mA 0.5 IOL = 16mA 0.4 IOL = 32mA 0.5 IOL = 64mA 0.55 VI = 0.8V Bushold Input Over-Drive Current to Change State 3.0 VI = (3) Input Current 3.6 VI = 5.5V 10 Control Pins 3.6 VI = 0V or VCC ±1 Data Pins 3.6 VI = 0V –5 (4) 75 ICCH Power Supply Current ICCL Power Supply Current Increase in Power Supply Current(5) V V µA –75 500 µA –500 VI = VCC Power Off Leakage Current V V IOH = –8mA 2.0V Units V 3.0 Bushold Input Minimum Drive IOFF ∆ICC Typ.(2) Max. 2.7 3.0 II(HOLD) Min. µA 1 0V ≤ VI or VO ≤ 5.5V ±100 µA 3.6 Outputs HIGH 0.19 mA 3.6 Outputs LOW 0 3.6 One Input at VCC – 0.6V, 5 mA 0.2 mA Other Inputs at VCC or GND Notes: 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. An external driver must source at least the specified current to switch from LOW-to-HIGH. 4. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 4 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear DC Electrical Characteristics TA = 25°C Conditions Symbol Parameter VCC (V) CL = 50pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 (7) VOLV Quiet Output Minimum Dynamic VOL 3.3 (7) Min. Typ. Ma.x Units 0.8 V –0.8 V Notes: 6. Characterized in SOIC package. Guaranteed parameter, but not tested. 7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = –40°C to +85°C, CL = 50pF, RL = 500Ω VCC = 3.3V ± 0.3V Symbol Parameter Min. Typ.(8) Max. VCC = 2.7V Min. Max. fMAX Maximum Clock Frequency 150 tPLH Propagation Delay. CP to On 1.7 4.9 1.7 5.5 1.9 4.8 1.9 5.1 Propagation Delay CLR to On 1.6 4.8 1.6 5.4 tW Pulse Duration 3.3 3.3 ns tS Setup Time Data HIGH or LOW before CP 2.3 2.7 ns CLR HIGH before CP 2.3 2.7 0 0 tPHL tPHL tH Hold Time Data HIGH or LOW after CP 150 Units MHz ns ns ns Note: 8. All typical values are at VCC = 3.3V, TA = 25°C. Capacitance(9) Symbol CIN COUT Parameter Conditions Typical Units Input Capacitance VCC = 0V, VI = 0V or VCC 3 pF Output Capacitance VCC = 3.0V, VO = 0V or VCC 6 pF Note: 9. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 5 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Dynamic Switching Characteristics(6) 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 6 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 7 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 8 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * ® SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 www.fairchildsemi.com 9 74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.