74LVTH543MTC

Revised November 2000 74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs General Description Features The LVTH543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. ■ Input and output interface capability to systems at 5V VCC The LVTH543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. This octal registered transceiver is designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH543 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 543 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number 74LVTH543WM M24B 74LVTH543MTC MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs LEAB, LEBA Latch Enable Inputs CEAB, CEBA Chip Enable Inputs A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs © 2000 Fairchild Semiconductor Corporation DS012448 www.fairchildsemi.com 74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs April 2000 74LVTH543 Logic Symbols Functional Description The LVTH543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table IEEE/IEC Inputs Output Latch Status CEAB LEAB OEAB H X X Latched High Z X H X Latched — Buffers L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. Logic Diagram Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 2) V V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current −32 IOL LOW Level Output Current 64 TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units mA −40 85 °C 0 10 ns/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVTH543 Absolute Maximum Ratings(Note 1) 74LVTH543 DC Electrical Characteristics Symbol TA =−40°C to +85°C VCC Parameter (V) Min Max −1.2 Conditions VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA II(HOLD) II(OD) Output LOW Voltage Bushold Input Minimum Drive 2.0 0.8 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 3) 3.0 −500 Input Current Control Pins Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE Output Current VO ≤ 0.1V or VO ≥ VCC − 0.1V 0.2 µA (Note 4) 3.6 10 µA VI = 5.5V 3.6 ±1 µA VI = 0V or VCC −5 µA VI = 0V 1 µA VI = VCC 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 0–1.5V ±100 µA Current to Change State II V 2.7 3.0 Bushold Input Over-Drive V II = −18 mA Input Clamp Diode Voltage VOL 2.7 Units VIK 3.6 VO = 0.5V to 3.0V VI = GND or VCC IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA A or B Port Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V Outputs Disabled ∆ICC Increase in Power Supply Current 3.6 0.2 mA (Note 5) One Input at VCC − 0.6V Other Inputs at VCC or GND Note 3: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 4: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 5: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 6) TA = 25°C VCC (V) Min Typ Conditions Max Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 7) Note 6: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 7: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3V ± 0.3V VCC = 2.7V Min Max Min Max tPLH Propagation Delay 1.3 4.4 1.3 4.8 tPHL Data to Outputs 1.3 4.6 1.3 5.2 tPLH Propagation Delay 1.3 5.4 1.3 6.4 tPHL LE to A or B 1.3 5.8 1.3 6.6 tPZH Output Enable Time 1.1 5.5 1.1 6.3 tPZL OE to A or B 1.1 6.1 1.1 7.2 tPHZ Output Disable Time 2.0 5.7 2.0 5.9 tPLZ OE to A or B 2.0 5.3 2.0 5.9 tPZH Output Enable Time 1.3 5.9 1.3 6.8 tPZL CE to A or B 1.3 6.2 1.3 7.4 tPHZ Output Disable Time 2.1 5.8 2.1 6.1 tPLZ CE to A or B 1.6 5.4 1.6 5.9 tW Pulse Duration tS Setup Time tH Hold Time tOSHL LE LOW 3.3 3.3 A or B before LE, Data HIGH 0.4 0.4 A or B before LE, Data LOW 1.0 1.5 A or B before CE, Data HIGH 0.2 0.2 1.2 A or B before CE, Data LOW 0.7 A or B before LE, Data HIGH 1.5 0.6 A or B before LE, Data LOW 1.3 1.5 A or B before CE, Data HIGH 1.6 0.5 A or B before CE, Data LOW 1.4 Output to Output Skew (Note 8) tOSLH Units ns ns ns ns ns ns ns ns ns 1.6 1.0 1.0 1.0 1.0 ns Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 9) Typical Units CIN Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 9: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. 5 www.fairchildsemi.com 74LVTH543 AC Electrical Characteristics 74LVTH543 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)