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74LVX240MX

74LVX240MX

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOIC20_300MIL

  • 描述:

    IC BUFFER INVERT 3.6V 20SOIC

  • 数据手册
  • 价格&库存
74LVX240MX 数据手册
Revised October 2003 74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVX240 is an octal inverting buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. ■ Input voltage translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number 74LVX240M 74LVX240SJ 74LVX240MTC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Truth Tables Inputs Connection Diagram Outputs OE1 In (Pins 12, 14, 16, 18) L L H L H L H X Z Inputs Outputs OE2 In (Pins 3, 5, 7, 9) L L H L H L H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 2003 Fairchild Semiconductor Corporation DS011609 www.fairchildsemi.com 74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs May 1993 74LVX240 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆V) −0.5V to VCC + 0.5V DC Output Voltage (VO) Note 1: Absolute Maximum Ratings are those values beyond which the safety to the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source ±25 mA or Sink Current (IO) DC VCC or Ground Current ±75 mA (ICC or IGND ) 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW. They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation (PD) 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ VCC Parameter TA = +25°C Min TA = −40°C to +85°C Typ Max Min HIGH Level 2.0 1.5 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Input Voltage 3.0 0.8 0.8 3.6 0.8 0.8 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 3.0 2.58 V VIN = VIH or VIL IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 LOW Level 2.0 0.0 Output Voltage 3.0 0.0 3-STATE Output Conditions V LOW Level HIGH Level Units 0.1 VIN = VIH or VIL 0.1 0.1 0.1 3.0 0.36 0.44 3.6 ±0.25 ±2.5 µA IOL = 50 µA IOL = 50 µA V IOL = 4 mA VIN = VIH or VIL VOUT = VCC or GND Off-State Current IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 4.0 40.0 µA VIN = VCC or GND Noise Characteristics (Note 3) Symbol Parameter VCC (V) TA = 25°C Typ Units CL (pF) 50 Limit VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.5 −0.8 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: (Input tr = tf = 3 ns) www.fairchildsemi.com 2 74LVX240 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay Time (V) 3-STATE Output tPZH Enable Time Units Conditions Max Min Max 5.7 10.1 1.0 12.5 8.2 13.6 1.0 16.0 4.3 6.2 1.0 7.5 6.8 9.7 1.0 11.0 7.1 13.8 1.0 16.5 CL = 15 pF, RL = 1 kΩ 9.6 17.3 1.0 20.0 CL = 50 pF, RL = 1 kΩ 5.5 8.8 1.0 10.5 8.0 12.3 1.0 14.0 2.7 11.6 16.0 1.0 19.0 3.3 ± 0.3 9.7 11.4 1.0 13.0 2.7 2.7 3.3 ± 0.3 Min TA = −40°C to +85°C Typ 3.3 ± 0.3 tPZL TA = +25°C VCC tPLZ 3-STATE Output tPHZ Disable Time tOSLH Output to Output 2.7 1.5 1.5 tOSHL Skew (Note 4) 3.3 1.5 1.5 CL = 15 pF ns CL = 50 pF CL = 15 pF CL = 50 pF ns CL = 15 pF, RL = 1 kΩ CL = 50 pF, RL = 1 kΩ ns ns CL = 50 pF, RL = 1 kΩ CL = 50 pF, RL = 1 kΩ CL = 50 pF Note 4: Parameter guaranteed by design. tOSLH = |t PLHm − tPLHn|, tOSHL = |t PHLm − tPHLn| Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 CIN Input Capacitance 4 COUT Output Capacitance 6 CPD Power Dissipation Capacitance (Note 5) 17 Min Units Max 10 pF pF 10 pF Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. 3 www.fairchildsemi.com 74LVX240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74LVX240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6
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