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to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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74LVX3245
8-Bit, Dual-Supply Translating Transceiver with
3-State Outputs
Features
Description
Bidirectional Interface Between 3 V and 5 V Buses
Outputs Source / Sink: 24 mA
Implements Proprietary EMI Reduction Circuitry
The 74LVX3245 is a dual-supply, 8-bit translating
transceiver designed to interface between a 3 V bus and
a 5 V bus in a mixed 5 V supply environment. The
Transmit/ Receive (T/¯
R ) input determines the direction
of data flow. Transmit (active-HIGH) enables data from
A-ports to B-ports; receive (active-LOW) enables data
from B-ports to A-ports. The output enable input, when
HIGH, disables both A- and B-ports by placing them in a
high-impedance condition. The A-port interfaces with
the 3 V bus; the B-port interfaces with the 5 V bus.
Inputs Compatible with TTL Level
3 V Data Flow at A-Port and 5 V Data Flow at BPort
Guaranteed Simultaneous Switching Noise Level
and Dynamic Threshold Performance
Functionally Compatible with the 74 Series 245
The 74LVX3245 is suitable for mixed-voltage
applications, such as notebook computers using 3.3 V
CPU and 5V peripheral components.
Related Resources
AN-5001 — Using Fairchild’s LVX Low-Voltage
Dual-Supply CMOS Translating Transceivers
Ordering Information
Part Number
Operating
Temperature Range
74LVX3245QSC
24-Lead Quarter-Size Outline Package
(QSOP), JEDEC MO-137, 0.150" Wide
74LVX3245QSCX
74LVX3245MTC
74LVX3245MTCX
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
Package
-40 to +85°C
24-Lead Thin-Shrink Small-Outline
Package (TSSOP), JEDEC MO-153,
4.4 mm Wide
Packing Method
Tubes
Tape and Reel
Tubes
Tape and Reel
www.fairchildsemi.com
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
April 2016
Figure 1.
Logic Symbol
Pin Configuration
Figure 2.
Pin Configuration
Pin Definitions
Pin #
Name
1
VCCA
Supply Voltage
2
T/¯
R
Transmit/Receive Input
3, 4, 5, 6, 7, 8, 9, 10
A0, A1, A2, A3, A4,
A5, A6, A7
11, 12, 13
GND
14, 15, 16, 17, 18, 19,
20, 21
B7, B6, B5, B4, B3,
B2, B1, B0
22
/OE
Output Enable Input
23
NC
No Connect
24
VCCB
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
Logic Symbol
Description
Port-A Inputs or 3-State Outputs
Ground
Port-B Inputs or 3-State Outputs
Supply Voltage
www.fairchildsemi.com
2
Figure 3.
Table 1.
Logic Diagram
Truth Table
Inputs
/OE
Outputs
T/¯
R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
Logic Diagram
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.5
7.0
V
-0.5
VCCA
+0.5
V
An
-0.5
VCCA to
+0.5
Bn
-0.5
VCCB to
+0.5
VCCA, VCCB Supply Voltage
VIN
VI/O
DC Input Voltage; (/OE, T/¯
R)
DC Input / Output Voltage
V
IIN
DC Input Diode Current (/OE and T/¯
R)
±20
mA
IOK
DC Output Diode Current
±50
mA
IO
DC Output Source or Sink Current
±50
mA
Output Pin
ICC or IGND DC VCC or Ground Current
TSTG
Storage Temperature Range
ISINK
TJ
ESD
±50
Maximum Current at
ICCA
±100
ICCB
mA
±200
-65
+150
°C
DC Latch-Up Source or Sink Current
±300
mA
Maximum Junction Temperature Under Bias
+150
°C
Electrostatic Discharge
Capability
2500
V
Human Body Model, JESD22-A114
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCCA
VCCB
VI
Parameter
Supply Voltage
Input Voltage (/OE and T/¯
R)
VI/O
DC Input / Output Voltage
TA
Operating Temperature, Free Air
t / V
Min.
Max.
2.7
3.6
4.5
5.5
Unit
V
0
VCCA
An
0
VCCA
Bn
0
VCCB
-40
+85
°C
8
ns/V
Minimum Input Edge Rate (VIN from 30 to 70% of VCC, VCC at 3.0 V,
4.5 V, and 5.5 V)
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
Absolute Maximum Ratings
V
V
Note:
1. Unused pins (inputs and I/O’s) must be held HIGH or LOW. They may not float.
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
www.fairchildsemi.com
4
Symbol
VIHA
VIHB
VILA
VILB
Parameter
Conditions
VCCA VCCB
(V)
(V)
TA= -25°C
Typ.
TA=-40 to+85°C
Guaranteed Limits
An, T/¯
R,
Minimum
/OE
VOUT 0.1 V or
HIGH Level
VCC - 0.1 V
Input Voltage B
n
3.6
5.0
2.0
2.0
2.7
5.0
2.0
2.0
3.3
4.5
2.0
2.0
3.3
5.5
2.0
2.0
An, T/¯
R,
Minimum
/OE
VOUT 0.1 V or
LOW Level
VCC - 0.1 V
Input Voltage B
n
3.6
5.0
0.8
0.8
2.7
5.0
0.8
0.8
3.3
4.5
0.8
0.8
3.3
5.5
0.8
0.8
IOUT=-100 µA
3.0
4.5
2.99
2.90
2.90
IOH=-24 mA
3.0
4.5
2.65
2.35
2.25
IOH=-12 mA
2.7
4.5
2.50
2.30
2.20
IOH=-24 mA
2.7
4.5
2.30
2.10
2.00
IOUT=-100 µA
3.0
4.5
4.50
4.40
4.40
IOH=-24 mA
3.0
4.5
4.25
3.86
3.76
IOUT=100 µA
3.0
4.5
0.002
0.100
0.100
IOH=24 mA
3.0
4.5
0.210
0.360
0.440
IOH=12 mA
2.7
4.5
0.110
0.360
0.440
IOH=24 mA
2.7
4.5
0.220
0.420
0.500
IOUT=100 µA
3.0
4.5
0.002
0.100
0.100
0.180
0.360
0.440
VOHA
Minimum HIGH Level
Output Voltage
VOHB
VOLA
Minimum LOW Level
Output Voltage
VOLB
Unit
V
V
V
V
IOH=24 mA
3.0
4.5
Maximum Input
Leakage Current;
/OE, T/¯
R
VIN=VCCB, GND
3.6
5.5
±0.1
±1.0
µA
IOZA
Maximum 3-State
Output Leakage; An
VIN=VIL, VIH;
/OE= VCCA;
VO=VCCA, GND
3.6
5.5
±0.5
±5.0
µA
IOZB
Maximum 3-State
Output Leakage; Bn
VIN=VIL, VIH;
/OE= VCCA;
VO=VCCB, GND
3.6
5.5
±0.5
±5.0
µA
Maximum
ICCT/Input at
VIN=VCCB-2.1 V
3.6
5.5
1.35
1.50
ICC
An, T/¯
R,
VIN=VCCA-0.6 V
/OE
3.6
5.5
0.35
0.50
ICCA
An=VCCA or GND,
Quiescent VCCA Supply Bn=VCCB or GND,
Current
/OE=GND,
T/¯
R =GND
3.6
5.5
5
50
ICCB
An=VCCA or GND,
Quiescent VCCB Supply Bn=VCCB or GND,
Current
/OE=GND,
T/¯
R =VCCA
3.6
IIN
Bn
1.00
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
DC Electrical Characteristics
mA
µA
5.5
8
80
Continued on the following page…
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
www.fairchildsemi.com
5
Parameter
VOLPA
Quiet Output Maximum
(2, 3)
Dynamic VOL
3.3
5.0
0.8
3.3
5.0
1.5
Quiet Output Minimum
(2, 3)
Dynamic VOL
3.3
5.0
-0.8
3.3
5.0
-1.2
Minimum HIGH Level
Dynamic Input
(2, 4)
Voltage
3.3
5.0
2.0
3.3
5.0
2.0
Maximum LOW Level
Dynamic Input
(2, 4)
Voltage
3.3
5.0
0.8
3.3
5.0
0.8
VOLPB
VOLVA
VOLVB
VIHDA
VIHDB
VILDA
VILDB
Conditions
TA=-40 to+85°C
VCCA VCCB TA= -25°C
(V)
(V)
Typ.
Guaranteed Limits
Symbol
Unit
V
V
V
V
Notes:
2. Worst-case package.
3. Maximum number of outputs defined as (n). Data inputs are driven 0 V to VCC level; one output at GND.
4. Maximum number of data inputs (n) switching. (n-1) inputs switching 0 V to VCC level. Input-under-test switching;
VCC level to threshold (VIHD), 0V to threshold (VILD), f=1 MHz.
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
DC Electrical Characteristics (Continued)
www.fairchildsemi.com
6
Symbol
Parameter
TA=-40 to +85°C,
CL=50 pF,
VCCA=2.7 V,
VCCB=5.0 V
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
Propagation
Delay A to B
1.0
5.4
8.0
1.0
8.5
1.0
9.0
1.0
5.6
7.5
1.0
8.0
1.0
8.5
Propagation
Delay B to A
1.0
5.1
7.5
1.0
8.0
1.0
8.5
1.0
5.7
7.5
1.0
8.0
1.0
8.5
Output Enable
Time /OE to B
1.0
4.8
8.0
1.0
8.5
1.0
9.0
1.0
6.3
8.5
1.0
9.0
1.0
9.5
Output Enable
Time /OE to A
1.0
6.3
8.5
1.0
9.0
1.0
9.5
1.0
6.8
9.0
1.0
9.5
1.0
10.0
Output Disable
Time /OE to B
1.0
5.3
7.5
1.0
8.0
1.0
8.5
1.0
4.2
7.0
1.0
7.5
1.0
8.0
Output Disable
Time /OE to A
1.0
5.3
8.0
1.0
8.5
1.0
9.0
1.0
3.7
6.5
1.0
7.0
1.0
7.5
1.0
1.5
tPHL, tPLH
tPZL, tPZH
tPHZ, tPLZ
tOSHL, tOSLH
TA=-40 to +85°C,
CL=50 pF,
(5)
VCCA=3.3 V ,
(6)
VCCB=5.0 V
TA=+25°C, CL=50 pF,
(5)
VCCA=3.3 V ,
(6)
VCCB=5.0 V
Output to Output
Skew, Data to
(7)
Output
1.5
Unit
ns
ns
ns
1.5
ns
Notes:
5. Voltage range 3.3 V is 3.3 V ± 0.3 V.
6. Voltage range 5.0 V is 5.0 V ± 0.5 V.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Conditions
Typ.
Unit
CIN
Input Capacitance
VCC = Open
4.5
pF
CI/O
Input / Output Capacitance
VCCA = 3.3 V,
VCCB = 5.0 V
15
pF
CPD
Power Dissipation Capacitance
(8)
A to B
B to A
VCCA = 3.3 V,
VCCB = 5.0 V
55
40
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
AC Electrical Characteristics
pF
Note:
8. CPD is measured at 10 MHz.
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
www.fairchildsemi.com
7
The 74LVX3245 is a dual-supply device capable of bidirectional signal translation. This level shifting ability
provides an efficient interface between low-voltage CPU
local bus with memory and a standard bus defined by
5 V I/O levels. The device control inputs can be
controlled by the low-voltage CPU and core logic or a
bus arbitrator with 5 V I/O levels.
Power-Up Considerations
To ensure that the system does not experience
unnecessary ICC current draw, bus contention, or
oscillations during power up; the following guidelines
should be followed to (refer to Table 2):
Manufactured on a sub-micron CMOS process, the
74LVX3245 is ideal for mixed voltage applications such
as notebook computers using 3.3 V CPUs and 5 V
peripheral devices.
Power up the control side of the device first (VCCA).
The Transmit/Receive (T/¯
R ) control pin should
ramp with VCCA. This ensures that the A-port data
pins are configured as inputs. With VCCA receiving
power first, the I/O port should be configured as an
input to help guard against bus contention and
oscillations.
/OE should ramp with or ahead of VCCA. This helps
guard against bus contention.
A-side data inputs should be driven to a valid logic
level. This prevents excessive current draw.
The above steps ensure that there are no bus
contentions or oscillations, and therefore no excessive
current draw occurs during the power-up cycling. These
steps help prevent possible damage to the translator
devices and potential damage to other system
components.
Figure 4.
Table 2.
Application Example
Low Voltage Translator Power-Up Sequencing
Device
74LVX3245
VCCA
VCCB
3V
5V
(Power-Up First) Configurable
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.6
T/¯
R
/OE
A-Side I/O
B-Side I/O
Floatable
Pin Allowed
Ramp
with VCCA
Ramp
with VCCA
Logic 0 V or
VCCA
Outputs
No
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
8-Bit Dual-Supply Translating Transceiver
www.fairchildsemi.com
8
8.741
8.591
0.10
24
13
1
12
A-B
A
24
13
5.60
3.99
3.84
0.10
6
A-B
1
0.20
12
.635
C
0.4
2X 12 TIPS
0.635
B
24X 0.3
LAND PATTERN
RECOMMENDATION
0.2
TOP VIEW
(0.695)
0.178
C A-B D
0.71
0.61
1.49
1.39
0.203
0.101
0.254
0.171
1.73 MAX
END VIEW
SIDE VIEW
0.25
0.50
0.25
0.50
NOTES :
R0.09 Min
GAGE
PLANE
0.254
A. THIS PACKAGE CONFORMS TO
JEDEC M0-137 VARIATION AE
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
E. LAND PATTERN STANDARD: SOP63P600X175-24M.
F. DRAWING FILE NAME: MKT-MQA24rev3
0.020
0.0295
0.039
SEATING PLANE
DETAIL A
1.75
7.8±0.1
A
0.20 TYP
13
24
13
1
12
B
12
1
(1.45)
3.2
6.4
4.4±0.1
(4.45)
5.9
(7.35)
24
0.65
0.20 C B A
0.10 C
0.65 TYP
0.10
C B Z
12° TOP & BOTTOM
R0.09MIN
0°- 8°
0.75
0.45
DATE 10/97.
(1.00)
DETAIL A
MTC24REV4
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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