74LVX574SJ

Revised April 2005 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVX574 is a high-speed octal D-type flip-flop which is controlled by an edge-triggered clock input (CP) and a buffered common Output Enable (OE) input. When the OE input is HIGH, the eight outputs are in a high impedance state. The LVX574 is functionally identical to the LVX374 but with inputs and outputs on opposite sides of the package. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. ■ Input voltage translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number 74LVX574M Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs © 2005 Fairchild Semiconductor Corporation DS500050 www.fairchildsemi.com 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs June 1993 74LVX574 Functional Description Truth Table The LVX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs Dn H L X Outputs   OE On L H L L X H Z CP H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) 0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI Supply Voltage (VCC) 0.5V 20 mA 0.5V to 7V DC Input Voltage (VI) VO 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) VO 2.0V to 3.6V Input Voltage (VI) 0V to VCC 40qC to 85qC Operating Temperature (TA) 0.5V VCC  0.5V 20 mA 20 mA 0.5V to VCC  0.5V DC Output Voltage (VO) Input Rise and Fall Time ('t/'V) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source r25 mA or Sink Current (IO) DC VCC or Ground Current r75 mA 65qC to 150qC (ICC or IGND) Storage Temperature (TSTG) Power Dissipation 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW. They may not float. 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ VCC Parameter TA Min 25qC Typ TA Max 40qC to 85qC Min HIGH Level 2.0 1.5 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Input Voltage 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 3.0 2.58 V VIN VIH or VIL V 2.48 LOW Level 2.0 0.0 Output Voltage 3.0 0.0 3-STATE Output Conditions V LOW Level Output Voltage Units 0.1 0.1 VIN 0.1 0.1 3.0 0.36 0.44 3.6 r0.25 r2.5 PA VIH or VIL V VIN Off-State Current VOUT IOH 50 PA IOH 50 PA IOH 4 mA IOL 50 PA IOL 50 PA IOL 4 mA VIH or VIL VCC or GND IIN Input Leakage Current 3.6 r0.1 r1.0 PA VIN 5.5V or GND ICC Quiescent Supply Current 3.6 4.0 40.0 PA VIN VCC or GND Noise Characteristics (Note 3) Symbol Parameter VCC (V) TA Typ 25qC Units Limit CL (pF) VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 0.5 0.8 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: (Input tr tf 3 ns) 3 www.fairchildsemi.com 74LVX574 Absolute Maximum Ratings(Note 1) 74LVX574 AC Electrical Characteristics (Note 4) Symbol fMAX VCC Parameter TA (V) Maximum 2.7 Clock 3.3 r 0.3 Frequency tPLH Propagation tPHL Delay Time tPZL 3-STATE Output tPZH Enable Time Typ Disable Time tW CP Pulse 50 CL 15 pF CL 50 pF 80 125 65 CL 15 pF 50 75 45 CL 50 pF tH MHZ 9.2 14.5 1.0 17.5 CL 15 pF 11.5 18.0 1.0 21.0 CL 50 pF 8.5 13.2 1.0 15.5 CL 15 pF 11.0 16.7 1.0 19.0 CL 50 pF 9.8 15.0 1.0 18.5 CL 15 pF, RL 1 k: 11.4 18.5 1.0 22.0 CL 50 pF, RL 1 k: 8.2 12.8 1.0 15.0 CL 15 pF, RL 1 k: 10.7 16.3 1.0 18.5 CL 50 pF, RL 1 k: 2.7 12.1 19.1 1.0 22.0 CL 50 pF, RL 1 k: 3.3 r 0.3 11.0 15.0 1.0 17.0 CL 50 pF, RL 1 k: CL 50 pF 6.5 7.5 3.3 r 0.3 5.0 5.0 2.7 5.0 5.0 3.3 r 0.3 3.5 3.5 Hold Time 2.7 1.5 1.5 Dn to CP 3.3 r 0.3 1.5 1.5 Dn to CP Conditions 40 2.7 Setup Time Units 60 2.7 Width tS Max 115 3.3 r 0.3 3-STATE Output Min 60 3.3 r 0.3 tPLZ tPHZ 40qC to 85qC TA Max 45 2.7 CP to On 25qC Min ns ns ns tOSHL Output to Output 2.7 1.5 1.5 Skew (Note 4) 3.3 1.5 1.5 |tPLHm  tPLHn|, tOSHL ns ns tOSLH Note 4: Parameter guaranteed by design. tOSLH ns ns |tPHLm  tPHLn|. Capacitance Symbol Parameter TA Min 25qC TA Typ Max 10 40qC to 85qC Min Max Units CIN Input Capacitance 4 COUT Output Capacitance 6 pF CPD Power Dissipation 27 pF 10 Capacitance (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. www.fairchildsemi.com 4 pF 74LVX574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVX574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com