74LVX74MTCX

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description ■ Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Asynchronous Inputs: ■ LOW input to SD (Set) sets Q to HIGH level ■ LOW input to CD (Clear) sets Q to LOW level ■ Clear and Set are independent of clock ■ Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number Package Number Package Description 74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop February 2008 Logic Symbols IEEE/IEC Pin Description Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H X L L X H H H H H H L H H L L H H H X Q0 Q0 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 2 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V IIK DC Input Diode Current, VI = –0.5V VI DC Input Voltage IOK DC Output Diode Current –20mA –0.5V to 7V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±25mA ICC or IGND DC VCC or Ground Current TSTG Storage Temperature P ±50mA –65°C to +150°C Power Dissipation 180mW Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Supply Voltage 2.0V to 3.6V VI Input Voltage 0V to 5.5V VO Output Voltage 0V to VCC TA Operating Temperature ∆t / ∆V Input Rise and Fall Time –40°C to +85°C 0ns/V to 100ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 3 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings TA = +25°C Symbol VIH VIL VOH VOL Parameter VCC Conditions Min. Typ. Max. TA = –40°C to +85°C Min. Max. HIGH Level Input Voltage 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 LOW Level Input Voltage 2.0 0.5 0.5 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level Output Voltage LOW Level Output Voltage Units V 2.4 2.0 VIN = VIL or VIH, IOH = –50µA 1.9 2.0 1.9 3.0 VIN = VIL or VIH, IOH = –50µA 2.9 3.0 2.9 VIN = VIL or VIH, IOH = –4mA 2.58 V V 2.48 2.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.1 0.1 3.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.1 0.1 VIN = VIL or VIH, IOL = 4mA 0.36 0.44 V IIN Input Leakage Current 3.6 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 3.6 VIN = VCC or GND 2.0 20.0 µA Noise Characteristics(2) TA = 25°C Symbol Parameter VCC (V) CL (pF) Typ. Limit Units VOLP Quiet Output Maximum Dynamic VOL 3.3 50 0.3 0.5 V VOLV Quiet Output Minimum Dynamic VOL 3.3 50 –0.3 –0.5 V VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 50 2.0 V VILD Maximum LOW Level Dynamic Input Voltage 3.3 50 0.8 V Note: 2. Input tr = tf = 3ns ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 4 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop DC Electrical Characteristics TA = –40°C to +85°C TA = +25°C Symbol Parameter tPLH, tPHL Propagation Delay, CPn to Qn or Qn VCC (V) CL (pF) 2.7 3.3 ± 0.3 tPLH, tPHL Propagation Delay, 2.7 CDn to SDn to Qn or Qn 3.3 ± 0.3 tW tS tH tREC fMAX CPn or CDn or SDn Pulse Width Typ. Max. Min. Max. Units 15 7.3 15 1.0 18.5 ns 50 9.8 18.5 1.0 22 15 5.7 9.7 1.0 11.5 50 8.2 13.2 1.0 15 15 8.4 15.6 1.0 18.5 50 10.9 19.1 1.0 22 15 6.6 10.1 1.0 12 50 9.1 13.6 1.0 15.5 2.7 8.5 10 3.3 ± 0.3 6 7 Setup Time, Dn to CPn 2.7 8.0 9.5 3.3 ± 0.3 5.5 6.5 2.7 0.5 0.5 3.3 ± 0.3 0.5 0.5 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 Hold Time, Dn to CPn Recovery Time, CPn or SDn to CPn Min. Maximum Clock Frequency 2.7 3.3 ± 0.3 tOSLH, tOSHL Output to Output Skew(3) 2.7 15 55 135 50 50 45 60 40 15 95 145 80 50 60 85 50 50 3.3 ns ns ns ns ns MHz 1.5 1.5 1.5 1.5 ns Note: 3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn| Capacitance TA = –40°C to +85°C TA = +25°C Symbol Parameter Min. Typ. Max. 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance(4) 25 Min. Max. 10 Units pF pF Note: 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. C PD × V CC × f IN × I CC Average operating current can be obtained by the eqation: ICC(opr.) = -------------------------------------------------------2 ( per, F ⁄ F ) ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 5 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop AC Electrical Characteristics 0.65 A 0.43TYP 14 8 B 6.4 6.10 3.2 1 PIN#1 IDENT 0.2 C B A 7 TOP VIEW 1.65 ALL LEAD TIPS 0.45 RECOMMENDED LAND PATTERN 1.2 MAX 0.30 0.19 ALL LEAD TIPS 0.1 C 0.65 SEE DETAIL A 0.90+0.15 -0.10 0.13 A B 0.20 0.09 C C FRONT VIEW 0.09 MIN NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. GAGE PLANE 0.09 MIN 1.00 0.25 SEATING PLANE DETAIL A 8.75 8.50 A 7.62 14 8 14 B 0.65 8 4.00 3.80 6.00 1 PIN #1 IDENT. 1.27 (0.33) TOP VIEW 5.60 7 0.51 0.35 0.25 M C B A 1.75 MAX 1.70 1 1.27 LAND PATTERN RECOMMENDATION A C 1.50 1.25 FRONT VIEW 0.25 0.10 0.50 0.25 x 45 R0.10 GAGE PLANE R0.10 0.36 8° 0° 0.90 0.50 (1.04) 0.10 C 0.25 0.19 SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. DRAWING FILENAME: MKT-M14Arev14 SEATING PLANE DETAIL A SCALE 16 : 1 7 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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