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to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
74VCX08
Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant
Inputs and Outputs
Features
General Description
■ 1.2V to 3.6V VCC supply operation
The VCX08 contains four 2-input AND gates. This product is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V.
■ 3.6V tolerant inputs and outputs
■ tPD:
■
■
■
■
■
■
– 2.8ns max. for 3.0V to 3.6V VCC
Power-off high impedance inputs and outputs
Static Drive (IOH/IOL)
– ±24mA @ 3.0V VCC
Uses proprietary Quiet Series™ noise/EMI reduction
circuitry
Latchup performance exceeds 300mA
ESD performance:
– Human body model > 2000V
– Machine model > 250V
Leadless DQFN package
The VCX08 is fabricated with an advanced CMOS
technology to achieve high-speed operation while maintaining low CMOS power dissipation.
Ordering Information
Order Number
74VCX08M
Package
Number
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74VCX08BQX(1)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74VCX08MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
December 2013
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
Logic Symbol
Connection Diagrams
Pin Assignments for SOIC and TSSOP
IEEE/IEC
Pad Assignments for DQFN
(Top View)
(Bottom View)
Pin Description
Pin Names
Description
An, Bn
Inputs
On
Outputs
DAP
No Connect
Note: DAP (Die Attach Pad)
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
2
Symbol
VCC
Parameter
Rating
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
–0.5V to +4.6V
–0.5V to 4.6V
HIGH or LOW State(2)
–0.5V to VCC+0.5V
VCC = 0V
–0.5V to +4.6V
IIK
DC Input Diode Current, VI < 0V
IOK
DC Output Diode Current
IOH / IOL
–50mA
VO < 0V
–50mA
VO > VCC
+50mA
DC Output Source/Sink Current
+50mA
ICC or GND DC VCC or Gound Current per Supply Pin
TSTG
Storage Temperature Range
±100mA
–65°C to +150°C
Note:
2. IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Power Supply Operating
VI
Input Voltage
VO
Output Voltage, HIGH or LOW State
IOH / IOL
Rating
1.2V to 3.6V
–0.3V to 3.6V
0V to VCC
Output Current
VCC = 3.0V to 3.6V
±24mA
VCC = 2.3V to 2.7V
±18mA
VCC = 1.65V to 2.3V
±6mA
VCC = 1.4V to 1.6V
±2mA
VCC = 1.2V
TA
∆t / ∆V
±100µA
Free Air Operating Temperature
–40°C to +85°C
Minimum Input Edge Rate, VIN = 0.8V to 2.0V, VCC = 3.0V
10ns/V
Note:
3. Floating or unused inputs must be held HIGH or LOW
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
3
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VIH
VIL
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
VCC (V)
Conditions
Min
2.7–3.6
2.0
2.3–2.7
1.6
1.65–2.3
0.65 × VCC
1.4–1.6
0.65 × VCC
1.2
0.65 × VCC
HIGH Level Output Voltage
0.8
2.3–2.7
0.7
0.35 × VCC
1.4–1.6
0.35 × VCC
IOH = –12mA
2.2
IOH = –18mA
2.4
3.0
IOH = –24mA
2.2
2.3–2.7
IOH = –100µA
VCC – 0.2
2.3
IOH = –6mA
2.3
IOH = –12mA
1.8
2.3
IOH = –18mA
1.7
IOH = –100µA
VCC – 0.2
1.4–1.6
1.2
IOH = –100µA
2.0
1.25
VCC – 0.2
1.05
VCC – 0.2
IOL = 100µA
0.2
2.7
IOL = 12mA
0.4
3.0
IOL = 18mA
0.4
3.0
IOL = 24mA
0.55
2.3–2.7
IOL = 100µA
0.2
2.3
IOL = 12mA
0.4
2.3
IOL = 18mA
0.6
1.65–2.3
IOL = 100µA
0.2
IOL = 6mA
0.2
IOL = 100µA
0.2
1.4
IOL = 2mA
0.35
1.2
IOL = 100µA
0.05
0 ≤ VI ≤ 3.6V
1.2–3.6
Power-OFF Leakage Current
ICC
Quiescent Supply Current
1.2–3.6
Increase in ICC per Input
2.7–3.6
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
V
2.7–3.6
IOFF
∆ICC
IOH = –100µA
IOH = –2mA
1.65
Input Leakage Current
IOH = –6mA
1.4
1.4–1.6
II
VCC – 0.2
2.7
1.65
LOW Level Output Voltage
0.05 x VCC
IOH = –100µA
3.0
1.65–2.3
VOL
V
1.65–2.3
2.7–3.6
0
Units
V
2.7–3.6
1.2
VOH
Max
V
±5.0
µA
0 ≤ (VI, VO) ≤ 3.6V
10
µA
VI = VCC or GND
20
µA
VCC ≤ VI ≤ 3.6V
±20
VIH = VCC –0.6V
750
µA
www.fairchildsemi.com
4
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
DC Electrical Characteristics
TA = –40°C to
+85°C
Symbol
Parameter
VCC (V)
tPHL, tPLH
Propagation Delay
3.3 ± 0.3
Conditions
CL = 30pF, RL = 500Ω
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
CL = 15pF, RL = 2kΩ
1.2
tOSHL, tOSLH Output to Output
Skew(5)
3.3 ± 0.3
Min.
Max.
Units
Figure
Number
0.6
2.8
ns
Fig. 1
0.8
3.7
1.0
7.4
1.0
14.8
Fig. 3
1.5
37.0
Fig. 4
CL = 30pF, RL = 500Ω
0.5
2.5 ± 0.2
0.5
1.8 ± 0.15
0.75
1.5 ± 0.1
Fig. 2
CL = 15pF, RL = 2kΩ
ns
1.5
1.2
1.5
Note:
4. For CL = 50pF, add approximately 300ps to the AC Maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
TA = 25°C
Symbol
VOLP
Parameter
VCC (V)
Quiet Output Dynamic Peak VOL
Conditions
CL = 30pF, VIH = VCC,
VIL = 0V
1.8
2.5
3.3
VOLV
Quiet Output Dynamic Valley VOL
CL = 30pF, VIH = VCC,
VIL = 0V
1.8
3.3
Quiet Output Dynamic Valley VOH
Unit
0.25
V
0.6
0.8
2.5
VOHV
Typical
–0.25
V
–0.6
–0.8
CL = 30pF, VIH = VCC,
VIL = 0V
1.8
2.5
3.3
1.5
V
1.9
2.2
Capacitance
TA = +25°C
Symbol
Parameter
Conditions
Typical
Units
Input Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
6.0
pF
COUT
Output Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
7.0
pF
CPD
Power Dissipation
Capacitance
VI = 0V or VCC, f = 10MHz, VCC = 1.8V, 2.5V or 3.3V
20.0
pF
CIN
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
5
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
AC Electrical Characteristics(4)
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V)
Test
Switch
tPLH, tPHL
Open
Figure 1. AC Test Circuit
VCC
Symbol
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
Vmi
1.5V
VCC / 2
VCC / 2
Vmo
1.5V
VCC / 2
VCC / 2
Figure 2. Waveform for Inverting and Non-inverting Functions
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
6
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
AC Loading and Waveforms (VCC 1.5 ± 0.1V to 1.2V)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC = 1.5V ± 0.1V
tPZH, tPHZ
GND
Figure 3. AC Test Circuit
VCC
Symbol
1.5V ± 0.1V
Vmi
VCC / 2
Vmo
VCC / 2
Figure 4. Waveform for Inverting and Non-Inverting Functions
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
7
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
Cavity Status
Cover Tape Status
BQX
Leader (Start End)
125 (Typ.)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00)
0.795 (20.20)
2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
8
74VCX08 — Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
Tape and Reel Specification
0.65
A
0.43TYP
14
8
B
6.4
6.10
3.2
1
PIN#1 IDENT
0.2 C B A
7
TOP VIEW
1.65
ALL LEAD TIPS
0.45
RECOMMENDED LAND PATTERN
1.2 MAX
0.30
0.19
ALL LEAD TIPS
0.1 C
0.65
SEE DETAIL A
0.90+0.15
-0.10
0.13
A B
0.20
0.09
C
C
FRONT VIEW
0.09 MIN
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
GAGE PLANE
0.09 MIN
1.00
0.25
SEATING PLANE
DETAIL A
8.75
8.50
A
7.62
14
8
14
B
0.65
8
4.00
3.80
6.00
1
PIN #1
IDENT.
1.27
(0.33)
TOP VIEW
5.60
7
0.51
0.35
0.25 M C B A
1.75 MAX
1.70
1
1.27
LAND PATTERN RECOMMENDATION
A
C
1.50
1.25
FRONT VIEW
0.25
0.10
0.50
0.25 x 45
R0.10
GAGE
PLANE
R0.10
0.36
8°
0°
0.90
0.50
(1.04)
0.10 C
0.25
0.19
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
SEATING PLANE
DETAIL A
SCALE 16 : 1
7
0.05 C
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
A
2X
1.00
MAX
2.50
1.70
MAX
0.50 TYP
3.50
MAX
0.05 C
PIN #1 QUADRANT
TOP VIEW
(0.90)
2X
0.50 TYP
0.24 TYP
RECOMMENDED LAND PATTERN
0.10 C
0.08 C
SEATING
PLANE
C
SIDE VIEW
A. CONFORMS TO JEDEC REGISTRATION
MO-241, VARIATION AA
B. DIMENSIONS ARE IN MILLIMETERS.
(14X)
PIN #1 IDENT
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP14Arev2.
0.50
0.50
(14X)
2.00
BOTTOM VIEW
0.10
0.05
C A B
C
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
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