74VCX16244

74VCX16244 Low−Voltage 1.8V/2.5V/3.3V 16−Bit Buffer http://onsemi.com MARKING DIAGRAM 48 48 1 With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74VCX16244 is an advanced performance, non−inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V. The 74VCX16244 is nibble controlled with each nibble functioning identically, but independently. The control pins may be tied together to obtain full 16−bit operation. The 3−state outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are in the high impedance state. Features TSSOP−48 DT SUFFIX CASE 1201 A WL YY WW VCX16244 AWLYYWW 1 = Assembly Location = Wafer Lot = Year = Work Week • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V • • • • • • • 3.0 ns max for 2.3 V to 2.7 V 6.0 ns max for 1.65 V to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V; Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free* ORDERING INFORMATION Device 74VCX16244DT 74VCX16244DTR Package TSSOP (Pb−Free) TSSOP (Pb−Free) Shipping † 39 / Rail 2500 / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 5 1 Publication Order Number: 74VCX16244/D 74VCX16244 OE1 OE1 1 O0 2 O1 3 GND 4 O2 5 O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 O11 17 VCC 18 O12 19 O13 20 GND 21 O14 22 O15 23 OE4 24 48 OE2 47 D0 46 D1 45 GND 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 32 D11 31 VCC 30 D12 29 D13 28 GND 27 D14 26 D15 25 OE3 OE1 48 OE2 25 OE3 24 OE4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 1 1 1 1 48 OE3 OE4 25 24 OE2 D0:3 O0:3 D8:11 O8:11 D4:7 O4:7 D12:15 O12:15 One of Four Figure 2. Logic Diagram EN1 EN2 EN3 EN4 1 1∇ 2 3 5 6 8 9 11 2∇ 3∇ 12 13 14 16 4∇ 17 19 20 22 23 Figure 1. 48−Lead Pinout (Top View) O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 Figure 3. IEC Logic Diagram Table 1. PIN NAMES Pins OEn D0−D15 O0−O15 Function Output Enable Inputs Inputs Outputs TRUTH TABLE OE1 L L H D0:3 L H X O0:3 L H Z OE2 L L H D4:7 L H X O4:7 L H Z OE3 L L H D8:11 L H X O8:11 L H Z OE4 L L H D12:15 L H X O12:15 L H Z H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 74VCX16244 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value −0.5 to +4.6 −0.5 ≤ VI ≤ +4.6 −0.5 ≤ VO ≤ +4.6 −0.5 ≤ VO ≤ VCC + 0.5 DC Input Diode Current DC Output Diode Current −50 −50 +50 DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range ±50 ±100 ±100 −65 to +150 Output in 3−State Note 1; Outputs Active VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO IOH IOL IOH IOL IOH IOL TA Dt/DV Supply Voltage Input Voltage Output Voltage HIGH Level Output Current, VCC = 3.0 V − 3.6 V LOW Level Output Current, VCC = 3.0 V − 3.6 V HIGH Level Output Current, VCC = 2.3 V − 2.7 V LOW Level Output Current, VCC = 2.3 V − 2.7 V HIGH Level Output Current, VCC = 1.65 V − 1.95 V LOW Level Output Current, VCC = 1.65 V − 1.95 V Operating Free−Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V −40 0 (Active State) (3−State) Parameter Operating Data Retention Only Min 1.65 1.2 −0.3 0 0 Typ 3.3 3.3 Max 3.6 3.6 3.6 VCC 3.6 −24 24 −18 18 −6 6 +85 10 Unit V V V mA mA mA mA mA mA °C ns/V http://onsemi.com 3 74VCX16244 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH Characteristic HIGH Level Input Voltage (Note 2) Condition 1.65 V ≤ VCC < 2.3 V 2.3 V ≤ VCC ≤ 2.7 V 2.7 V < VCC ≤ 3.6 V VIL LOW Level Input Voltage (Note 2) 1.65 V ≤ VCC < 2.3 V 2.3 V ≤ VCC ≤ 2.7 V 2.7 V < VCC ≤ 3.6 V VOH HIGH Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC = 1.65 V; IOH = −6 mA VCC = 2.3 V; IOH = −6 mA VCC = 2.3 V; IOH = −12 mA VCC = 2.3 V; IOH = −18 mA VCC = 2.7 V; IOH = −12 mA VCC = 3.0 V; IOH = −18 mA VCC = 3.0 V; IOH = −24 mA VOL LOW Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC = 1.65 V; IOL = 6 mA VCC = 2.3 V; IOL = 12 mA VCC = 2.3 V; IOL = 18 mA VCC = 2.7 V; IOL = 12 mA VCC = 3.0 V; IOL = 18 mA VCC = 3.0 V; IOL = 24 mA II IOZ IOFF ICC DICC Input Leakage Current 3−State Output Current Power−Off Leakage Current Quiescent Supply Current (Note 3) 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 3.6 V 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V; VI = VIH or VIL VCC = 0 V; VI or VO = 3.6 V 1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC 1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V Increase in ICC per Input 2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V 2. These values of VI are used to test DC electrical characteristics only. 3. Outputs disabled or 3−state only. VCC − 0.2 1.25 2.0 1.8 1.7 2.2 2.4 2.2 0.2 0.3 0.4 0.6 0.4 0.4 0.55 ±5.0 ±10 10 20 ±20 750 mA mA mA mA mA mA V Min 0.65 x VCC 1.6 2.0 0.35 x VCC 0.7 0.8 V V Max Unit V http://onsemi.com 4 74VCX16244 AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W) TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Input−to−Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output−to−Output Skew (Note 5) Waveform 1 2 2 Min 0.8 0.8 0.8 0.8 0.8 0.8 Max 2.5 2.5 3.5 3.5 3.5 3.5 0.5 0.5 VCC = 2.3 V to 2.7 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.0 3.0 4.1 4.1 3.8 3.8 0.5 0.5 VCC = 1.65 V to 1.95 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 8.2 8.2 6.8 6.8 0.75 0.75 Unit ns ns ns ns 4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W) TA = −405C to +855C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Propagation Delay Input−to−Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output−to−Output Skew (Note 6) Parameter Waveform 3 4 4 Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.0 3.0 4.4 4.4 4.1 4.1 0.5 0.5 VCC = 2.7 V Min Max 3.6 3.6 5.4 5.4 4.6 4.6 0.5 0.5 Unit ns ns ns ns 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 5 74VCX16244 DYNAMIC SWITCHING CHARACTERISTICS Symbol VOLP Characteristic Dynamic LOW Peak Voltage (Note 7) Condition VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V VOLV Dynamic LOW Valley Voltage (Note 7) VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V VOHV Dynamic HIGH Valley Voltage (Note 8) VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V Typical (TA = +25°C) 0.25 0.6 0.8 −0.25 −0.6 −0.8 1.5 1.9 2.2 V V Unit V 7. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. 8. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the HIGH state. CAPACITIVE CHARACTERISTICS Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition Note 9 Note 9 Note 9, 10MHz Typical 6 7 20 Unit pF pF pF 9. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC. http://onsemi.com 6 74VCX16244 VIH OEn VIH Dn Vm tPLH On Vm Vm tPHL Vm 0V VOH VOL On tPZH On tPZL Vm Vm tPLZ tPHZ Vm 0V VOH Vy ≈ 0V ≈ VCC Vx VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 4. AC Waveforms Table 2. AC WAVEFORMS VCC Symbol VIH Vm Vx Vy 3.3 V ± 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V VCC RL CL RL 6 V or VCC × 2 OPEN GND 2.5 V ± 0.2 V VCC VCC/2 VOL + 0.15 V VOH − 0.15 V 1.8 V ± 0.15 V VCC VCC/2 VOL + 0.15 V VOH − 0.15 V PULSE GENERATOR RT DUT Figure 5. Test Circuit Table 3. TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Open 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V GND SWITCH CL = 30 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W) http://onsemi.com 7 74VCX16244 VIH OEn Vm tPLH On Vm Vm tPHL Vm VIH 0V VOH VOL On On tPZL Vm tPZH Vm tPLZ tPHZ Vy ≈ 0V ≈ VCC Vx VOL Vm 0V Dn VOH WAVEFORM 3 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 4 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 6. AC Waveforms Table 4. AC WAVEFORMS VCC Symbol VIH Vm Vx Vy 3.3 V ± 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V VCC RL CL RL 6V or VCC × 2 OPEN GND 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V PULSE GENERATOR RT DUT Figure 7. Test Circuit Table 5. TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Open 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V GND SWITCH CL = 50 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50W) http://onsemi.com 8 74VCX16244 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 1201−01 ISSUE A 48X K REF 0.12 (0.005) M TU S V S K K1 J J1 48 25 0.254 (0.010) L B − U− N 1 24 SECTION N−N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 −−− 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 −−− 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 −−− 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 −−− 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ PIN 1 IDENT. A −V− N F DETAIL E M 0.25 (0.010) D 0.076 (0.003) −T− SEATING PLANE C DETAIL E G H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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