74VCX16821MTD

Revised October 2004 74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16821 contains twenty non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. ■ 3.6V tolerant inputs and outputs The 74VCX16821 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.4V to 3.6V VCC supply operation ■ tPD 3.5 ns max for 3.0V to 3.6V VCC ■ Power-off high impedance inputs and outputs ■ Supports live insertion and withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74VCX16821MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names © 2004 Fairchild Semiconductor Corporation DS500130 Description OEn Output Enable Input (Active LOW) CLKn Clock Input D0–D19 Inputs O0–O19 Outputs www.fairchildsemi.com 74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs March 1998 74VCX16821 Connection Diagram Truth Tables Inputs Outputs CLK1 OE1 D0–D9 O0–O9 X   H X Z L L L L H H L or H L X O0 Inputs Outputs CLK2 OE2 D10–D19 O10–O19 X   H X Z L or H L L L L H H L X O0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition  Functional Description The VCX16821 contains twenty D-type flip-flops with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of each other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. The twenty flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CLK) transition. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the flip-flops. Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 4) Supply Voltage (VCC) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Power Supply −0.5V to +4.6V Input Voltage Output Voltage (VO) Operating Outputs 3-STATE Outputs Active (Note 3) −0.5V to VCC + 0.5V DC Input Diode Current (IIK) VI < 0V Output Voltage (VO) −50 mA Output in Active States DC Output Diode Current (IOK) 0V to VCC Output in 3-STATE VO < 0V −50 mA VO > VCC +50 mA ±50 mA (IOH/IOL) 0.0V to 3.6V Output Current in IOH/IOL DC Output Source/Sink Current VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V ±6 mA VCC = 1.4V to 1.6V DC VCC or GND Current per ±100 mA Supply Pin (ICC or GND) Storage Temperature Range (TSTG) 1.4V to 3.6V −0.3V to +3.6V ±2 mA Free Air Operating Temperature (TA) −65°C to +150°C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage VCC (V) Min 2.7 - 3.6 2.0 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x VCC 1.4 - 1.6 0.65 x VCC 2.7 - 3.6 HIGH Level Output Voltage 0.8 0.7 1.65 - 2.3 0.35 x VCC 2.7 - 3.6 VCC - 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOH = −100 µA 2.3 - 2.7 VCC - 0.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.8 IOH = −18 mA 2.3 1.7 IOH = −100 µA 1.65 - 2.3 VCC - 0.2 1.65 1.25 IOH = −100 µA 1.4 - 1.6 VCC - 0.2 IOH = −12 mA 1.4 1.05 3 V 0.35 x VCC IOH = −100 µA IOH = −6 mA Units V 2.3 - 2.7 1.4 - 1.6 VOH Max V www.fairchildsemi.com 74VCX16821 Absolute Maximum Ratings(Note 2) 74VCX16821 DC Electrical Characteristics Symbol (Continued) Parameter Conditions VCC Min Max Units (V) VOL LOW Level Output Voltage IOL = 100 µA 2.7 - 3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 18 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 IOL = 100 µA 2.3 - 2.7 0.2 IOL = 6 mA 2.3 0.4 IOL = 12 mA 2.3 0.6 IOL = 100 µA 1.65 - 2.3 0.2 IOL = 6 mA IOL = 100 µA IOL = 2 mA 1.65 0.3 1.4 - 1.6 0.2 1.4 0.35 1.4 - 3.6 ±5.0 1.4 - 3.6 ±10 µA 0 10 µA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = VCC or GND 1.4 - 3.6 20 VCC ≤ (VI, VO) ≤ 3.6V (Note 5) 1.4 - 3.6 ±20 VIH = VCC −0.6V 2.7 - 3.6 750 VI = VIH or VIL ∆ICC Increase in ICC per Input Note 5: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 V µA µA µA Symbol fMAX tPHL Parameter Maximum Clock Frequency Propagation Delay VCC Conditions CL = 30 pF, RL = 500Ω Output Enable Time Output Disable Time tH tW Setup Time Hold Time Pulse Width tOSHL Output to Output Skew tOSLH (Note 7) 250 200 100 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 80.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 2.5 ± 0.2 1.0 4.4 1.8 ± 0.15 1.5 8.8 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 1.0 17.6 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.7 2.5 ± 0.2 1.0 4.7 Figure Number 3.5 1.8 ± 0.15 1.5 9.8 1.5 ± 0.1 1.0 19.6 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.7 2.5 ± 0.2 1.0 4.2 1.8 ± 0.15 1.5 7.6 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 1.0 15.2 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 2.5 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 3.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.0 2.5 ± 0.2 1.0 1.8 ± 0.15 1.0 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 2.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 4.0 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 4.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 CL = 15 pF, RL = 500Ω Units MHz CL = 15 pF, RL = 500Ω tPHZ tS 3.3 ± 0.3 Max 1.8 ± 0.15 tPZH tPLZ Min 2.5 ± 0.2 tPLH tPZL TA = −40°C to +85°C (V) ns Figures 1, 2 Figures 7, 8 ns Figures 1, 3, 4 Figures 7, 9, 10 ns Figures 1, 3, 4 Figures 7, 9, 10 ns Figure 6 ns Figure 6 ns Figure 5 0.5 2.5 ± 0.2 0.5 1.8 ± 0.15 0.75 1.5 ± 0.1 1.5 ns Note 6: For CL = 50 PF, add approximately 300 ps to the AC maximum specification. Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). 5 www.fairchildsemi.com 74VCX16821 AC Electrical Characteristics (Note 6) 74VCX16821 Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V VCC TA = +25°C (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz, 20 pF VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 74VCX16821 AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3V ± 0.3V; VCC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74VCX16821 AC Loading and Waveforms (VCC 1.5V ± 0.1V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC x 2 at VCC = 1.5V ± 0.1V tPZH, tPHZ GND FIGURE 7. AC Test Circuit FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic VCC Symbol 1.5V ± 0.1V Vmi www.fairchildsemi.com VCC/2 Vmo VCC/2 VX VOL + 0.1V VY VOH − 0.1V 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted