74VCX38MX

74VCX38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Features General Description ■ 1.2V to 3.6V VCC supply operation The VCX38 contains four 2-input NAND gates with open drain outputs. This product is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. ■ 3.6V tolerant inputs and outputs ■ tPD: ■ 2.8ns max. for 3.0V to 3.6V VCC ■ Power-Off high impedance inputs and outputs ■ Static Drive (IOL): ■ ■ ■ ■ – +24mA @ 3.0V VCC Uses patented Quiet Series™ noise/EMI reduction circuitry Latchup performance exceeds JEDEC 78 conditions ESD performance: – Human body model > 2000V – Machine model > 250V Leadless DQFN package The VCX38 is fabricated with advanced CMOS technology to achieve high-speed operation while maintaining CMOS low power dissipation. Ordering Information Order Number 74VCX38M Package Number M14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VCX38BQX(1) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74VCX38MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs February 2008 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Connection Diagrams Logic Symbol Pin Assignments for SOIC and TSSOP IEEE/IEC Pad Assignments for DQFN (Top View) Pin Description Pin Names Description An, Bn Inputs On Outputs ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +4.6V VI DC Input Voltage –0.5V to 4.6V VO Output Voltage(2) –0.5V to 4.6V IIK DC Input Diode Current, VI < 0V –50mA IOK DC Output Diode Current, VO < 0V –50mA IOL DC Output Source/Sink Current +50mA ICC or GND Supply Pin TSTG ±100mA Storage Temperature Range –65°C to +150°C Note: 2. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions(3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Power Supply Operating VI Input Voltage VO Output Voltage IOL Output Current 1.2V to 3.6V –0.3V to 3.6V 0V to VCC VCC = 3.0V to 3.6V ±24mA VCC = 2.3V to 2.7V ±18mA VCC = 1.65V to 2.3V ±6mA VCC = 1.4V to 1.6V ±2mA VCC = 1.2V TA ∆t / ∆V ± 100µA Free Air Operating Temperature –40°C to +85°C Minimum Input Edge Rate, VIN = 0.8V to 2.0V, VCC = 3.0V 10ns/V Note: 3. Floating or unused inputs must be held HIGH or LOW ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 3 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Absolute Maximum Ratings Symbol VIH VIL Parameter HIGH Level Input Voltage LOW Level Input Voltage VCC (V) Conditions 2.7–3.6 2.0 2.3–2.7 1.6 1.65–2.3 0.65 × VCC 1.4–1.6 0.65 × VCC 1.2 0.65 × VCC 2.7–3.6 LOW Level Output Voltage IOFF Power-Off Leakage Current ICC Quiescent Supply Current V 2.3–2.7 0.7 0.35 × VCC 1.4–1.6 0.35 × VCC 0.05 × VCC 2.7–3.6 IOL = 100µA 0.2 2.7 IOL = 12mA 0.4 3.0 IOL = 18mA 0.4 3.0 IOL = 24mA 0.55 V 2.3–2.7 IOL = 100µA 0.2 2.3 IOL = 12mA 0.4 2.3 IOL = 18mA 0.6 1.65–2.3 IOL = 100µA 0.2 IOL = 6mA 0.3 IOL = 100µA 0.2 1.4 IOL = 2mA 0.35 1.2 IOL = 100µA 0.05 1.2–3.6 0 ≤ VI ≤ 3.6V ±5.0 µA 0 ≤ (VI, VO) ≤ 3.6V 10.0 µA VI = VCC or GND 20.0 µA VCC ≤ (VI) ≤ 3.6V ±20.0 1.65 II Units V 1.65–2.3 1.4–1.6 Input Leakage Current Max 0.8 1.2 VOL Min 0 1.2–3.6 ∆ICC Increase in ICC per Input 2.7–3.6 VIH = VCC – 0.6V 750 µA IOHZ Off State Current 1.2–3.6 VO = 3.6 10.0 µA ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 4 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs DC Electrical Characteristics TA = –40°C to +85°C Symbol Parameter VCC (V) tPZL, tPZH Propagation Delay 3.3 ± 0.3 Conditions CL = 30pF, RL = 500Ω 2.5 ± 0.2 1.8 ± 0.15 1.5 ± 0.1 CL = 15pF, RL = 2kΩ Min. Max. Units Figure Number 0.6 2.8 ns Fig. 1 0.8 3.7 1.0 6.7 1.0 13.4 Fig. 3 33.5 Fig. 4 1.2 tOSHL, tOSLH Output to Output Skew(5) 3.3 ± 0.3 CL = 30pF, RL = 500Ω 0.5 2.5 ± 0.2 0.5 1.8 ± 0.15 0.75 1.5 ± 0.1 Fig. 2 CL = 15pF, RL = 2kΩ ns 1.5 1.2 1.5 Note: 4. For CL = 50pF, add approximately 300ps to the AC Maximum specification. 5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics TA = 25°C Symbol VOLP Parameter VCC (V) Quiet Output Dynamic Peak VOL 1.8 2.5 Conditions CL = 30pF, VIH = VCC, VIL = 0V 3.3 VOLV Quiet Output Dynamic Valley VOL 1.8 2.5 Typical Unit 0.25 V 0.6 0.8 CL = 30pF, VIH = VCC, VIL = 0V 3.3 –0.25 V –0.6 –0.8 Capacitance TA = +25°C Symbol Parameter Conditions Typical Units Input Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 6.0 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7.0 pF CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10MHz, VCC = 1.8V, 2.5V or 3.3V 20.0 pF CIN ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 5 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs AC Electrical Characteristics(4) 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V) Test Switch 6V at VCC = 3.3 ± 0.3V; tPZL, tPLZ VCC × 2 at VCC = 2.5V ± 0.2V; 1.8V Figure 1. AC Test Circuit VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC / 2 VCC / 2 Vmo 1.5V VCC / 2 VCC / 2 Vx VOL + 0.3V VOL + 0.15V VOL + 0.15V Figure 2. Waveform for Open Drain, Inverting and Non-inverting Functions ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 6 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs AC Loading and Waveforms (VCC 1.5 ± 0.1V to 1.2V) Test Switch tPZL, tPLZ VCC x 2 at VCC = 1.5V ± 0.1V Figure 3. AC Test Circuit VCC Symbol 1.5V ± 0.1V Vmi VCC / 2 Vmo VCC / 2 VX VOL + 0.1V VY VOH – 0.1V Figure 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 7 Tape Format for DQFN Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (Typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typ.) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 8 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Tape and Reel Specification 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 5. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 9 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Physical Dimensions Figure 6. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 10 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 7. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 11 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs Physical Dimensions (Continued) ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * ® SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 ©1999 Fairchild Semiconductor Corporation 74VCX38 Rev. 1.9.0 www.fairchildsemi.com 12 74VCX38 — Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.