74VHC273MX

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This literature is subject to all applicable copyright laws and is not for resale in any manner. 74VHC273 Octal D-Type Flip-Flop tm Features General Description ■ High Speed: fMAX = 165MHz (typ) at VCC = 5V ■ Low power dissipation: ICC = 4µA (max) at TA = 25°C The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.9V (max) ■ Pin and function compatible with 74HC273 ■ Leadless DQFN Package The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number Package Number Package Description 74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC273BQ (Preliminary) MLP020B (Preliminary) 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC273MTC Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 74VHC273 Octal D-Type Flip-Flop April 2007 74VHC273 Octal D-Type Flip-Flop Connection Diagrams Logic Symbols Pin Assignments for PDIP, SOIC, SOP, and TSSOP IEEE/IEC Pad Assignments for DQFN Function Table Operating Mode Inputs Outputs MR CP Dn Qn Reset (Clear) L X X L Load ‘1’ H H H Load ‘0’ H L L H = HIGH Voltage Level L = LOW Voltage Level (Top Through View) X = Immaterial = LOW-to-HIGH Transition Pin Descriptions Pin Names Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 3 74VHC273 Octal D-Type Flip-Flop Logic Diagram Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC/GND Current ±75mA TSTG Storage Temperature –65°C to +150°C TL Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr , tf Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C Input Rise and Fall Time, VCC = 3.3V ± 0.3V 0ns/V ∼ 100ns/V VCC = 5.0V ± 0.5V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 4 74VHC273 Octal D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0–5.5 0.7 x VCC 3.0 LOW Level Output Voltage Min. 0.50 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 V IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH IOL = 50µA or VIL 4.5 3.0 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA IOL = 8mA V 0.3 x VCC 1.9 4.5 2.0 V 0.3 x VCC VIN = VIH IOH = –50µA or VIL Units 0.7 x VCC 3.0 3.0 Max. 0.50 3.0–5.5 2.0 –40°C to +85°C Max. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 IIN Input Leakage Current 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA Noise Characteristics TA = 25°C Symbol Typ. Limits Units VOLP(2) Quiet Output Maximum Dynamic VOL Parameter VCC (V) 5.0 CL = 50pF Conditions 0.6 0.9 V VOLV(2) Quiet Output Minimum Dynamic VOL 5.0 CL = 50pF –0.6 –0.9 V VIHD(2) Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50pF 3.5 V VILD(2) Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50pF 1.5 V Note: 2. Parameter guaranteed by design. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 5 74VHC273 Octal D-Type Flip-Flop DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter VCC (V) Maximum Clock Frequency 3.3 ± 0.3 Conditions 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CK – Q) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR – Q) 3.3 ± 0.3 5.0 ± 0.5 tOSLH, tOSHL Output to Output Skew CIN Input Capacitance CPD Power Dissipation Capacitance 3.3 ± 0.3 (3) 5.0 ± 0.5 VCC (4) Min. Typ. Max. Min. CL = 15pF 75 120 65 CL = 50pF 50 75 45 CL = 15pF 120 165 100 CL = 50pF 80 110 70 Max. Units MHz MHz CL = 15pF 8.7 13.6 1.0 16.0 CL = 50pF 11.2 17.1 1.0 19.5 CL = 15pF 5.8 9.0 1.0 10.5 CL = 50pF 7.3 11.0 1.0 12.5 CL = 15pF 8.9 13.6 1.0 16.0 CL = 50pF 11.4 17.1 1.0 19.5 CL = 15pF 5.2 8.5 1.0 10.0 CL = 50pF 6.7 10.5 1.0 12.0 CL = 50pF 1.5 1.5 CL = 50pF 1.0 1.0 10.0 10.0 = Open 4.0 31 ns ns ns ns ns pF pF Notes: 3. Parameter guaranteed by design tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pieces of the Flip-Flop operates can be calculated by the equation: CPD (total) = 22 + 9n. AC Operating Requirements TA = 25°C Symbol tW(L), tW(H) tW(L) tS tH tREC Parameter Minimum Pulse Width (CK) Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (MR) VCC (V)(5) Typ. TA = –40°C to +85°C Guaranteed Minimum 3.3 5.5 6.5 5.0 5.0 5.0 3.3 5.0 6.0 5.0 5.0 5.0 3.3 5.5 6.5 5.0 4.5 4.5 3.3 1.0 1.0 5.0 1.0 1.0 3.3 2.5 2.5 5.0 2.0 2.0 Units ns ns ns ns ns Note: 5. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 6 74VHC273 Octal D-Type Flip-Flop AC Electrical Characteristics Tape Format for DQFN Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status BQ Leader (Start End) 125 (typ.) Empty Sealed Carrier 2500/3000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Tape Dimensions Dimensions are in millimeters unless otherwise noted. Figure 2. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 7 74VHC273 Octal D-Type Flip-Flop Tape and Reel Specification 74VHC273 Octal D-Type Flip-Flop Tape and Reel Specification (Continued) Reel Dimensions for DQFN Dimensions are in inches (millimeters) unless otherwise noted. Tape Size A B C D N W1 W2 12mm 13.0 (330) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 7.008 (178) 0.488 (12.4) 0.724 (18.4) Figure 3. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 8 74VHC273 Octal D-Type Flip-Flop Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 9 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 10 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B (Preliminary) ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 11 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 12 ® ACEx Across the board. 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A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 13 74VHC273 Octal D-Type Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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