74VHC541SJX

Revised May 2005 74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs General Description The VHC541 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. This device is similar in function to the VHC244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD 3.5 ns (typ) at VCC 5V ■ Low power dissipation: ICC 4 PA (max) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP 0.9V (typ) ■ Pin and function compatible with 74HC541 Ordering Code: Order Number 74VHC541M 74VHC541SJ 74VHC541MTC 74VHC541N Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Symbol IEEE/IEC Truth Table Pin Descriptions Inputs Pin Names Descriptions OE1, OE2 3-STATE Output Enable Inputs I0 - I7 Inputs O0 - O7 3-STATE Outputs OE1 OE2 I L L H H X X Z X H X Z L L L L H HIGH Voltage Level L LOW Voltage Level © 2005 Fairchild Semiconductor Corporation DS011639 Outputs H X Immaterial Z High Impedance www.fairchildsemi.com 74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs August 1993 74VHC541 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC  0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r0.3V 0 a 100 ns/V VCC 5.0V r0.5V 0 a 20 ns/V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 2: Unused inputs must be held HIGH or LOW. They may not float DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL 25qC 40qC to 85qC TA Typ Max Min 2.0 1.50 1.50 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level Output 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 LOW Level Output 2.0 ICC Quiescent Supply Current V VIN VIH V IOH 50 PA IOH 4 mA or VIL 4.4 0.0 0.1 V 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 VIN VIH V IOH 8 mA IOL 50 PA IOL 4 mA IOL 8 mA or VIL 3.0 0.36 0.44 0.36 0.44 5.5 r0.25 r2.5 0  5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND Off-State Current Input Leakage Current Conditions 4.5 3-STATE Output IIN Units V 3.0  5.5 Voltage IOZ TA Min 3.0  5.5 LOW Level Input Voltage VOH VCC (V) Parameter V PA VIN VIH or VIL VOUT VCC or GND Noise Characteristics Symbol Parameter VOLP Quiet Output Maximum Dynamic (Note 3) VOL VOLV Quiet Output Minimum Dynamic (Note 3) VOL VIHD Minimum HIGH Level Dynamic (Note 3) Input Voltage VILD Maximum HIGH Level Dynamic (Note 3) Input Voltage TA Typ Limits 5.0 0.9 1.2 V CL 50 pF 5.0 0.8 1.0 V CL 50 pF 5.0 3.5 V CL 50 pF 5.0 1.5 V CL 50 pF Note 3: Parameter guaranteed by design. www.fairchildsemi.com 25qC VCC (V) 2 Units Conditions Symbol Parameter tPLH Propagation Delay tPHL Time VCC (V) TA Min 3.3 r 0.3 5.0 r 0.5 tPZL 3-STATE Output tPZH Enable Time 3.3 r 0.3 5.0 r 0.5 25qC TA 40qC to 85qC Typ Max Min Max 5.0 7.0 1.0 8.5 7.5 10.5 1.0 12.0 3.5 5.0 1.0 6.0 5.0 7.0 1.0 8.0 6.8 10.5 1.0 12.5 9.3 14.0 1.0 16.0 4.7 7.2 1.0 8.5 6.2 9.2 1.0 10.5 tPLZ 3-STATE 3.3 r 0.3 11.2 15.4 1.0 17.5 tPHZ Output 5.0 r 0.5 6.0 8.8 1.0 10.0 Units Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 50 pF CL 50 pF CL 50 pF CL 50 pF ns ns ns RL ns RL ns Disable Time tOSLH Output to Output Skew tOSHL CIN Input Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance Note 4: Parameter guaranteed by design. tOSLH 3.3 r 0.3 1.5 1.5 5.0 r 0.5 1.0 1.0 10 10 4 |tPLHmax  t PLHmin|; tOSHL ns (Note 4) pF VCC Open 6 pF VCC 5.0V 18 pF (Note 5) |tPHLmax  tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (OPR.) CPD * VCC * fIN  ICC/8 (per bit). 3 www.fairchildsemi.com 74VHC541 AC Electrical Characteristics 74VHC541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74VHC541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHC541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com