74VHC74MX

74VHC74 Dual D-Type Flip-Flop with Preset and Clear Features General Description ■ High Speed: fMAX = 170MHz (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) The VHC74 is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC = 2µA (max.) at TA = 25°C ■ Pin and function compatible with 74HC74 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number Package Number Package Description 74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC74MTC 74VHC74N MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear February 2014 Logic Symbol IEEE/IEC Truth Table Pin Description Pin Names Inputs Description Outputs CLR PR D CK Q Q Clock Pulse Inputs L H X X L H Clear Direct Clear Inputs H L X X H L Preset PR1, PR2 Direct Preset Inputs L L X X H(1) H(1) Q1, Q1, Q2, Q2 Output H H L L H H H H H L H H X Qn Qn D1, D2 Data Inputs CK1, CK2 CLR1, CLR2 Function No Change Note: 1. This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state. ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 2 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG Storage Temperature TL ±50mA –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(2) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr , tf Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C Input Rise and Fall Time, VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V Note: 2. Unused inputs must be held HIGH or LOW. They may not float. ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 3 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Absolute Maximum Ratings TA = –40°C to +85°C TA = 25°C Min. Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. IOH = –50µA 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 4.5 IOH = –8mA 3.94 3.80 3.0 VIN = VIH or VIL IOL = 50µA 4.5 3.0 4.5 IOL = 8mA V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA V 0.3 x VCC 1.9 3.0 2.0 Units V 0.50 0.3 x VCC VIN = VIH or VIL Max. 0.7 x VCC 0.50 3.0–5.5 2.0 Max. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 IIN Input Leakage Current 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 VIN = VCC or GND 2.0 20.0 µA ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 4 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter Maximum Clock Frequency VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CK-Q, Q) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CLR, PR -Q, Q) 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Conditions CL = 15pF Min. Typ. 80 125 Max. Min. Max. 70 CL = 50pF 50 75 45 CL = 15pF 130 170 110 CL = 50pF 90 115 75 MHz CL = 15pF 6.7 11.9 1.0 14.0 CL = 50pF 9.2 15.4 1.0 17.5 CL = 15pF 4.6 7.3 1.0 8.5 CL = 50pF 6.1 9.3 1.0 10.5 CL = 15pF 7.6 12.3 1.0 14.5 CL = 50pF 10.1 15.8 1.0 18.0 CL = 15pF 4.8 7.7 1.0 9.0 CL = 50pF 6.3 9.7 1.0 11.0 4 10 VCC (3) = Open Units 10 25 ns ns pF pF Note: 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 2 (per F/F). AC Operating Requirements TA = –40°C to +85°C TA = 25°C Symbol tW(L), tW(H) tW(L) Parameter Minimum Pulse Width (CK) Minimum Pulse Width (CLR, PR) tS Minimum Setup Time tH Minimum Hold Time tREC VCC (V)(4) Minimum Recovery Time (CLR, PR) Typ. Guaranteed Minimum 3.3 6.0 7.0 5.0 5.0 5.0 3.3 6.0 7.0 5.0 5.0 5.0 3.3 6.0 7.0 5.0 5.0 5.0 3.3 0.5 0.5 5.0 0.5 0.5 3.3 5.0 5.0 5.0 3.0 3.0 Units ns ns ns ns ns Note: 4. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 5 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear AC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION C B A M (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 6 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 7 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 8 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC74 Rev. 1.3.1 www.fairchildsemi.com 9 74VHC74 — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 © Fairchild Semiconductor Corporation www.fairchildsemi.com