ADM1024

ADM1024 System Hardware Monitor with Remote Diode Thermal Sensing The ADM1024 is a complete system hardware monitor for microprocessor−based systems, providing measurement and limit comparison of various system parameters. Eight measurement inputs are provided; three are dedicated to monitoring 5.0 V and 12 V power supplies and the processor core voltage. The ADM1024 can monitor a fourth power supply voltage by measuring its own VCC. One input (two pins) is dedicated to a remote temperature−sensing diode. Two more pins can be configured as inputs to monitor a 2.5 V supply and a second processor core voltage, or as a second temperature−sensing input. The remaining two inputs can be programmed as general purpose analog inputs or as digital fan speed measuring inputs. Measured values can be read out via a serial System Management Bus and values for limit comparisons can be programmed in over the same serial bus. The high speed successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out−of−limit measurement. The ADM1024’s 2.8 V to 5.5 V supply voltage range, low supply current, and SMBus interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics. FEATURES http://onsemi.com TSSOP−24 CASE 948H MARKING DIAGRAM 1024 ARUZ #YYWW 1 xxx = Specific Device Code # = Pb−Free Package YYWW = Date Code • Up to Nine Measurement Channels • Inputs Programmable−to−Measure Analog Voltage, • External Temperature Measurement with Remote Diode • • • • • • • • • • (Two Channels) On−Chip Temperature Sensor Five Digital Inputs for VID Bits LDCM Support System Management Bus (SMBus) Chassis Intrusion Detect Interrupt and Overtemperature Outputs Programmable RESET Input Pin Shutdown Mode to Minimize Power Consumption Limit Comparison of All Monitored Values This is a Pb−Free Device Fan Speed or External Temperature PIN ASSIGNMENT NTEST_OUT/ADD 1 THERM 2 SDA 3 SCL 4 FAN1/AIN1 5 FAN2/AIN2 6 CI 7 GND 8 VCC 9 24 23 22 VID0/IRQ0 VID1/IRQ1 VID2/IRQ2 VID3/IRQ3 VID4/IRQ4 +VCCP1 +2.5VIN/D2+ VCCP2/D2– +5.0VIN +12VIN D1+ D1– (Top View) AD1024 21 20 19 18 17 16 15 14 13 INT 10 NTEST_IN/AOUT 11 RESET 12 APPLICATIONS ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. • Network Servers and Personal Computers • Microprocessor−Based Office Equipment • Test Equipment and Measuring Instruments © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 2 1 Publication Order Number: ADM1024/D ADM1024 VCC VID0/IRQ0 VID1/IRQ1 VID2/IRQ2 VID3/IRQ3 VID4/IRQ4 ADM1024 VID0–3 AND FAN DIVISOR REGISTER NTEST_OUT/ADD SERIAL BUS INTERFACE SDA SCL 100k W PULLUPS VID4 AND DEVICE ID REGISTER FAN SPEED COUNTER ADDRESS POINTER REGISTER CHANNEL MODE REGISTER VALUE AND LIMIT REGISTERS LIMIT COMPARATORS INTERRUPT STATUS REGISTERS INT MASK REGISTERS INTERRUPT MASKING CONFIGURATION REGISTERS CI FAN1/AIN1 FAN2/AIN2 +VCCP1 +2.5VIN /D2+ +5.0VIN +12VIN VCCP2/D2– D1+ D1– VCC BAND GAP TEMPERATURE SENSOR POWER TO CHIP INPUT ATTENUATORS AND ANALOG MULTIPLEXER TEMPERATURE CONFIGURATION REGISTER VCC 100k W VCC 100k W THERM INT 10−BIT ADC 2.5V BAND GAP REFERENCE ANALOG OUTPUT REGISTER AND 8−BIT DAC CHASSIS INTRUSION CLEAR REGISTER VCC 100k W NTEST_IN/AOUT RESET GND Figure 1. Functional Block Diagram ABSOLUTE MAXIMUM RATINGS Parameter Positive Supply Voltage (VCC) Voltage on 12 VIN Pin Voltage on AOUT, NTEST_OUT ADD, 2.5 VIN/D2+ Voltage on Any Other Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJMAX) Storage Temperature Range Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating All Pins Rating 6.5 20 −0.3 to (VCC +0.3) −0.3 to +6.5 ±5 ±20 150 −65 to +150 215 200 2000 Unit V V V V mA mA °C °C °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. THERMAL CHARACTERISTICS Package Type 24−Lead Small Outline Package qJA 50 qJC 10 Unit °C/W http://onsemi.com 2 ADM1024 PIN ASSIGNMENT Pin No. 1 2 3 4 5 6 7 Mnemonic NTEST_OUT/ADD THERM SDA SCL FAN1/AIN1 FAN2/AIN2 CI Description Digital I/O. Dual function pin. This is a three−state input that controls the two LSBs of the Serial Bus Address. This pin functions as an output when doing a NAND test. Digital I/O. Dual function pin. This pin functions as an interrupt output for temperature interrupts only, or as an interrupt input for fan control. It has an on−chip 100 kW pullup resistor. Digital I/O. Serial bus bidirectional data. Open−drain output. Digital Input. Serial bus clock. Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan tachometer input. Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan tachometer input. Digital I/O. An active high input from an external latch that captures a Chassis Intrusion event. This line can go high without any clamping action, regardless of the powered state of the ADM1024. The ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis Intrusion Latch. System Ground. Power (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combination of 10 mF (electrolytic or tantalum) and 0.1 mF (ceramic) bypass capacitors. Digital Output. Interrupt request (open−drain). The output is enabled when Bit 1 of Register 40h is set to 1. The default state is disabled. It has an on−chip 100 kW pullup resistor. Digital Input/Analog Output. An active−high input that enables NAND Test mode board−level connectivity testing. Refer to the section on NAND testing. Also functions as a programmable analog output when NAND Test is not selected. Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulse width. Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power−on reset). It has an on−chip 100 kW pullup resistor. Analog Input. Connected to cathode of first external temperature−sensing diode. Analog Input. Connected to anode of first external temperature−sensing diode. Programmable Analog Input. Monitors 12 V supply. Analog Input. Monitors 5.0 V supply. Programmable Analog Input. Monitors second processor core voltage or cathode of second external temperature−sensing diode. Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature−sensing diode. Analog Input. Monitors first processor core voltage (0 V to 3.6 V). Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor. Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor. Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor. Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor. Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor. 8 9 10 11 GND VCC INT NTEST_IN/AOUT 12 RESET 13 14 15 16 17 18 19 20 21 22 23 24 D1− D1+ +12 VIN +5.0 VIN VCCP2/D2– +2.5 VIN/D2+ +VCCP1 VID4/IRQ4 VID3/IRQ3 VID2/IRQ2 VID1/IRQ1 VID0/IRQ0 http://onsemi.com 3 ADM1024 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1 and 2) Parameter POWER SUPPLY Supply Voltage, VCC Supply Current, ICC Interface inactive, ADC Active ADC Inactive, DAC Active Shutdown Mode 0°C ≤ TA ≤ 100°C TA = 25°C ±1.0 0°C ≤ TA ≤ 100°C 25°C High level Low level (Note 3) 80 4.0 ±3.0 ±1.0 110 6.5 150 9.0 ±4.0 ±3.0 ±1.0 ±1.0 (Note 4) (Note 4) 80 754.8 9.6 140 5.0 0 IL = 2 mA ±1.0 No load Monotonic by design ±1.0 2.0 1.0 0°C ≤ TA ≤ 100°C Divisor = 1, fan count = 153 Divisor = 2, fan count = 153 Divisor = 3, fan count = 153 Divisor = 4, fan count = 153 0°C ≤ TA ≤ 100°C IOUT = +3.0 mA, VCC = 2.85 V −3.60 V IOUT = −3.0 mA, VCC = 2.85 V −3.60 V IOUT = 3.0 mA, VCC = 3.60 V VOUT = VCC 20 0.1 45 19.8 2.4 0.4 0.4 100 8800 4400 2200 1100 22.5 25.2 ±12 255 RPM 2.0 ±1.0 2.5 ±3.0 ±5.0 200 856.8 ±5.0 2.8 3.3 1.4 1.0 45 5.5 3.5 145 ±3.0 ±2.0 V mA mA °C °C °C °C mA Test Conditions/Comments Min Typ Max Unit TEMPERATURE−TO−DIGITAL CONVERTER Internal Sensor Accuracy Resolution External Diode Sensor Accuracy Resolution Remote Sensor Source Current ANALOG−TO−DIGITAL CONVERTER (Including MUX and ATTENUATORS) Total Unadjusted Error (TUE) (12 VIN) TUE (AIN, VCCP, 2.5 VIN, 5.0 VIN) Differential Non−linearity (DNL) Power Supply Sensitivity Conversion Time (Analog Input or Internal Temperature) Conversion Time (External Temperature) Input Resistance (2.5 V, 5.0 V, 12 V, VCCP1, VCCP2) Input Resistance (AIN1, AIN2) ANALOG OUTPUT Output Voltage Range Total Unadjusted Error (TUE) Full−Scale Error Zero−Scale Error Differential Non−linearity (DNL) Integral Non−linearity Output Source Current Output Sink Current FAN RPM−TO−DIGITAL CONVERTER Accuracy Full−Scale Count FAN1 to FAN2 Nominal Input RPM (Note 5) % V % % LSB LSB LSB mA mA % % LSB %/V ms ms kW MW Internal Clock Frequency DIGITAL OUTPUTS (NTEST_OUT) Output High Voltage, VOH Output Low Voltage, VOL Output Low Voltage, VOL High Level Output Leakage Current, IOH RESET and CI Pulsewidth kHz V V V mA ms OPEN−DRAIN DIGITAL OUTPUTS (INT, THERM, RESET) (Note 6) http://onsemi.com 4 ADM1024 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1 and 2) Parameter OPEN−DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Glitch Immunity DIGITAL INPUT LOGIC LEVELS (ADD, CI, RESET, VID0−VID4, FAN1, FAN2) (Note 7) Input High Voltage, VIH Input Low Voltage, VIL NTEST_IN Input High Current, IIH DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING (Note 8) Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU; STA Start Hold Time, tHD; STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 100 900 1.3 600 600 1.3 0.6 300 300 400 50 kHz ns ms ns ns ms ms ns ms ns ns VIN = VCC VIN = 0 20 –1.0 1.0 mA mA pF VCC = 2.85 V − 5.5 V 2.2 V VCC = 2.85 V − 5.5 V VCC = 2.85 V − 5.5 V 2.2 0.8 V V 500 100 2.2 0.8 V V mV ns IOUT = −3.0 mA, VCC = 2.85 V −3.60 V VOUT = VCC 0.1 0.4 100 V mA Test Conditions/Comments Min Typ Max Unit 1. All voltages are measured with respect to GND, unless otherwise specified. 2. Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V. 3. TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on−chip input attenuators, including an external series input protection resistor value between 0 kW and 1 kW. 4. Total monitoring cycle time is nominally m × 755 ms + n × 33244 ms, where m is the number of channels configured as analog inputs, plus 2 for the internal VCC measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (D1 and D2). 5. The total fan count is based on two pulses per revolution of the fan tachometer output. 6. Open−drain digital outputs may have an external pullup resistor connected to a voltage lower or higher than VCC (up to 6.5 V absolute maximum). 7. All logic inputs except ADD are tolerant of 5.0 V logic levels, even if VCC is less than 5.0 V. ADD is a three−state input that may be connected to VCC, GND, or left open−circuit. 8. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. tR tLOW SCL tF tHD:STA tHD:STA SDA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO tBUF P S S P Figure 2. Serial Bus Timing Diagram http://onsemi.com 5 ADM1024 TYPICAL PERFORMANCE CHARACTERISTICS 30 20 TEMPERATURE ERROR (°C) TEMPERATURE ERROR (5C) 10 0 –10 DXP TO VCC (5.0 V) –20 –30 –40 –50 –60 1 3.3 10 LEAK RESISTANCE (MΩ) 30 100 6 5 DXP TO GND 4 3 2 1 100mV p−p REMOTE 0 –1 50 250mV p−p REMOTE 500 5k 50k 500k 5M 50M FREQUENCY (Hz) Figure 3. Temperature Error vs. PC Board Track Resistance 25 Figure 4. Temperature Error vs. Power Supply Noise Frequency 110 100 20 TEMPERATURE ERROR (5C) 100mV p−p 90 80 70 15 10 50mV p−p READING 50M 60 50 40 30 5 0 25mV p−p 20 10 –5 50 500 5k 50k 500k 5M 0 0 10 20 30 FREQUENCY (Hz) 40 50 60 70 80 MEASURED TEMPERATURE 90 100 110 Figure 5. Temperature Error vs. Common−Mode Noise Frequency 25 Figure 6. Pentium) III Temperature vs. ADM1024 Reading 10 9 20 TEMPERATURE ERROR (5C) TEMPERATURE ERROR (5C) 8 7 6 5 4 3 2 1 10mV SQ. WAVE 15 10 5 0 –5 1 2.2 3.2 4.7 7 10 0 50 500 5k 50k 100k 500k 5M 25M 50M DXP−DXN CAPACITANCE (nF) FREQUENCY (Hz) Figure 7. Temperature Error vs. Capacitance Between D+ and D– Figure 8. Temperature Error vs. Differential−Mode Noise Frequency http://onsemi.com 6 ADM1024 TYPICAL PERFORMANCE CHARACTERISTICS 26.5 26.0 STANDBY CURRENT (mA) 25.5 25.0 24.5 24.0 23.5 23.0 22.5 –40 VDD = 3.3 V –20 0 20 40 60 80 100 120 TEMPERATURE (5C) Figure 9. Standby Current vs. Temperature http://onsemi.com 7 ADM1024 General Description Processor Voltage ID The ADM1024 is a complete system hardware monitor for microprocessor−based systems. The device communicates with the system via a serial SMBus. The serial bus controller has a hardwired address line for device selection (Pin 1), a serial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (Pin 3), and an input line for the serial clock (Pin 4). All control and programming functions of the ADM1024 are performed over the serial bus. Measurement Inputs Five digital inputs (VID4 to VID0—Pins 20 to 24) read the processor voltage ID code. These inputs can also be reconfigured as interrupt inputs. The VID pins have internal 100 kW pullup resistors. Chassis Intrusion A chassis intrusion input (Pin 7) is provided to detect unauthorized tampering with the equipment. RESET Programmability of the measurement inputs makes the ADM1024 extremely flexible and versatile. The device has a 10−bit ADC and nine measurement input pins that can be configured in different ways. Pins 5 and 6 can be programmed as general−purpose analog inputs with a range of 0 V to 2.5 V, or as digital inputs to monitor the speed of fans with digital tachometer outputs. The fan inputs can be programmed to accommodate fans with different speeds and different numbers of pulses per revolution from their tachometer outputs. Pins 13 and 14 are dedicated temperature inputs and may be connected to the cathode and anode of an external temperature sensing diode. Pins 15, 16, and 19 are dedicated analog inputs with on−chip attenuators, configured to monitor 12 V, 5.0 V, and the processor core voltage, respectively. Pins 17 and 18 may be configured as analog inputs with on−chip attenuators to monitor a second processor core voltage and a 2.5 V supply, or they may be configured as a temperature input and connected to a second temperature−sensing diode. The ADC also accepts input from an on−chip band gap temperature sensor that monitors system−ambient temperature. Finally, the ADM1024 monitors the supply from which it is powered, so there is no need for a separate 3.3 V analog input if the chip VCC is 3.3 V. The range of this VCC measurement can be configured for either a 3.3 V or 5.0 V VCC by Bit 3 of the Channel Mode Register. Sequential Measurement A RESET input/output (Pin 12) is provided. Pulling this pin low will reset all ADM1024 internal registers to default values. The ADM1024 can also be programmed to give a low going 45 ms reset pulse at this pin. Analog Output The ADM1024 contains an on−chip, 8−bit DAC with an output range of 0 V to 2.5 V (Pin 11). This is typically used to implement a temperature−controlled fan by controlling the speed of a fan dependent upon the temperature measured by the on−chip temperature sensor. Testing of board level connectivity is simplified by providing a NAND tree test function. The AOUT (Pin 11) also doubles as a NAND test input, while Pin 1 doubles as a NAND tree output. Internal Registers of the ADM1024 When the ADM1024 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in Value Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out−of−limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT line (Pin 10). Any or all of the Interrupt Status Bits can be masked by appropriate programming of the Interrupt Mask Register. A brief description of the ADM1024’s principal internal registers follows. More detailed information on the function of each register is given in Table 6 to Table 19: ♦ Configuration Registers: Provide control and configuration. ♦ Channel Mode Register: Stores the data for the operating modes of the input channels. ♦ Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1024, the first byte of data is always a register address, which is written to the Address Pointer Register. ♦ Interrupt (INT) Status Registers: Two registers to provide status of each interrupt event. These registers are also mirrored at addresses 4Ch and 4Dh. ♦ Interrupt (INT) Mask Registers: Allow masking of individual interrupt sources. ♦ Temperature Configuration Register: The configuration of the temperature interrupt is controlled by the lower three bits of this register. ♦ VID/Fan Divisor Register: The status of the VID0 to VID4 pins of the processor can be written to and read from these registers. Divisor values for fan speed measurement are also stored in this register. http://onsemi.com 8 ADM1024 ♦ ♦ ♦ Value and Limit Registers: The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values. Analog Output Register: The code controlling the analog output DAC is stored in this register. Chassis Intrusion Clear Register: A signal latched on the chassis intrusion pin can be cleared by writing to this register. Serial Bus Interface Control of the ADM1024 is carried out via the serial bus. The ADM1024 is connected to this bus as a slave device, under the control of a master device, e.g., ICH. The ADM1024 has a 7−bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The 5 MSBs of the address are set to 01011, and the 2 LSBs are determined by the logical states of Pin 1 (NTEST OUT/ADD). This is a three−state input that can be grounded, connected to VCC, or left open−circuit to give three different addresses. Table 1. ADD Pin Truth Table ADD Pin GND No Connect VCC A1 1 0 0 A0 0 0 1 If ADD is left open−circuit, the default address will be 0101100. ADD is sampled only at powerup, so any changes made while power is on will have no immediate effect. The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADM1024 is used in a system. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high−to−low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7−bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low−to−high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single Read or Write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In Write mode, the master will pull the data line high during the tenth clock pulse to assert a STOP condition. In Read mode, the master device will override the Acknowledge Bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADM1024, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the Address Pointer Register. This is illustrated in Figure 10 The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities: 1. If the ADM1024’s Address Pointer Register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADM1024 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. This is shown in Figure 11. http://onsemi.com 9 ADM1024 A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 12. 2. If the Address Pointer Register is known to be already at the desired address, data can be read 1 SCL 9 from the corresponding data register without first writing to the Address Pointer Register, so Figure 11 can be omitted. 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADM1024 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1024 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1024 STOP BY MASTER FRAME 3 DATA BYTE Figure 10. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADM1024 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1024 STOP BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE Figure 11. Writing to the Address Pointer Register Only 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADM1024 D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. STOP BY BY MASTER MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADM1024 Figure 12. Reading Data from a Previously Selected Register NOTES 1. Although it is possible to read a data byte from a data register without first writing to the Address Pointer Register, if the Address Pointer Register is already at the correct value, it is not possible to write data to a register without writing to the Address Pointer Register because the first data byte of a write is always written to the Address Pointer Register. 2. In Figure 10 to Figure 12, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are set by the three−state ADD pin. Measurement Inputs The ADM1024 has nine external measurement pins that can be configured to perform various functions by programming the Channel Mode Register. Pins 13 and 14 are dedicated to temperature measurement, while Pins 15, 16, and 19 are dedicated analog input channels. Their function is unaffected by the Channel Mode Register. Pins 5 and 6 can be individually programmed as analog inputs, or as digital fan speed measurement inputs, by programming Bits 0 and 1 of the Channel Mode Register. Bit 3 of the Channel Mode Register configures the internal VCC measurement range for either 3.3 V or 5.0 V. http://onsemi.com 10 ADM1024 Bits 4 to 6 of the Channel Mode Register enable or disable Pins 22 to 24 when they are configured as interrupt inputs by setting Bit 7 of the Channel Mode Register. This function is controlled for Pins 20 and 21 by Bits 6 and 7 of Configuration Register 2. Pins 17 and 18 can be configured as analog inputs or as inputs for external temperature−sensing diodes by programming Bit 2 of the Channel Mode Register. Bit 7 of the Channel Mode Register allows the processor core voltage ID bits (VID0 to VID4, Pins 24 to 20) to be reconfigured as interrupt inputs. A truth table for the Channel Mode Register is given in Table 2. Table 2. Channel Mode Register (Note 1) Channel Mode Register Bit 0 1 2 3 4 5 6 7 Controls Pin(s) 5 6 17, 18 Int. VCC Meas. 24 23 22 20–24 Function 0 = FAN1, 1 = AIN1 0 = FAN2, 1 = AIN2 0 = 2.5 V, VCCP2, 1 = D2–, D2+ 0 = 3.3 V, 1 = 5.0 V 0 = VID0, 1 = IRQ0 0 = VID1, 1 = IRQ1 0 = VID2, 1 = IRQ2 0 = VID0 to VID4, 1 = Interrupt Inputs 1. Power−On Default = 0000 0000 Table 3. A/D Output Code vs. VIN Input Voltage +12 VIN