ADP3118

Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3118 FEATURES Optimized for low gate charge MOSFETs All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel VRM 10 Meets CPU VR requirement when used with Analog Devices, Inc. Flex-Mode1 controller GENERAL DESCRIPTION The ADP3118 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3118 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3118 is specified over the commercial temperature range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead LFCSP packages. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM VIN 12V VCC D1 4 1 ADP3118 BST CBST2 CBST1 DRVH RG IN 2 8 Q1 TO INDUCTOR DELAY SW RBST 7 CMP VCC 6 DRVL CMP 1V CONTROL LOGIC 5 Q2 Figure 1. 1 Flex-Mode™ is protected by U.S. Patent 6683441. ©2008 SCILLC. All rights reserved. January 2008 – Rev. 2 Publication Order Number: ADP3118/D 05452-001 OD 3 DELAY 6 PGND ADP3118 TABLE OF CONTENTS Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Simplified Functional Block Diagram............................................1 Revision History................................................................................2 Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................4 ESD Caution ..................................................................................4 Pin Configuration and Function Descriptions .............................5 Timing Characteristics .....................................................................6 Typical Performance Characteristics..............................................7 Theory of Operation.........................................................................9 Low-Side Driver ............................................................................ 9 High-Side Driver........................................................................... 9 Overlap Protection Circuit .......................................................... 9 Application Information ................................................................10 Supply Capacitor Selection........................................................10 Bootstrap Circuit ........................................................................10 MOSFET Selection .....................................................................10 High-Side (Control) MOSFETs ................................................10 Low-Side (Synchronous) MOSFETs.........................................11 PC Board Layout Considerations .............................................11 Outline Dimensions........................................................................13 Ordering Guide ...........................................................................13 REVISION HISTORY 01/08 - Rev 2: Conversion to ON Semiconductor 9/07—Rev. 0 to Rev. A Added LFCSP...................................................................... Universal Updated Outline Dimensions........................................................13 Changes to Ordering Guide...........................................................13 4/05—Revision 0: Initial Version Rev. 2 | Page 2 of 14 | www.onsemi.com ADP3118 SPECIFICATIONS VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter PWM INPUT Input Voltage High Input Voltage Low Input Current Hysteresis OD INPUT Input Voltage High Input Voltage Low Input Current Hysteresis Propagation Delay Times2 Symbol Conditions Min 2.0 −1 90 2.0 −1 90 tpdlOD tpdhOD HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis 1 2 Typ Max Unit V V μA mV V V μA mV ns ns Ω Ω kΩ ns ns ns ns kΩ Ω Ω kΩ ns ns ns ns ns ns V mA V mV 0.8 +1 250 0.8 +1 250 20 40 2.2 1.0 10 25 20 25 25 10 2.0 1.0 10 20 16 12 30 190 150 35 55 3.5 2.5 40 30 40 35 See Figure 3 See Figure 3 BST − SW = 12 V BST − SW = 12 V BST − SW = 0 V BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 SW to PGND trDRVH tfDRVH tpdhDRVH tpdlDRVH 3.2 2.5 35 30 35 45 trDRVL tfDRVL tpdhDRVL tpdlDRVL VCC = PGND CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 SW = 5 V SW = PGND 110 95 4.15 VCC ISYS BST = 12 V, IN = 0 V VCC rising 2 1.5 350 13.2 5 3.0 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low. Rev. 2 | Page 3 of 14 | www.onsemi.com ADP3118 ABSOLUTE MAXIMUM RATINGS Unless otherwise specified, all voltages are referenced to PGND. Table 2. Parameter VCC BST BST to SW SW DC