a
FEATURES
Optimally Compensated Active Voltage Positioning
with Gain and Offset Adjustment (ADOPT™) for
Superior Load Transient Response
Complies with VRM 8.5 Specifications with Lowest
System Cost
5-Bit Digitally Programmable 1.05 V to 1.825 V Output
N-Channel Synchronous Buck Controller
Onboard 1.8 V Linear Regulator Controller
Total Accuracy 1% Over Temperature
High Efficiency Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional External
Components
VRM 8.5 Compatible
Single Phase Core Controller
ADP3170
FUNCTIONAL BLOCK DIAGRAM
SD
VCC
CT
UVLO
AND BIAS
OSCILLATOR
SET
RESET
CROWBAR
3.0V
REFERENCE
DRVH
PWM
LOGIC
DRVL
PGND
REF
DAC +20%
GND
PWRGD
REF
1.8V
LRFB
DAC –20%
LRDRV
CS–
CMP
APPLICATIONS
Core and 1.8 V Standby Supplies for Next Generation
Intel Pentium® III Processors
CS+
ADP3170
FB
gm
COMP
REF
VID
DAC
VID3 VID2 VID1 VID0 VID25
GENERAL DESCRIPTION
The ADP3170 is a highly efficient output synchronous buck
switching regulator controller optimized for converting a 5 V
main supply into the core supply voltage required by next
generation Intel Celeron processors. The ADP3170 uses an
internal 5-bit DAC to read a voltage identification (VID)
code directly from the processor, which is used to set the
output voltage between 1.05 V and 1.825 V. The ADP3170
uses a current mode, constant off-time architecture to drive two
N-channel MOSFETs at a programmable switching frequency
that can be optimized for regulator size and efficiency.
The ADP3170 also uses a unique supplemental regulation technique called Analog Devices Optimal Positioning Technology
(ADOPT) to enhance load transient performance. Active
voltage positioning results in a dc/dc converter that meets the
stringent output voltage specifications for high performance
processors, with the minimum number of output capacitors and
smallest footprint. Unlike voltage-mode and standard current-
mode architectures, active voltage positioning adjusts the output
voltage as a function of the load current so that it is always
optimally positioned for a system transient. The ADP3170 also
provides accurate and reliable short circuit protection and
adjustable current limiting. It also includes an integrated
overvoltage crowbar function to protect the microprocessor
from destruction in case the core supply exceeds the nominal
programmed voltage by more than 20%.
The ADP3170 contains a 1.8 V linear regulator controller that
is designed to drive an external N-channel MOSFET. This linear
regulator can be used to generate auxiliary voltages (such as 1.8 V
standby power) required in most motherboard designs, and has
been designed to provide a high bandwidth load-transient response.
The ADP3170 is specified over the commercial temperature range
of 0°C to 70°C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADP3170–SPECIFICATIONS1
Parameter
Symbol
FEEDBACK INPUT
Output Accuracy
1.05 V Output
1.5 V Output
1.825 V Output
Line Regulation
Input Bias Current
Crowbar Trip Point
Crowbar Reset Point
Crowbar Response Time
tCROWBAR
REFERENCE
Output Voltage
Output Current
VREF
IREF
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Pull-up Resistance
Internal Pull-up Voltage
Conditions
Min
Typ
Max
Unit
Figure 1
Figure 1
Figure 1
VCC = 10 V to 14 V
1.039
1.485
1.807
1.061
1.515
1.843
% of Nominal DAC Voltage
% of Nominal DAC Voltage
Overvoltage to DRVL Going High
115
40
1.05
1.5
1.825
0.06
5
120
50
400
V
V
V
%
nA
%
%
ns
VFB
∆VOUT
IFB
VCROWBAR
VIL(VID)
VIH(VID)
IVID
RVID
2.937
300
VIL(SD)
VIH(SD)
ISD
OSCILLATOR
Off Time
CT Charge Current
ICT
ERROR AMPLIFIER
Output Resistance
Transconductance
Output Current
Maximum Output Voltage
Output Disable Threshold
–3 dB Bandwidth
RO(ERR)
gm(ERR)
IO(ERR)
VCOMP(MAX)
VCOMP(OFF)
BWERR
CURRENT SENSE
Threshold Voltage
VCS(TH)
ICS+, ICS–
tCS
3.0
50
125
60
3.048
V
µA
0.8
V
V
µA
kΩ
V
2.3
VID(X) = 0 V
2.75
SHUTDOWN INPUT
Input Low Voltage
Input High Voltage
Input Current
Input Bias Current
Response Time
(VCC = 12 V, IREF = 150 A, TA = 0C to 70C, unless otherwise noted.)
300
16
3.1
425
3.4
0.8
1
V
V
µA
4.5
170
45
µs
µA
µA
2.0
TA = 25°C, CT = 200 pF
TA = 25°C, VOUT in Regulation
TA = 25°C, VOUT = 0 V
3.5
130
25
2.05
FB = 0
FB Forced to VOUT – 3%
600
COMP = Open
FB Forced to VOUT – 3%
FB ≤ 0.45 V
0.8 V ≤ COMP ≤ 1 V
CS+ = CS– = VOUT
CS+ – (CS–) > 87 mV
to DRVH going low
OUTPUT DRIVERS
Output Resistance
Output Transition Time
RO(DRV[X])
t R , tF
IL = 50 mA
CL = 3000 pF
LINEAR REGULATOR
Feedback Current
LR Feedback Voltage
Driver Output Voltage
ILRFB
VLRFB
VLRDRV
Figure 2, VCC = 4.5 V to 12.6 V
VCC = 4.5 V, VLRFB(X) = 0 V
–2–
69
35
4.0
150
35
1
2.2
625
3.0
750
500
78
45
1
0.5
50
2.35
900
87
54
5
5
0.3
1.8
mV
mV
mV
µA
ns
Ω
ns
4.5
75
1.75
4.2
MΩ
mmho
µA
V
mV
kHz
1
1.85
µA
V
V
REV. 0
ADP3170
Parameter
POWER GOOD COMPARATOR
Undervoltage Threshold
Undervoltage Hysteresis
Overvoltage Threshold
Overvoltage Reset Point
Output Voltage Low
Response Time
Symbol
Conditions
Min
Typ
Max
Unit
VPWRGD(UV)
% of Nominal DAC Voltage
% of Nominal DAC Voltage
% of Nominal DAC Voltage
% of Nominal DAC Voltage
IPWRGD(SINK) = 1 mA
74
80
5
120
50
250
200
86
%
%
%
%
mV
ns
VPWRGD(OV)
VOL(PWRGD)
SUPPLY
DC Supply Current2
UVLO Threshold Voltage
UVLO Hysteresis
ICC
VUVLO
114
40
6.75
0.8
7.5
7
1
126
60
500
9.5
7.25
1.2
mA
V
V
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
DRVH, DRVL, LRDRV . . . . . . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs & Outputs . . . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to GND.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADP3170JRU
0°C to 70°C
TSSOP
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3170 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3170
PIN CONFIGURATION
RU-20
VID3 1
20
GND
VID2 2
19
PGND
VID1 3
18
DRVH
VID0 4
17
DRVL
16
VCC
VID25 5
ADP3170
TOP VIEW 15 LRFB
(Not to Scale)
7
14 LRDRV
REF
PWRGD 6
SD 8
13
COMP
FB
9
12
CT
CS–
10
11
CS+
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1–5
6
7
8
VID3, VID2,
VID1, VID0,
VID25
PWRGD
REF
SD
9
10
11
FB
CS–
CS+
12
13
CT
COMP
14
15
16
17
LRDRV
LRFB
VCC
DRVL
18
DRVH
19
PGND
20
GND
Voltage Identification DAC Inputs. These pins are pulled up to an internal reference,
providing a logic one if left open. The DAC output programs the FB regulation voltage from
1.05 V to 1.825 V.
Open drain output that signals when the output voltage is in the proper operating range.
3.0 V Reference Output.
Regulator Shutdown. Pulling this pin high turns off both MOSFETs of the switching
regulator. SD has no effect on the linear regulator controller.
Feedback Input. Error amplifier input for remote sensing of the output voltage.
Current Sense Negative Node. Negative input for the current comparator.
Current Sense Positive Node. Positive input for the current comparator. The output current is
sensed as a voltage at this pin with respect to CS–.
External capacitor connected from CT to ground sets the OFF-Time of the device.
Error Amplifier Output and Compensation Point. The voltage at this output programs the
output current control level between CS+ and CS–.
Gate Drive for the 1.8 V linear regulator N-channel MOSFET.
Feedback Connections for the 1.8 V linear regulator controller.
Supply Voltage for the ADP3170.
Low-Side MOSFET Drive. Gate drive for the synchronous rectifier N-channel MOSFET.
The voltage at DRVL swings from GND to VCC.
High-Side MOSFET Drive. Gate drive for the buck switch N-channel MOSFET. The voltage
at DRVH swings from GND to VCC.
Power Ground. PGND should have a low impedance path to the source of the synchronous
MOSFET.
Small-Signal Ground. This ground reference can be used in conjunction with FB to provide
remote sensing of the output voltage at the CPU pins.
–4–
REV. 0
ADP3170
ADP3170
5-BIT CODE
VFB
1
VID3
GND 20
2
VID2
PGND 19
3
VID1
DRVH 18
4
VID0
DRVL 17
5
VID25
6
PWRGD
7
REF
8
SD
9
10
FB
CS–
ADP3170
12V
VCC 16
LRFB 15
1F
100nF
LRDRV 14
COMP 13
CT 12
100
1
VID3
GND 20
2
VID2
PGND 19
3
VID1
DRVH 18
4
VID0
DRVL 17
5
VID25
6
PWRGD
7
REF
8
SD
VCC
1F
100nF
VCC 16
VLR
LRFB 15
100nF
CS+ 11
LRDRV 14
COMP 13
10nF
AD820
9
1.2V
10
CT 12
CS+ 11
Figure 2. Linear Regulator Output Voltage Accuracy
Test Circuit
Figure 1. Closed-Loop Output Voltage Accuracy
Test Circuit
REV. 0
FB
CS–
–5–
ADP3170–Typical Performance Characteristics
TEK RUN
100
TRIG'D
TA = 25 C
SUPPLY CURRENT – mA
80
60
VCC
1
40
20
VCORE
2
0
0
100
200
300
400
SWITHCHING FREQUENCY – kHz
500
CH1 5.00V BW CH2
TPC 1. Supply Current vs. Operating Frequency Using
MOSFETs of Figure 3
500mV BW M 10.0ms A CH1
0.00000 s
5.90V
TPC 4. Power-On Start-Up Waveform
25
TA = 25 C
VOUT = 1.5V
T
NUMBER OF PARTS – %
20
1
15
10
5
2
0
CH1 5.00V
BW CH2 5.00V BWM 400ns
A
CH1
6.60V
TPC 2. Gate Switching Waveforms Using MOSFETs
of Figure 3
–0.6
0
OUTPUT ACCURACY – % OF NOMINAL
0.6
TPC 5. Output Accuracy Distribution
T
1
CH1 2.00V
BW CH2 2.00V BWM 40.0ns A CH1
5.76V
TPC 3. Driver Transition Waveforms Using MOSFETs
of Figure 3
–6–
REV. 0
ADP3170
THEORY OF OPERATION
The output of the latch forces the low side drive output to go low
and the high side drive output to go high. As a result, the low side
switch is turned off and the high side switch is turned on. The
sequence is then repeated. As the load current increases, the output
voltage starts to decrease. This causes an increase in the output of
the voltage-error amplifier, which, in turn, leads to an increase in
the current comparator threshold, thus tracking the load current.
To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins.
Before the low side drive output can go high, the high side drive
output must be low. Likewise, the high side drive output is unable
to go high while the low side drive output is high.
The ADP3170 uses a current-mode, constant off-time control
technique to switch a pair of external N-channel MOSFETs in
a synchronous buck topology. Constant off-time operation
offers several performance advantages, including that no slope
compensation is required for stable operation. A unique feature
of the constant off-time control technique is that since the offtime is fixed, the converter’s switching frequency is a function
of the ratio of input voltage to output voltage. The fixed offtime is programmed by the value of an external capacitor
connected to the CT pin. The on-time varies in such a way
that a regulated output voltage is maintained as described
below in the cycle-by-cycle operation. Under fixed operating
conditions the on-time does not vary, and it varies only slightly
as a function of load. This means that switching frequency is
fairly constant in standard VRM applications.
Output Crowbar
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 20% greater than the
targeted value, the ADP3170 will turn on the lower MOSFET,
which will current-limit the source power supply or blow its fuse,
pull down the output voltage, and thus save the microprocessor
from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the
output is programmed to 1.5 V, but is pulled up to 1.85 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 0.75 V, the crowbar
will release, allowing the output voltage to recover to 1.5 V if
the fault condition has been removed.
Active Voltage Positioning
The output voltage is sensed at the CS– pin. A voltage error
amplifier, (gm), amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed to between 1.05 V and 1.825 V by an
internal 5-bit DAC, which reads the code at the voltage identification (VID) pins. (Refer to Table I for output voltage vs. VID
pin code information.) A unique supplemental regulation technique called Analog Devices Optimal Positioning Technology
(ADOPT) adjusts the output voltage as a function of the load
current so that it is always optimally positioned for a load
transient. Standard (passive) voltage positioning, sometimes
recommended for use with other architectures, has poor dynamic
performance that renders it ineffective under the stringent
repetitive transient conditions specified in Intel VRM documents.
Consequently, such techniques do not allow the minimum
possible number of output capacitors to be used. ADOPT, as
used in the ADP3170, provides a bandwidth for transient
response that is limited only by parasitic output inductance.
This yields optimal load transient response with the minimum
number of output capacitors.
Onboard Linear Regulator Controller
The ADP3170 includes a linear regulator controller to provide a
low cost solution for generating an additional supply rail. This
regulator is internally set to 1.8 V with ± 2.8% accuracy. The
output voltage is sensed by the high input impedance LRFB
pin and compared to an internal fixed reference. The LRDRV
pin controls the gate of an external N-channel MOSFET
resulting in a negative feedback loop. The only additional
components required are a capacitor and resistor for stability.
Higher output voltages can be generated by placing a resistor
divider between the linear regulator output and its LRFB pin.
The maximum output load current is determined by the size
and thermal impedance of the external power MOSFET that
is placed in series with the supply and controlled by the ADP3170.
Reference Output
A 3.0 V reference is available on the ADP3170. This reference
is normally used to accurately set the voltage positioning using a
resistor divider to the COMP pin. In addition, the reference can
be used for other functions such as generating a regulated voltage with an external amplifier. The reference is bypassed with a
1 nF capacitor to ground. It is not intended to drive larger
capacitive loads, and it should not be used to provide more than
300 µA of output current.
APPLICATION INFORMATION
Specifications for a Design Example
The design parameters for a typical VRM 8.5-compliant
Pentium III application (shown in Figure 3) are as follows:
Input voltage: (VIN) = 5 V
Cycle-by-Cycle Operation
Auxiliary input: (VCC) = 12 V
During normal operation (when the output voltage is regulated), the voltage error amplifier and the current comparator
are the main control elements. During the on-time of the high
side MOSFET, the current comparator monitors the voltage
between the CS+ and CS– pins. When the voltage level between
the two pins reaches the threshold level, the DRVH output is
switched to ground, which turns off the high side MOSFET.
The timing capacitor CT is then charged at a rate determined
by the off-time controller. While the timing capacitor is charging,
the DRVL output goes high, turning on the low side MOSFET.
When the voltage level on the timing capacitor has charged to
the upper threshold voltage level, a comparator resets a latch.
REV. 0
VID setting voltage: (VOUT) = 1.8 V
Nominal output voltage at no load (VONL) = 1.845 V
Nominal output voltage at maximum load (VOFL) = 1.771 V
Static output voltage drop based on a 3.2 mW load line
(ROUT) from no load to full load (V∆) = VONL – VOFL =
1.845 V – 1.771 V = 74 mV
Maximum output current (IO[MAX]) = 23 A
–7–
ADP3170
Table I. Output Voltage vs. VID Code
CT Selection for Operating Frequency
The ADP3170 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high-side N-channel MOSFET switch turns on, the voltage
across CT is reset to approximately 0 V. During the off-time,
CT is charged by a constant current of 150 µA. Once CT reaches
3.0 V, a new on-time cycle is initiated. The value of the off-time is
calculated using the continuous-mode operating frequency.
Assuming a nominal operating frequency (fNOM) of 200 kHz
at an output voltage of 1.8 V, the corresponding off-time is:
V
1
tOFF = 1 – OUT ×
=
VIN f NOM
1.8 V
1
1 – 5 V × 200 kHz = 3.2 µs
(1)
The timing capacitor cab be calculated from the equation:
CT =
tOFF × I CT 3.2 µs × 150 µA
=
≈ 150 pF
3V
VT (TH )
(2)
The converter operates at the nominal operating frequency only
at the above-specified VOUT and at light load. At higher values of
VOUT, or under heavy load, the operating frequency decreases
due to the parasitic voltage drops across the power devices. The
actual minimum frequency at VOUT = 1.8 V is calculated to be
183 kHz (see Equation 3), where:
RDS(ON)HSF is the resistance of the high-side MOSFET
(estimated value: 6 mΩ)
R DS(ON)LSF is the resistance of the low-side MOSFET
(estimated value: 6 mΩ)
RSENSE is the resistance of the sense resistor
(estimated value: 2.5 mΩ)
RL is the resistance of the inductor
(estimated value: 3 mΩ)
f MIN =
1
tOFF
×
VID3
VID2
VID1
VID0
VID25
VOUT(NOM)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.050 V
1.075 V
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.500 V
1.525 V
1.550 V
1.575 V
1.600 V
1.625 V
1.650 V
1.675 V
1.700 V
1.725 V
1.750 V
1.775 V
1.800 V
1.825 V
VIN – IO ( MAX ) × (RDS ( ON )HSF + RSENSE + RL ) – VOUT
VIN – IO ( MAX ) × (RDS ( ON )HSF + RSENSE + RL – RDS ( ON )LSF )
=
1
5V – 23 A × (6 mΩ + 3 mΩ ) – 1.8 V
×
= 183 kHz
3.3 µs 5V – 23 A × (6 mΩ + 2.5 mΩ + 3 mΩ – 6 mΩ))
Inductance Selection
For 6 A peak-to-peak ripple current, which corresponds to
approximately 25% of the 23 A full-load dc current in an inductor,
Equation 4 yields an inductance of:
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. The following equation shows the relationship between the inductance, oscillator
frequency, peak-to-peak ripple current in an inductor and input
and output voltages:
L=
VOUT × tOFF
I L ( RIPPLE )
(3)
L=
1.8 V × 3.3 µs
= 990 nH
6A
A 1 µH inductor can be used, which gives a calculated ripple
current of 5.9 A at no load. The inductor should not saturate at
the peak current of 26 A and should be able to handle the sum
of the power dissipation caused by the average current of 23 A
in the winding and the core loss.
(4)
–8–
REV. 0
ADP3170
Designing an Inductor
such as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
Once the inductance is known, the next step is either to design
an inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. The first decision
in designing the inductor is to choose the core material. There
are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-M®
from Magnetics, Inc.) and the gapped soft ferrite cores (e.g.,
3F3 or 3F4 from Philips). Low frequency powdered iron cores
should be avoided due to their high core loss, especially when
the inductor value is relatively low and the ripple current is high.
There are many useful references for quickly designing a power
inductor. Table II gives some examples.
Table II. Magnetics Design References
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters
Two main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed
magnetic field may create problems with noise interference in
the circuitry surrounding the inductor. Closed-loop types,
McLyman, Kg Magnetics
ISBN 1-883107-00-08
L1
1.7H
5V
D1
MBR052LT1
C1
1000F
C2
1000F
C3
1000F
12V
C6
4.7nF
D2
MBR052LT1
FROM
CPU
VTT PWRGD CLK
C5
1000F
C12
22F
U1
C7
100nF
5V SB
C4
1000F
Q1
FDB7045L
L1
R6
1H
2.5m
ADP3170
1
VID3
GND 20
2
VID2
PGND 19
3
VID1
DRVH 18
4
VID0
DRVL 17
5
VID25
6
PWRGD
7
REF
8
SD
COMP 13
9
FB
CT 12
10
Q2
FDB7045L
1000F 8
RUBYCON ZA SERIES
24m ESR (EACH)
VCC(CORE)
1.05V – 1.825V
23A
VCC(CORE) RTN
C13 C14 C15 C16 C17 C18 C19 C20
VCC 16
LRFB 15
C22
68pF
LRDRV 14
CS+ 11
CS–
C19
150pF
COC
2.7nF
RB
30.1k
1%
5V SB
RA
13.7k
1%
Q6
IRL3103
R7
10k
C21
1F
1.8V SB
1.8V, 200mA
C11
1nF
R1
1k
R4
220
R5
220
C23
220F
C8
100pF
CORE
PWRGD
TO CPU
Figure 3. 24 A VRM 8.5-Compliant CPU Supply
REV. 0
–9–
ADP3170
Output Resistance
Selecting a Standard Inductor
Intel’s VRM 8.5 specification requires that the regulator output
voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc
output resistance of:
The companies listed in Table III can provide design consultation and deliver power inductors optimized for high power
applications upon request.
Table III. Power Inductor Manufacturers
ROUT =
Coilcraft
(847) 639-6400
http://www.coilcraft.com
Coiltronics
(561) 752-5000
http://www.coiltronics.com
RT =
The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, IO(MAX), which
equals the peak value less half of the peak-to-peak ripple current.
Solving for RSENSE allowing a 20% margin for overhead and
using the minimum current sense threshold of 69 mV yields:
VCS (TH )( MIN )
69 mV
=
= 2.66 mΩ (5)
I RIPPLE
5.9 A
IO ( MAX ) +
23 A +
2
2
In this case, 2.5 mΩ was chosen, assuming two 5 mΩ, 1 W
resistors in parallel (for power dissipation reasons). Once RSENSE
has been chosen, the output current at the point where current
limit is reached, IOUT(CL), can be calculated using the maximum
current sense threshold of 87 mV:
Intel’s VRM 8.5 specification requires that at no load the output
voltage of the regulator module be offset to a higher value than
the nominal voltage corresponding to the VID code. The offset
is introduced by realizing the total termination resistance of the
gm amplifier with a divider connected between the REF pin and
ground. The resistive divider introduces an offset to the output
of the gm amplifier that, when reflected back through the gain
of the gm stage, accurately positions the output voltage near its
allowed maximum at light load. Furthermore, the output of the
gm amplifier sets the current sense threshold voltage. At no load,
the current sense threshold is increased by the peak of the ripple
current in the inductor and reduced by the delay between sensing when the current threshold has been reached and when the
high side MOSFET actually turns off. These two factors are
combined with the inherent voltage (VGNL0), at the output of the
gm amplifier that commands a current sense threshold of 0 mV:
VGNL = VONL +
(6)
At output voltages below 450 mV, the current sense threshold is reduced to 54 mV, and the ripple current is negligible.
Therefore, the worst-case dead short output current is reduced to:
VCS ( SC ) 54 mV
=
= 21.6 A
RSENSE 2.5 mΩ
2
(11)
The divider resistors (RA for the upper, and RB for the lower)
can now be calculated assuming that the internal resistance of
the gm amplifier (ROGM) is 130 kΩ:
(7)
VREF
VREF – VGNL
– gm × V +
(12)
RT
3V
RB =
= 29.7 kΩ
3 V – 1.224 V
– 2.2 mmho × 45 mV
8.88 kΩ
RB =
To safely carry the current under maximum load conditions, the
sense resistor must have a power rating of at least:
PRSENSE = IO × RSENSE = 23 A2 × 2.5 mΩ = 1.33 W
I L ( RIPPLE ) × ROUT × nI
2
VIN – VOUT
× t D × RSENSE × nI
L
5.9 A × 3.2 mΩ × 25
VGNL = 1V +
–
2
5 V – 1.8 V
× 60 ns × 2.5 mΩ × 25 = 1.224 V
1 µH
IOUT ( CL ) =
IOUT ( SC ) =
(10)
Output Offset
The value of RSENSE is based on the required maximum output
current. The current comparator of the ADP3170 has a minimum
threshold of 69 mV. Note that this minimum value cannot be
used for the maximum specified nominal current, as headroom
is needed for ripple current and transients.
IOUT ( CL )
nI × RSENSE
25 × 2.5 mΩ
=
= 8.88 kΩ
gm × ROUT
2.2 mmho × 3.2 mΩ
where nI is the division ratio from the output voltage signal of the
gm amplifier to the PWM comparator and gm is the transconductance of the gm amplifier itself.
RSENSE
VCS (TH )( MAX ) I L ( RIPPLE )
–
RSENSE
2
87 mV 5.9 A
=
–
= 31.6 A
2.5 mΩ
2
(9)
The required dc output resistance can be achieved by terminating
the gm amplifier with a resistor. The value of the total termination resistance that will yield the correct dc output resistance is:
Sumida Electric Company
(408) 982-9660
http://www.sumida.com
RSENSE =
VONL – VOFL 1.845 V – 1.771V
=
= 3.2 mΩ
∆IO
23 A
(8)
Choosing the nearest 1% resistor value gives RB = 30.1 kΩ.
Finally, RA is calculated:
–10–
REV. 0
ADP3170
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range,
including dc, and equal to the specified dc output resistance.
With the wide-band resistive output impedance the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning
and allows the minimization of the output capacitor.
1
1
RA =
1
1
–
–
RT ROGM RB
1
= 12.83 kΩ
RA =
1
1
1
–
–
8.88 kΩ 1 MΩ 29.7 kΩ
(13)
Choosing the nearest 1% resistor value gives RA = 12.7 kΩ.
COUT Selection
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capacitors. The ESR of the output filter capacitor bank must be equal
to or less than the specified output resistance of the voltage
regulator (3.2 mΩ). The capacitance must be large enough that
the voltage across the capacitor, which is the sum of the resistive
and capacitive voltage drops, does not move below or above the
initial resistive step while the inductor current ramps up or
down to the value corresponding to the new load current. One
can use, for example, eight ZA series capacitors from Rubycon,
which have a maximum ESR of 24 mΩ. These eight 1000 µF
capacitors would give an ESR of 3 mΩ.
As long as the capacitance of the output capacitor is above a
critical value, and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique (ADOPT),
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
IO
(14)
COUT ( CRIT ) =
×L
ROUT × (VOUT + V –)
COUT ( CRIT ) =
23 A
× 1 µH = 4.06 mF
3.2 mΩ × (1.8 V + [–29 mV ])
The equivalent capacitance of the eight ZA series Rubycon
capacitors is 8 × 1 mF = 8 mF. In this case, the total capacitance
is safely above the critical value.
With an ideal current-mode controlled converter, where the
inductor current would respond without delay to the command
signal, the resistive output impedance could be achieved by
having a single-pole roll-off of the voltage gain of the voltageerror amplifier. The pole frequency must coincide with the ESR
zero of the output capacitor.
The ADP3170 uses peak-current control, which is known to
have a nonideal, frequency-dependent command signal-toinductor current transfer function. The frequency dependence
manifests in the form of a pair of complex conjugate poles at
one-half of the switching frequency. A purely resistive output
impedance could be achieved by canceling the complex conjugate with zeros at the same complex frequencies and adding a
third pole equal to the ESR zero of the output capacitor. Such a
compensating network would be quite complicated. Fortunately, in practice, it is sufficient to cancel the pair of complex
conjugate poles with a single real zero placed at one-half of the
switching frequency.
Although the end result is not a perfectly resistive output impedance, the remaining frequency dependence causes only a slight
percentage of deviation from the ideal resistive response. The
single-pole and single-zero compensation can be easily implemented by terminating the gm error amplifier with the parallel
combination of a resistor (RT) and a series RC network. The
value of the terminating resistor RT was determined previously;
the capacitance and resistance of the series RC network are
calculated as follows:
COUT × ESR
RT
8 mF × 3 mΩ
=
= 2.7 nF
8.88 kΩ
COC =
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3170 allows the best possible containment of the peak-to-peak output voltage deviation.
The output current slew rate of any practical switching power
converter is inherently limited by the inductor to a value much
less than the slew rate of the load. Therefore, any sudden change
of load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
larger than the critical value defined by Equation 14, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
COC
(15)
The closest standard value is 2.7 nF. The series resistance is:
2
COC × π × f MIN
2
RZ =
= 1255 Ω
2.7 nF × π × 188 kHz
RZ =
(16)
The nearest standard 5% resistor value is 1.2 kΩ. Note that this
resistor is only required when COUT approaches CCRIT (within
25% or less). In this example, COUT >> CCRIT, and RZ can
therefore be omitted.
REV. 0
–11–
ADP3170
Power MOSFETs
Two external N-channel power MOSFETs must be selected for
use with the ADP3170, one for the main switch and one for the
synchronous switch. The main selection parameters for the power
MOSFETs are the threshold voltage (VGS(TH)), the ON-resistance
(RDS(ON)), and the gate charge (QG). Logic-level MOSFETs are
highly recommended. Only logic-level MOSFETs with VGS ratings
higher than the absolute maximum value of VCC should be used.
The maximum output current IO(MAX) determines the RDS(ON)
requirement for the two power MOSFETs. When the ADP3170
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. For VIN = 5 V and VOUT = 1.8 V, the
maximum duty ratio of the high-side FET is:
DHSF ( MAX ) = 1 – ( f MIN × tOFF )
(17)
DHSF ( MAX ) = 1 – (183 kHz × 3.3 µs ) = 40%
The maximum duty ratio of the low-side (synchronous rectifier)
MOSFET is:
DLSF ( MAX ) = 1 – DHSF ( MAX ) = 60%
(18)
The maximum rms current of the high-side MOSFET is:
(
2
)
2
PHSF = RDS (ON )HSF × I HSF ( MAX ) +
PHSF
2
I LSF (MAX ) = D LSF (MAX ) ×
5 V × 100 nC × 183 kHz = 2.04 W
where the second term represents the turn-off loss of the
MOSFET and the third term represents the turn-on loss due to
the stored charge in the body diode of the low-side MOSFET.
In the second term, QG is the gate charge to be removed from
the gate for turnoff and IG is the gate turn-off current. From the
data sheet, the value of QG for the FDB7045L is 50 nC and the
peak gate drive current provided by the ADP3170 is about 1 A. In
the third term, QRR is the charge stored in the body diode of
the low-side MOSFET at the valley of the inductor current.
The data sheet of the FDB7045L does not give that information, so an estimated value of 100 nC is used. The estimate is
based on information found on the data sheets of similar devices.
2
PLSF = RDS (ON )HSF × I HSF ( MAX )
(19)
(
)
I L (VALLEY ) + I L (VALLEY ) × I L (PEAK ) + I L (PEAK )
Note that there are no switching losses in the low-side MOSFET.
2
3
(
)
17.4 A 2 + 17.4 A × 28.6 A + 28.6 A 2
3
= 18 A
(20)
Surface mount MOSFETs are preferred in CPU core converter
applications due to their ability to be handled by automatic
assembly equipment. The TO-263 package offers the power
handling of a TO-220 in a surface mount package. However,
this package still needs adequate copper area on the PCB to
help move the heat away from the package.
The junction temperature for a given area of two-ounce copper
can be approximated using:
TJ = (θ JA × PD ) + TA
PD ( FETs ) = 0.1 × VOUT × IOUT ( MAX )
PD ( FETs ) = 0.1 × 1.8 V × 23 A = 4.1 W
(21)
Allocating half of the total dissipation for the high-side MOSFET and
half for the low-side MOSFET, and assuming that the resistive loss of the high-side MOSFET is one-third, and the switching
loss is two-thirds of its portion, the required maximum MOSFET
resistances will be:
PD ( FETS )
3×I
RDS (ON )LS =
2
HSF ( MAX )
PD ( FETS )
2
I LSF ( MAX )
=
JA = 45°C/W for 0.5 in2
JA = 36°C/W for 1 in2
JA = 28°C/W for 2 in2
For 1 in 2 of copper area attached to each transistor and an
ambient temperature of 50°C:
Note that there is a trade-off between converter efficiency and
cost. Larger MOSFETs reduce the conduction losses and allow
(
)
= (28 C / W × 1.94W ) + 50 C = 104 C
T JHSF = 28o C / W × 2.06W + 50o C = 108o C
T JLSF
(23)
(26)
assuming:
4.1 W
= 6 mΩ (22)
3 × 14.7 A2
4.1W
=
= 6 mΩ
2 × 18 A2
(25)
PLSF = 6 mΩ × 18 A2 = 1.94 W
The RDS(ON) for each MOSFET can be derived from the
allowable dissipation. If 10% of the maximum output power is
allowed for MOSFET dissipation, the total dissipation will be:
RDS (ON )HSF =
(24)
5 × 28.6 A × 50 nC × 183 kHz
= 6 mΩ × 14.7 A2 +
+
2 ×1A
2
The maximum rms current of the low-side MOSFET is:
I HSF (MAX ) = 0.6 ×
VIN × I L ( PEAK ) × QG × f MIN
+
2 × IG
VIN × QRR × f MIN
17.4 A + (17.4 A × 28.6 A) + 28.6 A
= 14.7 A
3
2
I HSF ( MAX ) = 0.4 ×
With this choice, the high-side MOSFET dissipation is:
The low-side MOSFET dissipation is:
2
I L (VALLEY ) + I L (VALLEY ) × I L ( PEAK ) + vI L ( PEAK )
3
I HSF ( MAX ) = DHSF ( MAX ) ×
higher efficiency, but increase the system cost. A Fairchild
FDB7045L (RDS(ON) = 4.5 mΩ nominal, 6 mΩ worst-case) is a
good choice for both the low-side and high-side MOSFET.
o
o
o
All of the above-calculated junction temperatures are safely
below the 175°C maximum specified junction temperature of
the selected MOSFETs.
–12–
REV. 0
ADP3170
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output is given by:
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is a square wave with a duty ratio of VOUT/
VlN and an amplitude of one-half of the maximum output
current. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum rms current must be used.
The maximum rms capacitor current is given by:
I C ( RMS ) = IO DHSF – DHSF
PLDO = (VIN – VOUT ) × IOUT
2
I C ( RMS ) = 23 A × 0.4 – 0.42 = 11.3 A
(27)
For a ZA-type capacitor with 1000 µF capacitance and 6.3 V
voltage rating, the ESR is 24 mΩ and the maximum allowable
ripple current at 100 kHz is 2 A. At 105°C, at least six such
capacitors must be connected in parallel to handle the calculated ripple current. At 50°C ambient, however, a higher
ripple current can be tolerated, so five capacitors in parallel
are adequate.
(30)
Minimum power dissipation and maximum efficiency are
accomplished by choosing the lowest available input voltage
that exceeds the desired output voltage. However, if the chosen
input source is itself generated by a linear regulator, its power
dissipation will be increased in proportion to the additional
current it must now provide.
3.3V
1F
ADP3170
VLR
1.8V, 2.2A
RS
250m
LRDRV
1k
68pF
LRFB
10k
100F
1.8V
The ripple voltage across the five paralleled capacitors is:
ESRC
DHSF ( MAX )
VC ( RIPPLE ) = IO ×
+
nC × CIN × f MIN
nC
Figure 4. Adding Overcurrent Protection to the Linear
Regulator
(28)
24 mΩ
0.4
VC ( RIPPLE ) = 23 A ×
×
= 120 mV
5 × 1 mF × 183 kHz
5
Implementing Current Limit for the Linear Regulators
The circuit of Figure 4 gives an example of a current limit protection circuit that can be used in conjunction with the linear
regulator. The output voltage is internally set by the LRFB pin.
The value of the current sense resistor may be calculated as
follows:
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ms, an additional
small inductor (L > 1 µH @ 10 A) should be inserted between
the converter and the supply bus.
Linear Regulators
The linear regulator provides a low cost, convenient and versatile solution for generating a 1.8 V supply rail. The maximum
output load current is determined by the size and thermal
impedance of the external N-channel power MOSFET that is
placed in series with the supply and controlled by the ADP3170.
The output voltage is sensed at the LRFB pin and compared to
an internal reference voltage in a negative feedback loop which
keeps the output voltage in regulation. If the load is reduced or
increased, the MOSFET drive will also be reduced or increased
by the ADP3170 to provide a well regulated output voltage.
Output voltages higher than the fixed internal reference voltage
can be programmed by adding an external resistor divider.
The efficiency and corresponding power dissipation of each
of the linear regulators are not determined by the ADP3170.
Rather, these are a function of input and output voltage and
load current. Efficiency is approximated by the formula:
REV. 0
VOUT
VIN
540m V 540m V
=
= 250 mΩ
IO ( MAX )
2.2 A
(31)
The power rating of the current sense resistor must be at least:
2
PD ( RS ) = RS × IO ( MAX ) = 1.2 W
(32)
The maximum linear regulator MOSFET junction temperature with
a shorted output is:
(
TJ( MAX ) = TA + θ JC × VIN × IO( MAX )
(
)
)
TJ( MAX ) = 50o C + 1.4o C / W × 3.3 V × 2.2 A = 60o C
(33)
which is within the maximum allowed by the MOSFET’s data
sheet specification. The maximum MOSFET junction temperature at nominal output is:
Efficiency of the Linear Regulators
η = 100% ×
RS ≅
(
[
]
TJ( NOM ) = 50o C + θ JC × VIN – VOUT × IO( NOM )
(29)
(
[
]
)
)
(34)
TJ( NOM ) = 50o C + 1.4o C / W × 3.3 V – 1.8 V × 2 A = 54o C
This example assumes an infinite heat sink. The practical limitation will be based on the actual heat sink used.
–13–
ADP3170
upper MOSFET. In the absence of an effective Schottky
diode, this dissipation occurs through the following sequence
of switching events. The lower MOSFET turns off in
advance of the upper MOSFET turning on (necessary to
prevent cross-conduction). The circulating current in the
power converter, no longer finding a path for current
through the channel of the lower MOSFET, draws current
through the inherent body-drain diode of the MOSFET.
The upper MOSFET turns on, and the reverse recovery
characteristic of the lower MOSFET’s body-drain diode
prevents the drain voltage from being pulled high quickly.
The upper MOSFET then conducts very large current
while it momentarily has a high voltage forced across it,
which translates into added power dissipation in the upper
MOSFET. The Schottky diode minimizes this problem
by carrying a majority of the circulating current when the
lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal performance of a switching regulator in a PC system:
General Recommendations
1.
For best results, a four-layer PCB is recommended. This
should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths.
2.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and inductance introduced by these current paths is minimized and
the via current rating is not exceeded.
3.
If critical signal lines (including the voltage and current
sense lines of the ADP3170) must cross through power circuitry, it is best if a ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the signals
at the expense of making signal ground a bit noisier.
4.
The GND pin of the ADP3170 should connect first to a
ceramic bypass capacitor (on the VCC pin) and then into the
analog ground plane. The analog ground plane should be
located below the ADP3170 and the surrounding smallsignal components, such as, the timing capacitor and
compensation network. The analog ground plane should
connect to power ground plane at a single point; the best
location being the negative terminal of the last output
capacitor.
9.
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is
a current path); and improved thermal performance—
especially if the vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
10. The output power path, though not as critical as the switching power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors.
5.
The output capacitors should also be connected as closely as
possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed,
the capacitors too should be distributed, and generally in
proportion to where the load tends to be more dynamic. It is
advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
11. For best EMI containment, the ground plane should extend
fully under all the power components. These are: the input
capacitors, the power MOSFETs and Schottky diode, the
inductor, the current sense resistor, any snubbing elements
that might be added to dampen ringing and the output
capacitors.
6.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
12. The output voltage is sensed and regulated between the
GND pin (which connects to the signal ground plane) and
the CS– pin. The output current is sensed (as a voltage)
and regulated between the CS– pin and the CS+ pin. In
order to avoid differential mode noise pickup in those
sensed signals, their loop areas should be small. Thus the
CS– trace should be routed atop the signal ground plane,
and the CS+ and CS– traces should be routed as a closely
coupled pair (CS+ should be over the signal ground plane
as well).
Power Circuitry
7. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system, as well as, noise-related operational
problems in the power converter control circuitry. The
switching power path is the loop formed by the current
path through the input capacitors, the two FETs and the
power Schottky diode, if used, including all interconnecting PCB traces and planes. The use of short and wide
interconnection traces is especially critical in this path for
two reasons: it minimizes the inductance in the switching
loop, which can cause high-energy ringing; and it accommodates the high current demand with minimal voltage loss.
8.
A power Schottky diode (1 ~ 2 A dc rating) placed from
the lower MOSFET’s source (anode) to drain (cathode)
will help to minimize switching power dissipation in the
Signal Circuitry
13. The CS+ and CS– traces should be Kelvin connected to
the current sense resistor so that the additional voltage drop
due to current flow on the PCB at the current sense resistor
connections does not affect the sensed voltage. It is desirable
to have the ADP3170 close to the output capacitor bank
and not in the output power path, so that any voltage drop
between the output capacitors and the GND pin is minimized, and voltage regulation is not compromised.
–14–
REV. 0
ADP3170
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead TSSOP
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
10
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–15–
8
0
0.028 (0.70)
0.020 (0.50)
–16–
PRINTED IN U.S.A.
C02620–1.5–7/01(0)
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