ADP3193A

8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller ADP3193A FEATURES Selectable 2- or 3-phase operation at up to 1 MHz per phase ±7.7 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Fast enhanced PWM (FEPWM) flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay FUNCTIONAL BLOCK DIAGRAM VCC 23 RT RAMPADJ 9 10 SHUNT REGULATOR UVLO SHUTDOWN GND 14 850mV EN 1 OSCILLATOR + – 15 OD PWM1 PWM2 PWM3 CMP – + DAC +150mV + CSREF DAC –350mV – + CURRENT BALANCING CIRCUIT SET EN RESET 22 21 CMP – + RESET 2-/3-PHASE DRIVER LOGIC 20 CMP – + RESET CURRENT LIMIT 19 18 17 PWRGD 2 DELAY APPLICATIONS Desktop PC power supplies for Next generation Intel® processors VRM modules ILIMIT 8 DELAY 7 IREF 16 COMP 5 4 FBRTN 3 VIDSEL 32 24 25 26 VC DAC 27 28 29 30 31 06652-001 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 1. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3193A also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193A also provides accurate and reliable short-circuit protection, adjustable current limiting, and delayed power-good output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3193A has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3193A is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 32-lead LFCSP. 1 Protected by U.S. Patent Number 6,683,441; other patents pending. ©2008 SCILLC. All rights reserved. February 2008 – Rev. 1 + The ADP3193A1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.5 V and 1.6 V. PRECISION REFERENCE – GENERAL DESCRIPTION + – – CROWBAR SW1 SW2 SW3 CSCOMP CSREF CSSUM 13 CURRENT MEASUREMENT AND LIMIT + – 11 12 FB BOOT VOLTAGE AND SOFT START CONTROL 6 SS ADP3193A Publication Order Number: ADP3193A/D ADP3193A TABLE OF CONTENTS Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram...............................................................1 Revision History................................................................................2 Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................5 ESD Caution ..................................................................................5 Pin Configuration and Function Descriptions .............................6 Typical Performance Characteristics..............................................7 Test Circuits .......................................................................................8 Theory of Operation.........................................................................9 Start-Up Sequence ........................................................................9 Phase Detection Sequence ...........................................................9 Master Clock Frequency ............................................................10 Output Voltage Differential Sensing ........................................10 Output Current Sensing .............................................................10 Current Control Mode and Thermal Balance.........................10 Voltage Control Mode ................................................................10 Current Reference .......................................................................11 Fast Enhanced PWM Mode.......................................................11 Delay Timer .................................................................................11 Soft Start .......................................................................................11 Current-Limit, Short-Circuit, and Latch-Off Protection ......11 Dynamic VID ..............................................................................12 Power-Good Monitoring ...........................................................12 Output Crowbar..........................................................................12 Output Enable and UVLO.........................................................13 Application Information ................................................................18 Setting the Clock Frequency .....................................................18 Soft Start Delay Time .................................................................18 Current-Limit Latch-Off Delay Times.....................................18 Inductor Selection.......................................................................18 Current Sense Amplifier ............................................................19 Inductor DCR Temperature Correction..................................20 Output Offset...............................................................................20 COUT Selection..............................................................................21 Power MOSFETs .........................................................................22 Ramp Resistor Selection ............................................................23 COMP Pin Ramp ........................................................................23 Current-Limit Setpoint ..............................................................23 Feedback Loop Compensation Design ....................................24 CIN Selection and Input Current di/dt Reduction ..................25 Shunt Resistor Design ................................................................25 Tuning Procedure for ADP3193A ............................................26 Layout and Component Placement..........................................27 Outline Dimensions........................................................................29 Ordering Guide ...........................................................................29 REVISION HISTORY 02/08—Rev 1: Conversion to ON Semiconductor 05/07—Revision 0: Initial Version Rev. 1 | Page 2 of 29 | www.onsemi.com ADP3193A SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Symbol VIREF IIREF VCOMP VFB VFB(BOOT) Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate Boot Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation IFB IFBRTN ICOMP GBW(ERR) tBOOT VIL(VID) VIH(VID) IIN(VID) Conditions Min Typ 1.5 15 Max Unit V μA V mV V LSB μA μA μA MHz V/μs ms V V μA ns μs MHz kHz kHz kHz V mV μA mV nA MHz V/μs V V μA ms mV kΩ μA % RIREF = 100 kΩ 14.25 0 −7.7 1.092 −1 13.5 15.75 4.4 +7.7 Relative to nominal DAC output, referenced to FBRTN (see Figure 4) In startup IFB = IIREF FB forced to VOUT − 3% COMP = FB COMP = FB CDELAY = 10 nF VID(x), VIDSEL VID(x), VIDSEL VID code change to FB change VID code change to PWM going low 1.1 15 65 500 20 25 2 1.108 +1 16.5 200 0.4 0.8 −1 400 5 0.25 240 4 293 fOSC fPHASE Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) TA = 25°C, RT = 210 kΩ, 3-phase TA = 25°C, RT = 100 kΩ, 3-phase TA = 25°C, RT = 40 kΩ, 3-phase RT = 243 kΩ to GND RAMPADJ − FB 1.9 −50 1 −1.0 −10 260 530 1000 2.0 2.1 +50 50 +1.0 +10 CSSUM − CSREF (see Figure 4) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 10 10 0 0.05 500 8 −600 10 8 −4 +200 26 20 +4 3.5 3.5 ICSCOMP tOC(DELAY) VSW(x)CM RSW(x) ISW(x) ΔISW(x) CDELAY = 10 nF SW(x) = 0 V SW(x) = 0 V SW(x) = 0 V 17 12 Rev. 1 | Page 3 of 29 | www.onsemi.com ADP3193A Parameter CURRENT LIMIT COMPARATOR ILIMIT Bias Current ILIMIT Voltage Maximum Output Voltage Current-Limit Threshold Voltage Current-Limit Setting Ratio DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage POWER-GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY VCC2 DC Supply Current UVLO Turn-On Current UVLO Threshold Voltage UVLO Turn-Off Voltage 1 2 Symbol IILIMIT VILIMIT VCL Conditions IILIMIT = 2/3 × IIREF RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT)) VCSREF − VCSCOMP, RILIMIT = 121 kΩ VCL/VILIMIT IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF Min 9 1.09 3 80 Typ 10 1.21 100 82.6 15 3.75 1.7 15 850 100 −1 2 160 Max 11 1.33 125 Unit μA V V mV mV/V μA μA V μA mV mV μA ms mV V IDELAY IDELAY(CL) VDELAY(TH) ISS VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) 12 3.0 1.6 12 800 80 18 4.5 1.8 18 900 125 During startup, ISS = IIREF EN > 950 mV, CDELAY = 10 nF 500 4 Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = −4 mA CDELAY = 10 nF 100 −400 100 5 −350 150 150 2 250 200 150 375 250 400 160 5 5 6.5 500 −300 200 300 mV mV mV ms μs ns mV mV μs ns mV V V mA mA V V VCROWBAR tCROWBAR Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low 100 320 100 200 430 VOL(PWM) VOH(PWM) VCC IVCC VUVLO IPWM(SINK) = −400 μA IPWM(SOURCE) = 400 μA VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 4) VSYSTEM = 13.2 V, RSHUNT = 340 Ω VCC rising VCC falling 4.0 4.65 5.55 25 11 9 4.1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production. Rev. 1 | Page 4 of 29 | www.onsemi.com ADP3193A ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM1 to PWM3, RAMPADJ SW1 to SW3