ADP3196

6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3196 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay FUNCTIONAL BLOCK DIAGRAM VCC 31 SHUNT REGULATOR OSCILLATOR SET RESET EN 30 PWM1 19 OD RT 12 RAMPADJ 13 UVLO SHUTDOWN GND 18 + CMP – 800mV – + – + + DAC – 250mV – CURRENT BALANCING CIRCUIT + CMP – + CMP – RESET 29 PWM2 EN 1 1.8V CSREF RESET 2-/3-/4-PHASE DRIVER LOGIC 28 PWM3 + CMP – 27 PWM4 RESET CURRENT LIMIT PWRGD 2 DELAY CROWBAR 25 SW1 TTSENSE 10 24 SW2 THERMAL THROTTLING CONTROL 23 SW3 22 SW4 APPLICATIONS Desktop PC power supplies for next generation AMD processors VRM modules VRMHOT VRM_OFF 9 8 17 CSCOMP ILIMIT 11 DELAY 7 CURRENT MEASUREMENT AND LIMIT + – 15 CSREF 16 CSSUM 21 IMON IREF 20 COMP 5 PRECISION REFERENCE FBRTN 3 SOFT START CONTROL 6 SS – + + – 14 LLSET 4 FB GENERAL DESCRIPTION The ADP3196 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Advanced Micro Devices, Inc. (AMD) processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3196 supports a programmable slope function to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. This can be disabled by connecting Pin LLSET to Pin CSREF. 1 1 VID DAC 34 35 36 VID3 37 VID2 38 VID1 39 VID0 ADP3196 VID5 VID4 Figure 1. Functional Block Diagram The ADP3196 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3196 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3196 is specified over the extended commercial temperature range of 0°C to +85°C and is available in a 40-lead LFCSP. Protected by U.S. Patent Number 6,683,441; others patents pending. ©2008 SCILLC. All rights reserved. January 2008 – Rev. 1 Publication Order Number: ADP3196/D 06371-001 ADP3196 TABLE OF CONTENTS Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram...............................................................1 Table of Contents...............................................................................2 Revision History................................................................................2 Specifications .....................................................................................3 Test Circuits .......................................................................................5 Absolute Maximum Ratings ............................................................6 ESD Caution ..................................................................................6 Pin Configuration and Function Description...............................7 Typical Performance Characteristics..............................................9 Theory of Operation.......................................................................10 Start-Up Sequence ......................................................................10 Phase Detection Sequence .........................................................10 Master Clock Frequency ............................................................11 Output Voltage Differential Sensing ........................................11 Output Current Sensing.............................................................11 Active Impedance Control Mode .............................................11 Current Control Mode and Thermal Balance.........................11 Voltage Control Mode ................................................................12 Current Reference.......................................................................12 Enhanced PWM Mode...............................................................12 Delay Timer .................................................................................12 Soft Start.......................................................................................12 Current Limit, Short-Circuit, and Latch-Off Protection.......13 Dynamic VID ..............................................................................14 Power-Good Monitoring ...........................................................14 Output Crowbar..........................................................................14 Output Enable and UVLO.........................................................14 Thermal Monitoring...................................................................14 Layout and Component Placement..........................................17 Outline Dimensions........................................................................18 Ordering Guide ...........................................................................18 REVISION HISTORY 01/08 - Rev 1: Conversion to ON Semiconductor 10/06—Revision 0: Initial Version Rev. 1 | Page 2 of 18 | www.onsemi.com ADP3196 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Symbol VIREF IIREF VCOMP VFB Conditions Min Typ 1.5 15 Max Unit V μA V mV mV LSB μA μA μA MHz V/μs mV nA V V μA ns 4 220 MHz kHz kHz kHz V mV μA mV nA MHz V/μs V V μA ms +6 +200 26 20 +4 11 1.33 125 % mV kΩ μA % μA V V mV mV/V RIREF = 100 kΩ 14.25 0.05 −10 −78 −1 −9 15.75 4.4 10 Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) CSREF – LLSET = 80 mV IFB = 0.5 × IIREF FB forced to VOUT – 3% COMP = FB COMP = FB Relative to CSREF −80 −7.5 65 500 20 25 IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET VIL(VID) VIH(VID) IIN(VID) −82 +1 −6 200 −250 −10 +250 +10 0.6 VID(X), VIDSEL VID(X), VIDSEL VID code change to FB change 1.4 −10 400 0.25 180 fOSC fPHASE TA = 25°C, RT = 205 kΩ, 4 phase TA = 25°C, RT = 118 kΩ, 4 phase TA = 25°C, RT = 55 kΩ, 4 phase RT = 243 kΩ to GND RAMPADJ – FB, DAC = 1.55 V Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current ILIMIT Voltage Maximum Output Voltage Current Limit Threshold Voltage Current Limit Setting Ratio VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) 1.9 −50 1 −1.0 −10 200 400 800 2.0 2.1 +50 50 +1.0 +10 CSSUM – CSREF (see Figure 3) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 10 10 0 0.05 500 8 −6 −600 10 8 −4 9 1.09 3 80 3.5 3.5 ICSCOMP tOC(DELAY) IMON VSW(X)CM RSW(X) ISW(X) ΔISW(X) IILIMIT VILIMIT VCL CDELAY = 10 nF 10 × (CSREF – CSCOMP) > 50mV SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V IILIMIT = 2/3 × IIREF RILIMIT = 121kΩ (VILIMIT = IILIMIT × RILIMIT) VCSREF – VCSCOMP, RILIMIT = 121 kΩ VCL/IILIMIT Rev. 1 | Page 3 of 18 | www.onsemi.com 17 12 10 1.21 100 82.6 ADP3196 Parameter DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current (Startup) Output Current (DAC Code Change) ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage OD Pull-Down Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRM_OFF Threshold Voltage TTSENSE VRMHOT Threshold Voltage TTSENSE Hysteresis VRM_OFF Output Low Voltage VRMHOT Output Low Voltage POWER-GOOD COMPARATOR Overvoltage Threshold Undervoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage POWER SUPPLY VCC DC Supply Current UVLO Turn On Current UVLO Threshold Voltage UVLO Threshold Voltage 1 Symbol IDELAY IDELAY(CL) VDELAY(TH) ISS(STARTUP) ISS(DAC) Conditions IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF Min 12 3.0 1.6 3 15 Typ 15 3.75 1.7 3.75 18.75 Max 18 4.5 1.8 4.5 22.5 Unit μA μA V μA μA During startup, ISS(STARTUP) = 0.25 × IIREF DAC code change, ISS(DAC) = 1.25 × IIREF VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD) EN > 950 mV, CDELAY = 10 nF 750 80 800 100 −1 2 160 850 125 mV mV μA ms 500 mV V kΩ 4 5 60 Internally limited 0 −135 1.06 765 −123 1.105 810 50 150 150 5 −111 1.15 855 V μA V mV mV mV mV mV mV mV mV mV ms μs ns V μs ns VOL(VRFAN) VOL(VRHOT) VPWRGD(OV) VPWRGD(UV) VOL(PWRGD) I VRFAN (SINK) = −4 mA I VRHOT (SINK) = −4 mA Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V IPWRGD(SINK) = −4 mA CDELAY = 10 nF 100 200 190 −300 −310 300 300 300 310 −200 −190 300 250 250 −250 −250 150 2 250 200 1.8 250 400 160 5 5 6.5 VCROWBAR tCROWBAR Relative to FBRTN Overvoltage to PWM going low 1.75 100 1.85 VOL(PWM) VOH(PWM) VCC IVCC VUVLO VUVLO IPWM(SINK) = −400 μA IPWM(SOURCE) = 400 μA VSYSTEM = 12 V, RSHUNT = 340Ω (see Figure 2) 500 4.0 4.65 mV V V mA mA V 5.55 25 11 VCC rising VCC falling 9 4.1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production. Rev. 1 | Page 4 of 18 | www.onsemi.com ADP3196 TEST CIRCUITS 12V 6-BIT CODE + 40 NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC 1μF 680Ω 100nF 680Ω 12V ADP3196 680 Ω 31 1.25V 1 680Ω 1kΩ 10nF 10nF ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE ADP3196 PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON VCC FB 4 10kΩ 3 FBRTN LLSET 14 – ΔV 15 100kΩ 250kΩ CSREF + GND 18 1V 20kΩ VID DAC 100nF NC = NO CONNECT. 06371-002 ΔVFB = FBΔV = 80mV – FBΔV = 0mV Figure 2. Closed-Loop Output Voltage Accuracy Figure 4. Positioning Voltage 12V ADP3196 680Ω 680Ω 31 VCC CSCOMP 17 39kΩ 100nF 16 CSSUM 1kΩ 15 CSREF CSCOMP – 1V 40 1V 18 Figure 3. Current Sense Amplifier VOS Rev. 1 | Page 5 of 18 | www.onsemi.com 06371-003 GND VOS = 06371-004 ADP3196 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM3 – PWM4, RAMPADJ SW1 – SW4