ADP3198

8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3198 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±11 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay FUNCTIONAL BLOCK DIAGRAM VCC 31 RT RAMPADJ 12 13 SHUNT REGULATOR UVLO SHUTDOWN GND 18 850mV EN 1 OSCILLATOR + – 19 OD PWM1 PWM2 CMP – + DAC + 150mV + CSREF DAC – 500mV – + CURRENT BALANCING CIRCUIT SET EN RESET RESET 30 CMP – + 29 CMP – + CMP – + 28 PWM3 RESET 2/3/4-PHASE DRIVER LOGIC 27 PWM4 RESET PWRGD 2 DELAY TTSENSE 10 VRHOT 9 VRFAN 8 THERMAL THROTTLING CONTROL APPLICATIONS Desktop PC power supplies for next generation Intel® processors VRM modules ILIMIT 11 DELAY 7 IREF 20 COMP 5 4 GENERAL DESCRIPTION The ADP31981 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.5 V and 1.6 V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3198 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3198 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. 1 FBRTN 3 VIDSEL 40 32 33 34 VID DAC 35 36 37 38 39 06094-001 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 1. The ADP3198 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3198 is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 40-lead LFCSP. Protected by U.S. Patent Number 6,683,441; other patents pending. ©2008 SCILLC. All rights reserved. January 2008 – Rev. 2 – PRECISION REFERENCE + + – – CROWBAR CURRENT LIMIT 25 24 23 22 17 SW1 SW2 SW3 SW4 CSCOMP CSREF CSSUM IMON FB LLSET CURRENT MEASUREMENT AND LIMIT + – 15 16 21 14 BOOT VOLTAGE AND SOFT START CONTROL 6 SS ADP3198 Publication Order Number: ADP3198/D ADP3198 TABLE OF CONTENTS Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram...............................................................1 Revision History................................................................................2 Specifications .....................................................................................3 Test Circuits .......................................................................................5 Absolute Maximum Ratings ............................................................6 ESD Caution ..................................................................................6 Pin Configuration and Function Descriptions .............................7 Typical Performance Characteristics..............................................9 Theory of Operation.......................................................................10 Start-Up Sequence ......................................................................10 Phase Detection Sequence .........................................................10 Master Clock Frequency ............................................................11 Output Voltage Differential Sensing ........................................11 Output Current Sensing .............................................................11 Active Impedance Control Mode .............................................11 Current Control Mode and Thermal Balance.........................11 Voltage Control Mode ................................................................12 Current Reference .......................................................................12 Enhanced PWM Mode...............................................................12 Delay Timer .................................................................................12 Soft Start .......................................................................................12 Current-Limit, Short-Circuit, and Latch-Off Protection ......13 Dynamic VID ..............................................................................13 Power-Good Monitoring ...........................................................13 Output Crowbar..........................................................................14 Output Enable and UVLO.........................................................14 Thermal Monitoring...................................................................14 Application Information ................................................................19 Setting the Clock Frequency .....................................................19 Soft Start Delay Time .................................................................19 Current-Limit Latch-Off Delay Times.....................................19 Inductor Selection.......................................................................19 Current Sense Amplifier ............................................................20 Inductor DCR Temperature Correction..................................21 Output Offset...............................................................................22 COUT Selection..............................................................................22 Power MOSFETs .........................................................................24 Ramp Resistor Selection ............................................................25 COMP Pin Ramp ........................................................................25 Current-Limit Setpoint ..............................................................25 Feedback Loop Compensation Design ....................................25 CIN Selection and Input Current di/dt Reduction ..................27 Thermal Monitor Design...........................................................27 Shunt Resistor Design ................................................................28 Tuning the ADP3198..................................................................28 Layout and Component Placement..........................................29 Outline Dimensions........................................................................31 Ordering Guide ...........................................................................31 REVISION HISTORY 01/08 - Rev 2: Conversion to ON Semiconductor 8/06—Rev. 0 to Rev. A. 6/06—Revision 0: Initial Version Rev. 2 | Page 2 of 31 | www.onsemi.com ADP3198 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Symbol VIREF IIREF VCOMP VFB VFB(BOOT) Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current BOOT Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Conditions Min Typ 1.5 15 Max Unit V μA V mV V mV LSB μA μA μA MHz V/μs mV nA ms V V μA ns μs MHz kHz kHz kHz V mV μA mV nA MHz V/μs V V μA ms % mV kΩ μA % μA RIREF = 100 kΩ 14.25 0 −11 1.089 −78 −1 13.5 15.75 4.4 +11 Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) In startup CSREF − LLSET = 80 mV IFB = IIREF FB forced to VOUT – 3% COMP = FB COMP = FB Relative to CSREF CDELAY = 10 nF VID(X), VIDSEL VID(X), VIDSEL VID code change to FB change VID code change to PWM going low 1.1 −80 15 65 500 20 25 IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET tBOOT VIL(VID) VIH(VID) IIN(VID) 1.111 −82 +1 16.5 200 −350 −10 2 +350 +10 0.4 0.8 −1 400 5 0.25 156 4 240 fOSC fPHASE Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) TA = 25°C, RT = 243 kΩ, 4-phase TA = 25°C, RT = 113 kΩ, 4-phase TA = 25°C, RT = 51 kΩ, 4-phase RT = 243 kΩ to GND RAMPADJ − FB 1.9 −50 1 −2 −10 200 400 800 2.0 2.1 +50 50 +2 +10 CSSUM − CSREF (see Figure 3) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 10 10 0 0.05 500 8 −6 −600 10 8 −5 9 +6 +200 26 20 +5 11 3.5 3.5 ICSCOMP tOC(DELAY) IMON VSW(X)CM RSW(X) ISW(X) ΔISW(X) IILIMIT CDELAY = 10 nF 10 × (CSREF − CSCOMP) > 50 mV SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V IILIMIT = 2/3 × IIREF 17 12 10 Rev. 2 | Page 3 of 31 | www.onsemi.com ADP3198 Parameter ILIMIT Voltage Maximum Output Voltage Current-Limit Threshold Voltage Current-Limit Setting Ratio DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage OD Pull Down Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRFAN Threshold Voltage TTSENSE VRHOT Threshold Voltage TTSENSE Hysteresis VRFAN Output Low Voltage VRHOT Output Low Voltage POWER-GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY VCC2 DC Supply Current UVLO Turn-On Current UVLO Threshold Voltage UVLO Turn-Off Voltage 1 Symbol VILIMIT VCL Conditions RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT)) VCSREF − VCSCOMP, RILIMIT = 121 kΩ VCL/VILIMIT IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF Min 1.09 3 80 Typ 1.21 100 82.6 15 3.75 1.7 15 850 100 −1 2 160 Max 1.33 125 Unit V V mV mV/V μA μA V μA mV mV μA ms mV V kΩ IDELAY IDELAY(CL) VDELAY(TH) ISS VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD) 12 3.0 1.6 12 800 80 18 4.5 1.8 18 900 125 During startup, ISS = IIREF EN > 950 mV, CDELAY = 10 nF 500 4 5 60 Internally limited 0 −133 1.06 765 VOL(VRFAN) VOL(VRHOT) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) IVRFAN(SINK) = −4 mA IVRHOT(SINK) = −4 mA Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = −4 mA CDELAY = 10 nF 100 −450 250 −123 1.105 810 50 150 150 −500 300 150 2 250 200 300 450 250 400 160 5 5 6.5 5 −113 1.15 855 300 300 −550 350 300 V μA V mV mV mV mV mV mV mV ms μs ns mV mV μs ns VCROWBAR tCROWBAR Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low 250 395 100 350 505 VOL(PWM) VOH(PWM) VCC IVCC VUVLO IPWM(SINK) = −400 μA IPWM(SOURCE) = 400 μA VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 2) VSYSTEM = 13.2 V, RSHUNT = 340 Ω VCC rising VCC falling 500 4.0 4.65 mV V V mA mA V V 5.55 25 11 9 4.1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production. Rev. 2 | Page 4 of 31 | www.onsemi.com ADP3198 TEST CIRCUITS 12V 12V ADP3198 680Ω 31 8-BIT CODE + 40 1μF 680 Ω 100nF 680Ω 680Ω VCC COMP 4 VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC 1.25V 1 10kΩ 3 1kΩ 10nF 10nF ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF EN PWRGD FBRTN FB COMP SS DELAY VRFAN VRHOT TTSENSE ADP3198 PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 NC FB LLSET 14 – ΔV 15 CSREF + GND 18 VID DAC 1V 100kΩ 250kΩ 20kΩ 06094-002 ΔVFB = FBΔV = 80mV – FBΔV = 0mV NC = NO CONNECT 100nF Figure 4. Positioning Voltage Figure 2. Closed-Loop Output Voltage Accuracy 12V ADP3198 680 Ω 680Ω 31 VCC CSCOMP 17 39kΩ 100nF 16 CSSUM 1kΩ 15 CSREF 1V 18 Figure 3. Current Sense Amplifier VOS Rev. 2 | Page 5 of 31 | www.onsemi.com 06094-003 GND VOS = CSCOMP – 1V 40 06094-004 ADP3198 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM3 to PWM4, RAMPADJ SW1 to SW4 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source. 1 CH1 50mV M 10μs A CH1 –36mV 06094-012 THERMAL MONITOR DESIGN A thermistor is used on the TTSENSE input of the ADP3198 for monitoring the temperature of the VR. A constant current of 123 μA is sourced out of this pin and runs through a thermistor network such as the one shown in Figure 15. ADP3198 Figure 13. Typical Transient Response for Design Example Load Step 1 8 VRFAN OPTIONAL TEMPERATURE ADJUST RESISTOR 9 VRHOT 10 TTSENSE 06094-013 CH1 50mV M 10μs A CH1 –36mV RTTSENSE Figure 14. Typical Transient Response for Design Example Load Release Figure 15. VR Thermal Monitor Circuit CIN SELECTION AND INPUT CURRENT di/dt REDUCTION In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by A voltage is generated from this current through the thermistor and sensed inside the IC. When the voltage reaches 1.105 V, the VRFAN output gets set. When the voltage reaches 0.81 V, the VRHOT gets set. This corresponds to RTTSENSE values of 8.98 kΩ for VRFAN and 6.58 kΩ for VRHOT. These values correspond to a thermistor temperature of ~100°C and ~110°C when using the same type of 100 kΩ NTC thermistor used in the current sense amplifier. An additional fixed resistor in parallel with the thermistor allows tuning of the trip point temperatures to match the hottest temperature in the VR, when the thermistor itself is directly sensing a proportionately lower temperature. Setting this resistor value is best accomplished with a variable resistor during thermal validation and then fixing this value for the final design. Additionally, a 0.1 μF capacitor should be used for filtering noise. I CRMS = D × I O × 1 −1 N×D (44) 1 − 1 = 14.7 A 4 × 0.108 I CRMS = 0.108 × 119 A × Rev. 2 | Page 27 of 31 | www.onsemi.com 06094-014 PLACE THERMISTOR NEAR CLOSEST PHASE 0.1μF ADP3198 SHUNT RESISTOR DESIGN The ADP3198 uses a shunt to generate 5 V from the 12 V supply range. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 16 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages. 550 500 450 400 350 300 250 200 150 7.0 PSHUNT RSHUNT 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 11.0 TUNING THE ADP3198 1. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to the circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 2. DC Load Line Setting 3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few mV, adjust RCS1 and RCS2 using Equation 46 and Equation 48. 4. PSHUNT (W) RSHUNT (Ω) RCS2 ( NEW ) = R CS2 (OLD ) × 5. 06094-019 V NL − VFLCOLD V NL − VFLHOT (46) 7.5 8.0 8.5 9.0 VIN (UVLO) 9.5 10.0 10.5 Repeat Step 4 until the cold and hot voltage measurements remain the same. Measure the output voltage from no load to full load using 5 A steps. Compute the load line slope for each change, and then average to get the overall load line slope (ROMEAS). If ROMEAS is off from RO by more than 0.05 mΩ, use Equation 47 to adjust the RPH values. 6. Figure 16. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage The maximum power dissipated is calculated using Equation 45. PMAX where: (V = IN ( MAX ) − VCC ( MIN ) ) 7. 2 R SHUNT (45) R PH ( NEW ) = R PH (OLD ) × 8. ROMEAS RO (47) VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP3198. This is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W. Repeat Step 6 and Step 7 to check the load line. Repeat adjustments if necessary. When the dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure. 9. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. RCS1( NEW ) = RCS1(OLD ) × RTH (25° C ) + RCS1(OLD ) − RCS2 ( NEW ) × RCS1(OLD ) − RTH (25° C ) ( 1 RCS1(OLD ) + RTH (25° C ) )( )− R 1 TH ( 25° C ) (48) AC Load Line Setting 11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 μs/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 17. Rev. 2 | Page 28 of 31 | www.onsemi.com ADP3198 19. If both overshoots are larger than desired, try making the adjustments using the following suggestions: • VACDRP VDCDRP Make the ramp resistor larger by 25% (RRAMP) For VTRAN1, increase CB or increase the switching frequency For VTRAN2, increase RA and decrease CA by 25% • • Figure 17. AC Load Line Waveform If these adjustments do not change the response, the design is limited by the output decoupling. Check the output response every time a change is made, and check the switching nodes to ensure that the response is still stable. 20. For load release (see Figure 19), if VTRANREL is larger than the allowed overshoot, there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be made smaller. When changing inductors, start the design again using a spreadsheet and this tuning procedure. 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown in Figure 17. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 49 to adjust CCS. Users may need to parallel different values to get the right one because limited standard capacitor values are available. It is a good idea to have locations for two capacitors in the layout for this. 06094-015 C CS ( NEW ) = C CS (OLD ) × V ACDRP V DCDRP VTRANREL (49) VDROOP 17. Repeat Step 11 to Step 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. Set the dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means that VACDRP and VDCDRP are equal. Figure 19. Transient Setting Waveform Initial Transient Setting 18. With the dynamic load still set at the maximum step size, expand the scope time scale to either 2 μs/div or 5 μs/div. The waveform can have two overshoots and one minor undershoot (see Figure 18). Here, VDROOP is the final desired value. Because the ADP3198 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. Therefore, the user does not have to add headroom for ripple. This allows load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications. VDROOP LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. VTRAN1 VTRAN2 06094-016 Figure 18. Transient Setting Waveform Rev. 2 | Page 29 of 31 | www.onsemi.com 06094-017 ADP3198 General Recommendations For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3198) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3198 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3198 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (described in the Power Circuitry Recommendations section). board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the Rev. 2 | Page 30 of 31 | www.onsemi.com ADP3198 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX 31 30 40 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 5.75 BCS SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD (BOTTOM VIEW) 4.25 4.10 SQ 3.95 10 11 21 20 0.25 MIN 4.50 REF 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 20. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters ORDERING GUIDE Model ADP3198JCPZ-RL1 1 Temperature Range 0°C to 85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-40 Ordering Quantity 2,500 Z = Pb-free part. are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any ON Semiconductor and products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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