ADP4101JCPZ-RL7

ADP4100 Product Preview Programmable Multi-Phase Synchronous Buck Converter The ADP4100 is an integrated power control IC for VR11.1 applications. The ADP4100 can be programmed for 1−, 2−, 3−, 4−, 5− or 6−phase operation, allowing for the construction of up to six complementary buck switching stages. The ADP4100 supports PSI, which is a power state indicator and can be used to reduce number of operating phases at light loads. The ADP4100 is optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8−bit DAC to read the voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.375 V and 1.6 V. http://onsemi.com ADP4100 JCPZ #YYWW XXXXX CCCCC Features xx # YYWW XXX CCC Supports Both VR11 and VR11.1 Specifications Digitally Programmable 0.375 V to 1.6 V Output Selectable 1−, 2−, 3−, 4−, 5− or 6−Phase Operation Fast−Enhanced PWM FlexModet TRDET to Improve Load Release Active Current Balancing Between All Output Phases Supports On−The−Fly (OTF) VID Code Changes Supports PSI − Power Saving Mode Short Circuit Protection with Latchoff Delay This is a Pb−Free Device = Device Code = Pb−Free Package = Date Code = Assembly Lot = Country of Origin PIN ASSIGNMENT 48 VCC3 47 PWRGD 46 PSI 45 VID0 44 VID1 43 VID2 42 VID3 41 VID4 40 VID5 39 VID6 38 VID7 37 VCC • • • • • • • • • • MARKING DIAGRAM LFCSP48 CASE 932AD NC 1 NC 2 NC 3 NC 4 EN 5 Typical Applications ADP4100 GND 6 PSI_SET 7 LLSET 8 IMON 9 TTSENSE 10 VRHOT 11 IREF 12 TOP VIEW (Not to Scale) RT 13 RAMPADJ 14 TRDET 15 FBRTN 16 COMP 17 FB 18 CSREF 19 CSSUM 20 CSCOMP 21 ILIMFS 22 ODN 23 OD1 24 • Servers • Desktop PC’s • POLs (Memory) 36 PWM1 35 PWM2 34 PWM3 33 PWM4 32 PWM5 31 PWM6 30 SW1 29 SW2 28 SW3 27 SW4 26 SW5 25 SW6 PIN 1 INDICATOR ORDERING INFORMATION Device* Package Shipping† ADP4100JCPZ−REEL LFCSP48 2500/Tape & Reel ADP4100JCPZ−RL7 This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2008 March, 2008 − Rev. P0 1 LFCSP48 750/Tape & Reel *The “Z’ suffix indicates Pb−Free package. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: ADP4100/D ADP4100 VCC VCC3 37 48 TRDET RT SHUNT REGULATOR 3.3 V REGULATOR 15 RAMPADJ 13 14 46 PSI 7 PSI_SET 23 ODN 24 OD1 36 PWM1 RESET 35 PWM2 RESET 34 PWM3 33 PWM4 32 PWM5 31 PWM6 OSCILLATOR UVLO SHUTDOWN GND 6 SET + RESET CMP – 850 mV + – EN/VTT 5 CMP – + + VRHOT 11 CURRENT BALANCING CIRCUIT THERMAL THROTTLING CONTROL TTSENSE 10 CMP – 2 / 3 / 4 /5 / 6 PHASE DRIVER LOGIC + RESET CMP – + RESET CMP – Over Voltage Threshold – CSREF + RESET CMP + – CURRENT LIMIT CROWBAR + Under Voltage Threshold – DELAY CURRENT MEASUREMENT AND LIMIT + ILIMFS 22 – PWRGD 47 EN 30 SW1 29 SW2 28 SW3 27 SW4 26 SW5 25 SW6 21 CSCOMP 19 CSREF 20 CSSUM 9 IMON 18 FB 8 LLSET IREF 12 – COMP 17 + + – ADP4100 PRECISION REFERENCE 16 FBRTN – BOOT VOLTAGE AND SOFT−START CONTROL VID DAC 45 44 43 42 41 40 39 38 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 Figure 1. Simplified Block Diagram http://onsemi.com 2 + 100 k NTC 3 VID1 COMP VID0 FBRTN RAMPADJ RT 220 k Figure 2. Application Schematic http://onsemi.com 470 pF X7R CSSUM 32.4 k CSCOMP VID4 1.21 k VID5 6.81 k, 1% 1000 pF 35.7 k 1500 pF X7R 82.5 k 1k 1k 1k 1k 1k 1k 5% 100 k Thermistor 1500 pF X7R SW6 SW5 SW4 SW3 SW2 SW1 PWM6 OD1 3.3 pF ILIMFS 560 pF ODN VID6 4.99 k VID7 69.8 k PSI 121 k ADP4100 IREF VRHOT TTSENSE IMON LLSET PSI_SET PWM4 PWM3 PWM5 1 uF X7R 680 470 pF X7R 0.1uF PROCHOT VCC3 GND PWRGD 4.54 k 1 nF VID2 EN NC NC VID3 20 k 4.7 uF VTT I/O PWM2 PWM1 VCC NC 1200 uF 16 V 680 NC POWER GOOD PSI 1 uF X7R 1k Vin 12 V CSREF FB TRDET 348 k 4.7 uF 4.7 uF 4.7 uF 4.7 uF 4.7 uF 4.7 uF 18 nF OD VCC 2 3 4 18 nF DRVL 5 PGND 6 SW 7 DRVH 8 OD VCC 2 3 4 18 nF OD VCC 2 3 4 18 nF OD VCC 2 3 4 18 nF DRVL 5 PGND 6 SW 7 DRVH 8 VCC 4 18 nF DRVL 5 PGND 6 SW 7 DRVH 8 BST IN OD VCC 1 2 3 4 DRVL 5 PGND 6 SW 7 DRVH 8 ADP3121 10 nF 2.2 OD 2 3 BST IN 1 ADP3121 10 nF 2.2 BST IN 1 10 nF DRVL 5 PGND 6 SW 7 DRVH 8 ADP3121 2.2 BST IN 1 10 nF DRVL 5 PGND 6 SW 7 DRVH 8 ADP3121 2.2 BST IN 1 ADP3121 10 nF 2.2 BST IN 1 ADP3121 10 nF 2.2 150 nH 4.7 uF 150 nH 4.7 uF 150 nH 4.7 uF 150 nH 4.7 uF 150 nH 4.7 uF 150 nH 4.7 uF 10 10 10 10 10 10 Vcc Core (RTN) Vcc Core Vcc Sense Vss Sense ADP4100 63.4 k 63.4 k 63.4 k 63.4 k 63.4 k 63.4 k ADP4100 ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VIN −0.3 to 6 V VFBRTN −0.3 to + 0.3 V V −0.3 to VIN + 0.3 V SW1 to SW6 −5 to +25 V V SW1 to SW6 ( 0.8 V, Internal Delay tDELAY(EN) 2.0 ms Output Low Voltage IOD(SINK) = −400 mA VOL(ODN/1) 160 Output High Voltage IOD(SOURCE) = 400 mA VOL(ODN/1) Delay Time 0.3 0.8 V V ODN and OD1 Outputs 4.0 ODN / OD1 Pulldown Resistor 500 mV 5.0 V 60 kW Power−Good Comparator Undervoltage Threshold Relative to Nominal DAC Output VPWRGD(UV) −600 −500 −400 mV Overvoltage Threshold Relative to DAC Output, PWRGD_Hi = 00 VPWRGD(OV) 200 300 400 mV Output Low Voltage IPWRGD(SINK) = −4 mA VOL(PWRGD) 150 300 mV 6. Guaranteed by design or bench characterization, not tested in production. http://onsemi.com 7 ADP4100 ELECTRICAL CHARACTERISTICS Vin = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit Power Good Delay Time During Soft−Start (Note 6) Internal Timer 2.0 ms Power−Good Comparator VID Code Changing 100 VID Code Static Crowbar Trip Point Relative to DAC Output, PWRGD_Hi = 00 Crowbar Reset Point Relative to FBRTN Crowbar Delay Time Overvoltage to PWM going low VCROWBAR 250 ms 200 ns 200 300 400 mV 250 300 350 mV 100 250 ms 400 ns tCROWBAR VID Code Changing VID Code Static PWM Outputs Output Low Voltage IPWM(SINK) = −400 mA VOL(PWM) Output High Voltage IPWM(SOURCE) = 400 mA VOH(PWM) 160 4.0 500 5.0 mV V VRHOT Output Output Low Voltage IVRHOT(SINK) = −6 mA VOL(VRHOT) Output High Leakage Current VOH = 5.0 V IOH(VRHOT) 160 500 mV 1.0 mA 2 V TTSENSE Inputs TTSENSE Voltage Range Internally Limited Source Current RIREF = 121 kW 0 ITH VRHOT Voltage Threshold −110 −125 −140 mA 780 810 840 mV VRHOT Hysteresis VRHOT Output Low Voltage 55 IVRHOT(SINK) = −4mA mV 150 300 mV 5.25 5.75 V 20 25 mA 6.5 11 mA Supply VCC (Note 6) VCC 4.7 DC Supply Current (see Figure 2) VSYSTEM = 13.2 V, RSHUNT = 340 W IVCC UVLO Turn−On Current UVLO Threshold Voltage VCC Rising UVLO Turn−Off Voltage VCC Falling VCC3 Output Voltage IVCC3 = 1 mA VUVLO 9.5 V 4.1 VCC3 6. Guaranteed by design or bench characterization, not tested in production. http://onsemi.com 8 3.0 3.3 V 3.6 V ADP4100 TYPICAL CHARACTERISTICS 3000 2500 Frequency (Hz) 2000 PWM1 1500 1000 500 0 13 20 30 43 50 68 75 82 130 180 270 395 430 500 680 850 RT (kW) Figure 3. ADP4100 RT vs Frequency http://onsemi.com 9 ADP4100 TEST CIRCUITS +12 V 680W 100nF VCC3 PWRGD PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC +1mF 680W +1.25 V 121kW ADP4100 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SW1 SW2 SW3 SW4 SW5 SW6 RT RAMPADJ TRDET FBRTN COMP FB CSREF CSSUM CSCOMP ILIMITFS ODN OD1 NC NC NC NC EN GND PSI_SET LLSET IMON TTSENSE VRHOT IREF 1kW 20kW 10kW 100nF Figure 4. Closed−Loop Output Voltage Accuracy ADP4100 +12 V 680 W 680 W 12V COMP ADP4100 680W VCC 37 680W 17 VCC 10 k 37 FB – 18 + CSCOMP 21 LLSET 8 CSSUM 20 1kW nV + – 39kW 100nF 1.0V + – 1V GND 6 VOS = CSCOMP – 1V 40 + – CSREF 19 CSREF 19 – + VID DAC GND 6 nVFB = FBDV=80mV − FBnV=0mV Figure 5. Current Sense Amplifier VOS Figure 6. Positioning Accuracy http://onsemi.com 10 ADP4100 Theory of Operation Figure 8 typical startup waveforms: Channel 1: CSREF Channel 2: PWM1 Channel 3 : Enable The ADP4100 is a 6−Phase VR11.1 regulator. A typical application circuits is shown in Figure 2. Startup Sequence The ADP4100 follows the VR11 startup sequence shown in Figure 7. After both the EN and UVLO conditions are met, an internal timer goes through one delay cycle TD1 (= 2ms). The first six clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the following section. Then the internal soft−start ramp is enabled (TD2) and the output comes up to the boot voltage of 1.1V. The voltage is held at 1.1V for the 2 ms, also known as the Boot Hold time or TD3. During TD3 the processor VID pins settle to the required VID code. When TD3 is over, the ADP4100 reads the VID inputs and soft−starts either up or down to the final VID voltage (TD4). After TD4 has been completed and the PWRGD masking time (equal to VID on the fly masking) is finished, a third cycle of the internal timer sets the PWRGD blanking (TD5). 5V SUPPLY VTT I/O (ADP4100 EN) VCC_CORE Phase Detection During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP4100 operates as a 6−Phase PWM controller. To operate as a 5−Phase Controller connect PWM6 to VCC. To operate as a 4−Phase Controller connect PWM5 and PWM6 to VCC. To operate as a 3−Phase Controller connect PWM4, PWM5 and PWM6 to VCC. To operate as a 2−Phase Controller connect PWM3, PWM4, PWM5 and PWM6 to VCC. To operate as a single phase controller connect PMW2, PWM3, PWM4, PWM5 and PWM6 to VCC. Prior to soft−start, while EN is high the PWM6, PWM5, PWM4 PWM3 and PWM2 pins sink approximately 100 mA each. An internal comparator checks each pin’s voltage vs. a threshold of 3.0 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 is low during the phase detection interval that occurs during the first six clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 mA current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 mA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the ADP3121. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases. UVLO THRESHOLD 0.85V TD3 VBOOT (1.1V) TD1 VVID TD4 TD2 VR READY (ADP4100 PWRGD) 50ms CPU VID INPUTS VID INVALID TD5 VID VALID Figure 7. System Startup Sequence for VR11 Figure 8 shows typical startup waveforms for the ADP4100. Master Clock Frequency The clock frequency of the ADP4100 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 6. If 4 phases are in use then divide by 4. RT + n 1 f sw Cr * R TO (eq. 1) Where: CT = 2.2 pF and RTO = 21 K Output Voltage Differential Sensing The ADP4100 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst−case specification of ±7 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB is connected Figure 8. Shows Typical Startup Waveforms for the ADP4100 http://onsemi.com 11 ADP4100 through a resistor, RB, to the regulation point, usually the remote sense pin of the microprocessor. FBRTN is connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 mA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. I ILIMFS + V ILIMFS * V CSCOMP R ILIMFS (eq. 2) Where: VILIMFS = VCSREF I ILIMFS + V CSREF * V CSCOMP R ILIMFS V CSREF * V CSCOMP + Output Current Sensing R CS R PH (eq. 3) RL I LOAD Where: RL = DCR of the Inductor Assuming that: The ADP4100 provides a dedicated Current−Sense Amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current, for the IMON output and for current−limit detection. Sensing the load current at the output gives the total real time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low−side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system, as follows: • Output inductor DCR sensing without a thermistor for lowest cost. • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature. • Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the average output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is used as a differential input for the current−limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate. R CS R PH R L + 1 mW (eq. 4) i.e. the external circuit is set up for a 1 mW Loadline then the RILIMFS is calculated as follows: I ILIMFS + 1 mW I LOAD R LIMITS (eq. 5) Assuming we want a current limit of 150 A that means that ILIMFS must equal 22 mA at that load. 22 mA + 1 mW 150 A R LIMITFS (eq. 6) Solving this equation for RLIMITFS we get 6.8 kW. Closest 1% resistor is 6.81 kW. Current−Limit, Short−Circuit and Latchoff Protection If the current limit is reached and TD5 has completed, an internal latchoff delay time will start, and the controller will shut down if the fault is not removed. This delay is four times longer than the delay time during the startup sequence. The current limit delay time only starts after the TD5 has completed. If there is a current limit during startup, the ADP4100 will go through TD1 to TD5, and then start the latchoff time. Because the controller continues to cycle the phases during the latchoff delay time, if the short is removed before the timer is complete, the controller can return to normal operation. The latchoff function can be reset by either removing and reapplying the supply voltage to the ADP4100, or by toggling the EN pin low for a short time. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit limits the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low−side MOSFETs through the current balance circuitry. Typical overcurrent latchoff waveforms are shown in Figure 9). Current−Limit Setpoint The current limit threshold on the ADP4100 is programmed by a resistor between the ILIMFS pin and the CSCOMP pin. The ILIMFS current, IILIMFS, is compared with an internal current reference of 22 mA. If IILIMFS exceeds 22 mA then the output current has exceeded the limit and the current limit protection is tripped. http://onsemi.com 12 ADP4100 resistor only. This is because the ILIMITFS resistor sets up both the current limit and also the current out of the IMON pin, as explained earlier. The IMON pin also includes an active clamp to limit the IMON voltage to 1.15 V MAX while maintaining accuracy at 900 mV full scale. Active Impedance Control Mode For controlling the dynamic output voltage droop as a function of output current, the CSA gain and load line programming can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed−forward response. Figure 9. Overcurrent Latchoff Waveforms Channel 1: CSREF, Channel 2: COMP, Channel 3: PWM1 An inherent per phase current limit protects individual phases if one or more phases stops functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Load Line Setting For load line values greater than 1 mW, RCSA can be set equal to RO, and the LLSET pin can be directly connected to the CSCOMP pin. When the load line value needs to be less than 1 mW, two additional resistors are required. Figure 10 shows the placement of these resistors. Output Current Monitor IMON is an analog output from the ADP4100 representing the total current being delivered to the load. It outputs an accurate current that is directly proportional to the current set by the ILIMFS resistor. I IMON + 10 I SW I LIMFS ADP4100 (eq. 7) CSCOMP The current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage as per the VR11.1 specification. The size of the resistor is used to set the IMON scaling. The scaling is set such that IMON = 900 mV at the TDC current of the processor. This means that the RIMON resistor should be chosen as follows. From the Current−Limit Setpoint paragraph we know the following: 1 mW I LOAD I ILIMFS + R LIMFS I IMON + 10 CSSUM CSREF 1 mW 135 A + 198mA 6.81 kW V IMON + 900 mV + 198 mA 19 LLSET RLL2 OPTIONAL LOAD LINE SELECT SWITCH 8 QLL Figure 10. Load Line Setting Resistors The two resistors RLL1 and RLL2 set up a divider between the CSCOMP pin and CSREF pin. This resistor divider is input into the LLSET pin to set the load line slope RO of the VR according to the following equation: For a 150 A current limit RLIMFS = 6.81 kW. Assuming the TDC = 135 A then VMON should equal 900 mV when ILOAD = 135 A. When ILOAD = 135 A, IMON equals: I MON + 10 20 RLL1 (eq. 8) 1 mW I LOAD R LIMFS 21 RO + R LL2 R LL1 ) R LL2 R CSA (eq. 10) The resistor values for RLL1 and RLL2 are limited by two factors. • The minimum value is based upon the loading of the CSCOMP pin. This pin’s drive capability is 500 mA and the majority of this should be allocated to the CSA feedback. If the current through RLL1 and RLL2 is limited to 10% of this (50 mA), the following limit can be placed for the minimum value for RLL1 and RLL2: (eq. 9) R MON This gives a value of 4.54 kW for RMON. If the TDC and OCP limit for the processor have to be changed then it may be necessary to change the ILIMITFS http://onsemi.com 13 ADP4100 R LL1 ) R LL2 w I LIM 50 R CSA 10 *6 This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to 16 mA) from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with respect to the VID DAC for Intel CPU’s. The value of RB can be found using the following equation: (eq. 11) Here, ILIM is the current−limit current, which is the maximum signal level that the CSA responds to. • The maximum value is based upon minimizing induced dc offset errors based on the bias current of the LLSET pin. To keep the induced dc error less than 1 mV, which makes this error statistically negligible, place the following limit of the parallel combination of RLL1 and RLL2: It is best to select the resistor values to minimize their values to reduce the noise and parasitic susceptibility of the feedback path. R LL1 R LL2 *3 v 1 10 *9 + 8.33 kW R LL1 ) R LL2 120 10 (eq. 12) RB + By combining Equation 10 with Equation 12 and selecting minimum values for the resistors, the following equations result: R LL2 + I LIM R O 50 mA R LL1 + ǒ Ǔ R LL2 (eq. 15) RAMPADJ Input Current The resistor connected to the Rampadj pin sets the internal PWM ramp. The value for this resistor is chosen to provide the combination of thermal balance, stability and transient response. (eq. 13) R CSA *1 RO V VID * V ONL I FB (eq. 14) RR + Therefore, both RLL1 and RLL2 need to be in parallel and less than 8.33 kW. Another useful feature for some VR applications is the ability to select different load lines. Figure 10 shows an optional MOSFET switch that allows this feature. Here, design for RCSA = RO(MAX) (selected with QLL on) and then use Equation 10 to set RO = RO(MIN) (selected with QLL off). For this design, RCSA = RO = 1 mW. As a result, connect LLSET directly to CSCOMP; the RLL1. 3 AR L A D R DS (eq. 16) CR Where AR is the internal ramp amplifier gain (= 0.5) AD is the current balancing amplifier gain (= 5) RDS is the total low side MOSFET on resistance CR is the internal ramp capacitor value (= 5pF). The internal ramp voltage can be calculated as follows: VR + A R (1 * D) V VID R R C R f SW (eq. 17) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and noise rejection improves but the transient performance decreases. If the ramp is made smaller then the transient response improves however noise rejection and stability degrades. Current Control Mode and Thermal Balance The ADP4100 has individual inputs (SW1 to SW6) for each phase that are used for monitoring the current of each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed−forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. COMP Pin Ramp There is a ramp signal on the COMP signal, which is due to the droop voltage and the output voltage ramps. This ramp adds to the internal ramp to produce the following ramp signal at the PWM input. V RT + ǒ VR 1* Ǔ 2 (1*n D) n f SW C X R O (eq. 18) Where Cx = bulk capacitance RO = Droop n = number of phases fSW = switching frequency per phase D = duty cycle VR = Internal Ramp Voltage (calculated in Rampadj section of this data sheet) Voltage Control Mode A high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in VID Code Table. The VID code is set using the VID Input pins. http://onsemi.com 14 ADP4100 Reference Current This ramp voltage should be set to at least 0.5 V for noise immunity reasons. If it is less than 0.5 V then decrease the ramp resistor. The IREF pin is used to set an internal current reference. This reference current sets IFB and ITTSENSE. A resistor to ground programs the current based on the 1.8 V output. Dynamic VID The ADP4100 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as Dynamic VID (DVID). A DVID can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in a single or multiple steps from the start code to the finish code. This change can be positive or negative. When a VID bit changes state, the ADP4100 detects the change and ignores the DAC inputs for a minimum of 200 ns. This time prevents a false code due to logic skew while the VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 ms to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. If a VID off code is detected the ADP4100 will wait for 5 msec to ensure that the code is correct before initiating a shutdown of the controller. I REF + 1.8 V R IREF (eq. 19) Typically, RIREF is set to 121 kW to program IREF = 15 mA. The following currents are then equal to: I FB + I REF + 15 mA (eq. 20) I TTSENSE + −8 (I IREF) + −120 mA Power Good Monitoring The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open−drain output whose high level (when connected to a pullup resistor) indicates that the output voltage is within the nominal limits specified in the specifications above based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a DVID event for a period of 100 ms to prevent false signals during the time the output is charging. The PWRGD circuitry also incorporates an initial turn−on delay time (TD5). Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS circuit reaches the programmed DAC voltage, the internal timer operates. The range for the PWRGD comparator is +300 mV and −500 mV. Enhanced Transients Mode The ADP4100 incorporates enhanced transient response for both load step up and load release. For load step up it senses the output of the error amp to determine if a load step up has occurred and then sequences on the appropriate number of phases to ramp up the output current. For load release, it also senses the output of the error amp and uses the load release information to trigger the TRDET pin, which is then used to adjust the error amp feedback for optimal positioning. This is especially important during high frequency load steps. Additional information is used during load transients to ensure proper sequencing and balancing of phases during high frequency load steps as well as minimizing the stress on components such as the input filter and MOSFETs. Power State Indicator The PSI pin is an input used to determine the operating state of the load. If this input is pulled low, the load is in a low power state and the controller asserts the ODN pin low, which can be used to disable phases and maintain better efficiency at lighter loads. The sequencing into and out of low power operation is maintained to minimize output deviations as well as providing full power load transients immediately after exiting a low power state. The user can program if one or two phases are enabled during PSI using the PSI_SET pin. If this pin is pulled low then 1 phase is enabled (always phase 1). If it is pulled high then two phases are enabled (phase 1 and phase 4 in a 6−phase or 5−phase system, phase 1 and phase 3 in a 4−phase system. Extreme care should be taken to ensure that OD1 is connected to all phases enabled during PSI. TRDET and Phase Shuffling The ADP4100 senses the error amp output and triggers the TRDET pin when a load release takes place. The TRDET circuit, as shown in Figure 2, adjusts the feedback for optimal positioning especially during high frequency load steps. TRDET is also used to trigger phase shuffling. If repeated transients take place at the switching frequency then its possible for one phase to carry most of the currrent. To prevent this from happening the ADP4100 will shuffle the phases whenever a load release happens, i.e. it will randomize the phase sequence. http://onsemi.com 15 ADP4100 PSI Set Table # of Phases Normally PSI Set accuracy, the thermistors can be linearized using resistors. A fixed current of 8 times IREF (normally giving 120 mA) is sourced out of the TTSENSE pin into the thermistor. The resulting voltage is compared with the VRHOT Threshold (0.81 V). When the meaured voltage goes below the threshold (i.e. using this thermistor and resistor combination, when the temperature has exceeded approximately 85 °C) the VRHOT signal asserts high. VRHOT is low when the temperature is below the limit (i.e. the volatge is higher than the threshold). Phases on During PSI 6 High Low Phase 1 and 4 Phase 1 5 High Low Phase 1 and 4 Phase 1 4 High Low Phase 1 and 3 Phase 1 3 High Low Phase 1 Phase 1 2 High Low Phase 1 Phase 1 1 High Low Phase 1 Phase 1 120 mA Output Crowbar As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low−side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300 mV. The value for the crowbar limit follows the PWRGD high limit. Turning on the low−side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high−side MOSFET, this action current−limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. TTSENSE NTC 100 kW - 20 kW 0.81 V + VRHOT Figure 11. TTSENSE Diagram Shunt Resistor The ADP4100 uses a shunt to generate 5.0 V from the 12 V supply range. A trade−off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 12 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages. Output Enable and UVLO For the ADP4100 to begin switching, the input supply current to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.8 V threshold. This initiates a system startup sequence. If either UVLO or EN is less than their respective thresholds, the ADP4100 is disabled. This holds the PWM outputs at ground and forces PWRGD, ODN and OD1 signals low. In the application circuit (see Figure 2), the OD1 pin should be connected to the OD inputs of the external drivers for the phases that are always on. The ODN pin should be connected to the OD inputs of the external drivers on the phases that are shutdown during low power operation. Grounding the driver OD inputs disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. 0.325 400 0.3 350 0.275 Rshunt 300 0.25 250 0.225 200 Pshunt 2−0603 Limit 2−0805 Limit 0.2 0.175 150 8 9 10 11 12 13 14 15 16 ICC (UVLO) Thermal Monitoring Figure 12. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage The ADP4100 includes a thermal monitoring channel using a thermistor. The VR thermal monitoring circuits require an NTC thermistor to be placed from TTSENSE to GND. For best http://onsemi.com 16 ADP4100 Driver Connections The maximum power dissipated is calculated using Equation 21. P MAX + ǒVIN(MAX) * VCC(MIN)Ǔ R SHUNT Each driver in the external circuit is connected to one PWM signal from the controller. The PWM signal controls when the driver turns on and off both the high and low side FET’s. Each driver is also connected to either the OD1 or ODN signal from the controller. This signal is used to disable the driver, i.e. both high side and low side FET’s are disabled. Drivers are disabled when OD pins are low and switching when the OD pin is high. Phases which are enabled during PSI should be connected to OD1. Phases which are disabled during PSI should be connected to ODN. Extreme care should be taken to ensure that the controller configuration (set by the PSI_Set pin) matches the OD1 and ODN connections on the board. 2 (eq. 21) where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP4100. This is specified as 4.7 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface−mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W. VID Inputs The ADP4100 has seven VID Input pins which are used to set the target output voltage. The VID codes are decoded using the following VR11.1 Table. An input voltage of less than 0.3 V is decoded as logic low. An input voltage of greater than 0.8 V is decoded as logic high. If the pins are left open then an internal pulldown will pull the pin low. VCC3 The ADP4100 has an internal 3.3 V LDO to supply the internal circuits on the ADP4100. A 1 mF X7R capacitor should be placed between this pin and AGND. This should not be loaded by an external circuitry. http://onsemi.com 17 ADP4100 VR11 VID CODES for the ADP4100 OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 OFF 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 1.60000 0 0 0 0 0 0 1 0 1.59375 0 0 0 0 0 0 1 1 1.58750 0 0 0 0 0 1 0 0 1.58125 0 0 0 0 0 1 0 1 1.57500 0 0 0 0 0 1 1 0 1.56875 0 0 0 0 0 1 1 1 1.56250 0 0 0 0 1 0 0 0 1.55625 0 0 0 0 1 0 0 1 1.55000 0 0 0 0 1 0 1 0 1.54375 0 0 0 0 1 0 1 1 1.53750 0 0 0 0 1 1 0 0 1.53125 0 0 0 0 1 1 0 1 1.52500 0 0 0 0 1 1 1 0 1.51875 0 0 0 0 1 1 1 1 1.51250 0 0 0 1 0 0 0 0 1.50625 0 0 0 1 0 0 0 1 1.50000 0 0 0 1 0 0 1 0 1.49375 0 0 0 1 0 0 1 1 1.48750 0 0 0 1 0 1 0 0 1.48125 0 0 0 1 0 1 0 1 1.47500 0 0 0 1 0 1 1 0 1.46875 0 0 0 1 0 1 1 1 1.46250 0 0 0 1 1 0 0 0 1.45625 0 0 0 1 1 0 0 1 1.45000 0 0 0 1 1 0 1 0 1.44375 0 0 0 1 1 0 1 1 1.43750 0 0 0 1 1 1 0 0 1.43125 0 0 0 1 1 1 0 1 1.42500 0 0 0 1 1 1 1 0 1.41875 0 0 0 1 1 1 1 1 1.41250 0 0 1 0 0 0 0 0 1.40625 0 0 1 0 0 0 0 1 1.40000 0 0 1 0 0 0 1 0 1.39375 0 0 1 0 0 0 1 1 1.38750 0 0 1 0 0 1 0 0 1.38125 0 0 1 0 0 1 0 1 1.37500 0 0 1 0 0 1 1 0 1.36875 0 0 1 0 0 1 1 1 1.36250 0 0 1 0 1 0 0 0 1.35625 0 0 1 0 1 0 0 1 1.35000 0 0 1 0 1 0 1 0 1.34375 0 0 1 0 1 0 1 1 1.33750 0 0 1 0 1 1 0 0 1.33125 0 0 1 0 1 1 0 1 http://onsemi.com 18 ADP4100 VR11 VID CODES for the ADP4100 OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.32500 0 0 1 0 1 1 1 0 1.31875 0 0 1 0 1 1 1 1 1.31250 0 0 1 1 0 0 0 0 1.30625 0 0 1 1 0 0 0 1 1.30000 0 0 1 1 0 0 1 0 1.29375 0 0 1 1 0 0 1 1 1.28750 0 0 1 1 0 1 0 0 1.28125 0 0 1 1 0 1 0 1 1.27500 0 0 1 1 0 1 1 0 1.26875 0 0 1 1 0 1 1 1 1.26250 0 0 1 1 1 0 0 0 1.25625 0 0 1 1 1 0 0 1 1.25000 0 0 1 1 1 0 1 0 1.24375 0 0 1 1 1 0 1 1 1.23750 0 0 1 1 1 1 0 0 1.23125 0 0 1 1 1 1 0 1 1.22500 0 0 1 1 1 1 1 0 1.21875 0 0 1 1 1 1 1 1 1.21250 0 1 0 0 0 0 0 0 1.20625 0 1 0 0 0 0 0 1 1.20000 0 1 0 0 0 0 1 0 1.19375 0 1 0 0 0 0 1 1 1.18750 0 1 0 0 0 1 0 0 1.18125 0 1 0 0 0 1 0 1 1.17500 0 1 0 0 0 1 1 0 1.16875 0 1 0 0 0 1 1 1 1.16250 0 1 0 0 1 0 0 0 1.15625 0 1 0 0 1 0 0 1 1.15000 0 1 0 0 1 0 1 0 1.14375 0 1 0 0 1 0 1 1 1.13750 0 1 0 0 1 1 0 0 1.13125 0 1 0 0 1 1 0 1 1.12500 0 1 0 0 1 1 1 0 1.11875 0 1 0 0 1 1 1 1 1.11250 0 1 0 1 0 0 0 0 1.10625 0 1 0 1 0 0 0 1 1.10000 0 1 0 1 0 0 1 0 1.09375 0 1 0 1 0 0 1 1 1.08750 0 1 0 1 0 1 0 0 1.08125 0 1 0 1 0 1 0 1 1.07500 0 1 0 1 0 1 1 0 1.06875 0 1 0 1 0 1 1 1 1.06250 0 1 0 1 1 0 0 0 1.05625 0 1 0 1 1 0 0 1 1.05000 0 1 0 1 1 0 1 0 1.04375 0 1 0 1 1 0 1 1 http://onsemi.com 19 ADP4100 VR11 VID CODES for the ADP4100 OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.03750 0 1 0 1 1 1 0 0 1.03125 0 1 0 1 1 1 0 1 1.02500 0 1 0 1 1 1 1 0 1.01875 0 1 0 1 1 1 1 1 1.01250 0 1 1 0 0 0 0 0 1.00625 0 1 1 0 0 0 0 1 1.00000 0 1 1 0 0 0 1 0 0.99375 0 1 1 0 0 0 1 1 0.98750 0 1 1 0 0 1 0 0 0.98125 0 1 1 0 0 1 0 1 0.97500 0 1 1 0 0 1 1 0 0.96875 0 1 1 0 0 1 1 1 0.96250 0 1 1 0 1 0 0 0 0.95625 0 1 1 0 1 0 0 1 0.95000 0 1 1 0 1 0 1 0 0.94375 0 1 1 0 1 0 1 1 0.93750 0 1 1 0 1 1 0 0 0.93125 0 1 1 0 1 1 0 1 0.92500 0 1 1 0 1 1 1 0 0.91875 0 1 1 0 1 1 1 1 0.91250 0 1 1 1 0 0 0 0 0.90625 0 1 1 1 0 0 0 1 0.90000 0 1 1 1 0 0 1 0 0.89375 0 1 1 1 0 0 1 1 0.88750 0 1 1 1 0 1 0 0 0.88125 0 1 1 1 0 1 0 1 0.87500 0 1 1 1 0 1 1 0 0.86875 0 1 1 1 0 1 1 1 0.86250 0 1 1 1 1 0 0 0 0.85625 0 1 1 1 1 0 0 1 0.85000 0 1 1 1 1 0 1 0 0.84375 0 1 1 1 1 0 1 1 0.83750 0 1 1 1 1 1 0 0 0.83125 0 1 1 1 1 1 0 1 0.82500 0 1 1 1 1 1 1 0 0.81875 0 1 1 1 1 1 1 1 0.81250 1 0 0 0 0 0 0 0 0.80625 1 0 0 0 0 0 0 1 0.80000 1 0 0 0 0 0 1 0 0.79375 1 0 0 0 0 0 1 1 0.78750 1 0 0 0 0 1 0 0 0.78125 1 0 0 0 0 1 0 1 0.77500 1 0 0 0 0 1 1 0 0.76875 1 0 0 0 0 1 1 1 0.76250 1 0 0 0 1 0 0 0 0.75625 1 0 0 0 1 0 0 1 http://onsemi.com 20 ADP4100 VR11 VID CODES for the ADP4100 OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.75000 1 0 0 0 1 0 1 0 0.74375 1 0 0 0 1 0 1 1 0.73750 1 0 0 0 1 1 0 0 0.73125 1 0 0 0 1 1 0 1 0.72500 1 0 0 0 1 1 1 0 0.71875 1 0 0 0 1 1 1 1 0.71250 1 0 0 1 0 0 0 0 0.70625 1 0 0 1 0 0 0 1 0.70000 1 0 0 1 0 0 1 0 0.69375 1 0 0 1 0 0 1 1 0.68750 1 0 0 1 0 1 0 0 0.68125 1 0 0 1 0 1 0 1 0.67500 1 0 0 1 0 1 1 0 0.66875 1 0 0 1 0 1 1 1 0.66250 1 0 0 1 1 0 0 0 0.65625 1 0 0 1 1 0 0 1 0.65000 1 0 0 1 1 0 1 0 0.64375 1 0 0 1 1 0 1 1 0.63750 1 0 0 1 1 1 0 0 0.63125 1 0 0 1 1 1 0 1 0.62500 1 0 0 1 1 1 1 0 0.61875 1 0 0 1 1 1 1 1 0.61250 1 0 1 0 0 0 0 0 0.60625 1 0 1 0 0 0 0 1 0.60000 1 0 1 0 0 0 1 0 0.59375 1 0 1 0 0 0 1 1 0.58750 1 0 1 0 0 1 0 0 0.58125 1 0 1 0 0 1 0 1 0.57500 1 0 1 0 0 1 1 0 0.56875 1 0 1 0 0 1 1 1 0.56250 1 0 1 0 1 0 0 0 0.55625 1 0 1 0 1 0 0 1 0.55000 1 0 1 0 1 0 1 0 0.54375 1 0 1 0 1 0 1 1 0.53750 1 0 1 0 1 1 0 0 0.53125 1 0 1 0 1 1 0 1 0.52500 1 0 1 0 1 1 1 0 0.51875 1 0 1 0 1 1 1 1 0.51250 1 0 1 1 0 0 0 0 0.50625 1 0 1 1 0 0 0 1 0.50000 1 0 1 1 0 0 1 0 OFF 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1 FlexMode is a trademark of Analog Devices, Inc. http://onsemi.com 21 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LFCSP48 7x7, 0.5P CASE 932AD−01 ISSUE A DATE 23 JAN 2009 SCALE 2:1 D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B D1 PIN ONE REFERENCE E1 E DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M 0.20 C TOP VIEW 0.20 C H (A3) 0.10 C A NOTE 4 0.08 C SIDE VIEW A1 C 4X M D2 K 4X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 7.00 BSC 6.75 BSC 4.95 5.25 7.00 BSC 6.75 BSC 4.95 5.25 0.50 BSC −−− 12 ° 0.20 −−− 0.30 0.50 −−− 0.60 SOLDERING FOOTPRINT* 7.30 M 5.14 13 48X 0.63 25 1 E2 PIN 1 INDICATOR 5.14 48X 7.30 L 1 37 48 e BOTTOM VIEW 48X b 0.10 C A B 0.05 C NOTE 3 PACKAGE OUTLINE 48X 0.50 PITCH 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON26683D LFCSP48, 7x7, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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