ADT7460ARQZ-REEL

dBCOOL™ Remote Thermal Controller and Fan Controller ADT7460 FEATURES GENERAL DESCRIPTION Controls and monitors up to 4 fan speeds 1 on-chip and 2 remote temperature sensors Dynamic TMIN control mode optimizes system acoustics intelligently Automatic fan speed control mode controls system cooling based on measured temperature Enhanced acoustic mode dramatically reduces user perception of changing fan speeds Thermal protection feature via THERM output Monitors performance impact of Intel® Pentium® 4 Processor thermal control circuit via THERM input 2-wire and 3-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications (fully SMBus 1.1-compliant) The ADT74601 dBCOOL controller is a thermal monitor and multiple PWM fan controller for noise-sensitive applications requiring active system cooling. It can monitor the temperature of up to two remote sensor diodes plus its own internal temperature. It can measure and control the speed of up to four fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. A unique dynamic TMIN control mode enables the system thermals/acoustics to be intelligently managed. The effectiveness of the system’s thermal solution can be monitored using the THERM input. The ADT7460 also provides critical thermal protection to the system by using the bidirectional THERM pin as an output to prevent system or component overheating. APPLICATIONS Low acoustic noise PCs Networking and telecommunications equipment FUNCTIONAL BLOCK DIAGRAM ADDR SELECT ADDR_EN SCL SMBUS ADDRESS SELECTION PWM1 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS SERIAL BUS INTERFACE ADDRESS POINTER REGISTER AUTOMATIC FAN SPEED CONTROL ACOUSTIC ENHANCEMENT CONTROL DYNAMIC TMIN CONTROL TACH1 TACH2 SDA SMBALERT PWM CONFIGURATION REGISTERS FAN SPEED COUNTER TACH3 TACH4 INTERRUPT MASKING PERFORMANCE MONITORING THERMAL PROTECTION THERM VCC INTERRUPT STATUS REGISTERS VCC TO ADT7460 ADT7460 D1+ INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER D2– +2.5VIN 10-BIT ADC LIMIT COMPARATORS BAND GAP REFERENCE BAND GAP TEMP SENSOR VALUE AND LIMIT REGISTERS 03228-001 D1– D2+ GND Figure 1. 1 Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADT7460 TABLE OF CONTENTS Specifications..................................................................................... 3 Additional ADC Functions for Voltage Measurements........ 17 Absolute Maximum Ratings............................................................ 5 Temperature Measurement System.......................................... 17 Thermal Characteristics .............................................................. 5 Additional ADC Functions for Temperature Measurement 19 ESD Caution.................................................................................. 5 Limits, Status Registers, and Interrupts................................... 20 Pin Configuration and Function Descriptions............................. 6 Status Registers ........................................................................... 21 Typical Performance Characteristics ............................................. 7 Handling SMBALERT Interrupts............................................. 22 Product Description......................................................................... 9 THERM Timer ........................................................................... 24 Measurement Inputs .................................................................... 9 Fan Drive Using PWM Control ............................................... 27 Sequential Measurement ............................................................. 9 Operating from 3.3 V Standby ................................................. 33 Recommended Implementation................................................. 9 XNOR Tree Test Mode .............................................................. 33 ADT7460 Address Selection ..................................................... 10 Power-On Default ...................................................................... 33 Internal Registers of the ADT7460 .......................................... 10 ADT7460 Register Summary........................................................ 34 Theory of Operation ...................................................................... 11 Outline Dimensions ....................................................................... 51 Serial Bus Interface..................................................................... 11 Ordering Guide .......................................................................... 51 Voltage Measurement Input...................................................... 15 REVISION HISTORY 3/05—Rev. B to Rev. C 6/03—Rev. 0 to Rev. A Updated Format.................................................................. Universal Changes to Absolute Maximum Ratings Table..............................5 Changes to ADT7460 Register Map Summary Section .............34 Updated Ordering Guide................................................................51 Updated ORDERING ............................................................................4 Updated the SERIAL BUS INTERFACE section................................9 Added the To Assign THERM Functionality to a Pin 9 section ....21 Added the THERM as an Input section.............................................21 Renamed the Therm Input section to THERM Timer ....................21 Renumbered the figures after Figure 25.............................................22 Updated Step 1 in the Configuring the Desired THERM Behavior section........................................................................................................2 Updated the Fan Speed Control section ............................................28 Added the POWER-ON DEFAULT section .....................................29 Updated Table IV ..................................................................................30 Updated Table XVIII ............................................................................38 Updated Table XX .................................................................................40 Updated Table XXXV ...........................................................................46 Updated OUTLINE DIMENSIONS ...................................................49 9/03—Rev. A to Rev. B Changed XOR Tree Test Mode to XNOR ............................ Universal Changes to SPECIFICATIONS............................................................. 2 Changes to TPC 7.................................................................................... 7 Rev. C | Page 2 of 52 ADT7460 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Table 1. Parameter1, 2, 3 POWER SUPPLY Supply Voltage Supply Current, ICC Min Typ4 Max Unit Test Conditions/Comments 3.0 5.0 5.5 3 20 V mA µA Interface inactive, ADC active Standby mode ±1.5 ±3 °C °C °C °C °C °C °C µA µA TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy 0.25 Resolution Remote Sensor Source Current 0.25 180 11 ±1.5 ±2.5 ±3 ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE Differential Nonlinearity, DNL Power Supply Sensitivity Conversion Time (Voltage Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Monitoring Cycle Time Input Resistance FAN RPM-TO-DIGITAL CONVERTER Accuracy ±1.5 ±1 80 13 13.50 28 134.50 15 200 ±7 ±11 ±13 65,535 Full-Scale Count Nominal Input RPM Internal Clock Frequency OPEN-DRAIN DIGITAL OUTPUTS, PWM1–PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis ±0.1 11.38 12.09 25.59 120.17 13.51 140 82.8 % LSB %/V ms ms ms ms ms kΩ 0°C ≤ TA ≤ 70°C −40°C ≤ TA ≤ +120°C 0°C ≤ TA ≤ 70°C; 0°C ≤ TD ≤ 120°C 0°C ≤ TA ≤ 105°C; 0°C ≤ TD ≤ 120°C 0°C ≤ TA ≤ 120°C; 0°C ≤ TD ≤ 120°C High level Low level 8 bits Averaging enabled Averaging enabled Averaging enabled Averaging enabled (incl. delay5) Averaging disabled % % % 0°C ≤ TA ≤ 70°C 0°C ≤ TA ≤ 105°C −40°C ≤ TA ≤ +120°C Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C 109 329 5000 10000 90.0 97.2 RPM RPM RPM RPM kHz 0.1 8.0 0.4 1 mA V µA IOUT = −8.0 mA, VCC = 3.3 V VOUT = VCC 0.1 0.4 1 V µA IOUT = −4.0 mA, VCC = 3.3 V VOUT = VCC 0.4 V V mV 2.0 500 Rev. C | Page 3 of 52 ADT7460 Parameter1, 2, 3 DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH Min Typ4 Max Unit 2.0 V V V V V p-p 5.5 +0.8 Input Low Voltage, VIL −0.3 Hysteresis DIGITAL INPUT LOGIC LEVELS (THERM) Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING6 Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Detect Clock Low Timeout, tTIMEOUT 0.5 1.7 Maximum input voltage Minimum input voltage V V 0.8 −1 +1 5 400 50 1.3 0.6 0.6 1.3 0.6 300 300 100 15 Test Conditions/Comments 35 µA µA pF VIN = VCC VIN = 0 kHz ns µs µs µs µs µs ns µs ns ms See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 Can be optionally disabled 1 All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN. 3 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a rising edge. 4 Typicals are at TA = 25°C and represent the most likely parametric norm. 5 The delay is the time between the round robin finishing one set of measurements and starting the next. 6 Guaranteed by design, not production tested. 2 tLOW tR tF tHD; STA SCL tHIGH tHD; DAT tSU; STA tSU; STO tSU; DAT SDA tBUF P S S Figure 2. Serial Bus Timing Diagram Rev. C | Page 4 of 52 P 03228-002 tHD; STA ADT7460 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Positive Supply Voltage (VCC) Voltage on Any Other Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature IR Reflow Peak Temperature for Pb Free Lead Temperature (Soldering 10 s) ESD Rating Rating 6.5 V −0.3 V to +6.5 V ±5 mA ±20 mA 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 220°C 260°C 300°C 1500 V 16-Lead QSOP Package: θJA = 150°C/W θJC = 39°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 52 ADT7460 SCL 1 16 SDA GND 2 15 PWM1/XTO 14 +2.5VIN/SMBALERT 13 D1+ 12 D1– TACH1 6 11 D2+ TACH2 7 10 D2– PWM3/ADDRESS ENABLE 8 9 TACH4/ADDRESS SELECT/THERM VCC 3 TACH3 4 ADT7460 PWM2/SMBALERT 5 (Not to Scale) TOP VIEW 03228-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 Mnemonic SCL GND VCC 4 TACH3 5 PWM2 SMBALERT 6 TACH1 7 TACH2 8 PWM3 ADDRESS ENABLE 9 TACH4 ADDRESS SELECT THERM 10 11 12 13 14 D2− D2+ D1− D1+ +2.5VIN SMBALERT 15 PWM1/XTO 16 SDA Description Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. Ground Pin for the ADT7460. Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also monitored through this pin. The ADT7460 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans. Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2 speed. Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans. Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/4 speed. Requires 10 kΩ typical pull-up. If pulled low on power-up, this places the ADT7460 into address select mode, and the state of Pin 9 determines the ADT7460’s slave address. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans. If in address select mode, this pin determines the SMBus device address. Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions. Cathode Connection to Second Thermal Diode. Anode Connection to Second Thermal Diode. Cathode Connection to First Thermal Diode. Anode Connection to First Thermal Diode. Analog Input. Monitors 2.5 V supply, typically a chipset voltage. Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up. Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up. Rev. C | Page 6 of 52 ADT7460 TYPICAL PERFORMANCE CHARACTERISTICS 3 DXP TO GND 5 0 –5 DXP TO VCC (3.3V) –10 –15 –20 10.0 30.0 3.3 LEAKAGE RESISTANCE (MΩ) 1 100.0 2 HIGH LIMIT 1 +3 SIGMA 0 –3 SIGMA –1 –2 –3 –40 60 10 TEMPERATURE (°C) 110 Figure 7. Local Temperature Error vs. Actual Temperature Figure 4. Remote Temperature Error vs. Leakage Resistance 3 LOW LIMIT 03228-007 LOCAL TEMPERATURE ERROR (°C) 10 03228-004 REMOTE TEMPERATURE ERROR (°C) 15 14 REMOTE TEMPERATURE ERROR (°C) –3 REMOTE TEMPERATURE ERROR (°C) REMOTE TEMPERATURE ERROR (°C) 0 –6  –9 –12 –15 –18 –21 –24 –27 –30 12 10 8 6 250mV 4 2 100mV 0 2.2 3.3 4.7 10.0 DXP–DXN CAPACITANCE (nF) 22.0 47.0 Figure 5. Remote Temperature Error vs. Capacitance between D+ and D− –2 100k LOCAL TEMPERATURE ERROR (°C) HIGH LIMIT +3 SIGMA 0 –3 SIGMA –1 LOW LIMIT –2 10 60 TEMPERATURE (°C) 110 03228-006 REMOTE TEMPERATURE ERROR (°C) 12.5 1 –3 –40 50M Figure 8. Remote Temperature Error vs. Power Supply Noise Frequency 3 2 550k 5M FREQUENCY (Hz) 10.0 7.5 250mV 5.0 2.5 100mV 0 –2.5 –5.0 100k 550k 5M FREQUENCY (Hz) 50M 03228-009 1 03228-008 –36 03228-005 –33 Figure 9. Local Temperature Error vs. Power Supply Noise Frequency Figure 6. Remote Temperature Error vs. Actual Temperature Rev. C | Page 7 of 52 ADT7460 40 1.85 35 REMOTE TEMPERATURE ERROR (°C) 1.90 1.75 1.70 1.65 1.60 1.55 1.50 1.45 100mV 30 25 20 15 10 40mV 5 0 20mV 2.6 2.5 3.0 3.4 3.8 4.2 4.6 5.0 SUPPLY VOLTAGE (V) 5.4 5.5 03228-010 –5 1.40 –10 10k 100k 1M FREQUENCY (Hz) 10M 03228-012 SUPPLY CURRENT (mA) 1.80 Figure 12. Remote Temperature Error vs. Common-Mode Noise Frequency Figure 10. Supply Current vs. Supply Voltage REMOTE TEMPERATURE ERROR (°C) 16 20mV 14 12 10 8 10mV 6 4 2 –2 60k 110k 1M FREQUENCY (Hz) 10M 50M 03228-011 0 Figure 11. Remote Temperature Error vs. Differential Mode Noise Frequency Rev. C | Page 8 of 52 ADT7460 PRODUCT DESCRIPTION SEQUENTIAL MEASUREMENT The ADT7460 is a thermal monitor and multiple fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial System Management Bus (SMBus). The serial bus controller has an optional address line for device selection (Pin 9), a serial data line for reading and writing addresses and data (Pin 16), and an input line for the serial clock (Pin 1). All control and programming functions of the ADT7460 are performed over the serial bus. In addition, two of the pins can be reconfigured as an SMBALERT output to indicate out-of-limit conditions. When the ADT7460 monitoring sequence is started, it cycles sequentially through the measurement of 2.5 V input and the temperature sensors. Measured values from these inputs are stored in value registers. These can be read out over the serial bus or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions. RECOMMENDED IMPLEMENTATION MEASUREMENT INPUTS Configuring the ADT7460 as in Figure 13 allows the systems designer the following features: The device has three measurement inputs, one for voltage and two for temperature. It can also measure its own supply voltage and can measure ambient temperature with its on-chip temperature sensor. • Two PWM outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). • Three TACH fan speed measurement inputs. • VCC measured internally through Pin 3. Power is supplied to the chip via Pin 3, and the system also monitors VCC through this pin. In PCs, this pin is normally connected to a 3.3 V standby supply. This pin can, however, be connected to a 5 V supply and monitor it without overranging. • CPU temperature measured using Remote 1 temperature channel. • Ambient temperature measured through Remote 2 temperature channel. Remote temperature sensing is provided by the D1± and D2± inputs, to which diode-connected, external temperature-sensing transistors, such as a 2N3904 or CPU thermal diode, may be connected. • Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT monitoring and can function as an overtemperature THERM output. • SMBALERT system interrupt output. Pin 14 is an analog input with an on-chip attenuator and is configured to monitor 2.5 V. The ADC also accepts input from an on-chip band gap temperature sensor, which monitors system ambient temperature. FRONT CHASSIS FAN ADT7460 TACH2 PWM1 TACH1 REAR CHASSIS FAN PWM3 TACH3 D2+ D2– THERM PROCHOT D1+ D1– SDA SCL SMBALERT GND Figure 13. Recommended Implementation Rev. C | Page 9 of 52 ICH 3228-013 AMBIENT TEMPERATURE ADT7460 ADT7460 ADDRESS SELECTION INTERNAL REGISTERS OF THE ADT7460 Pin 8 is the dual-function PWM3/ADDRESS ENABLE pin. If Pin 8 is pulled low on power-up, the ADT7460 reads the state of Pin 9 (TACH4/ADDRESS SELECT/THERM) to determine the ADT7460’s slave address. If Pin 8 is high on power-up, the ADT7460 defaults to SMBus Slave Address 0x2E. This function is described in more detail later. Table 4 summarizes the ADT7460’s principal internal registers. Table 41 to Table 81 describe the registers in more detail. Table 4. Summary Internal Registers Register Configuration Address Pointer Status Registers Interrupt Mask Value and Limit Offset TMIN TRANGE Operating Point Enhance Acoustics Description These registers provide control and configuration of the ADT7460, including alternate pinout functionality. This register contains the address that selects one of the other internal registers. When writing to the ADT7460, the first byte of data is always a register address, which is written to the address pointer register. These registers provide the status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. If Pin 14 or Pin 5 is configured as SMBALERT, this pin asserts low whenever an unmasked status bit is set. These registers allow each interrupt status event to be masked when Pin 14 or Pin 5 is configured as an SMBALERT output. The results of analog voltage input, temperature, and fan speed measurements are stored in these registers, along with their limit values. These registers allow each temperature channel reading to be offset by a twos complement value written to these registers. These registers program the starting temperature for each fan under automatic fan speed control. These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each PWM output. These registers define the target operating temperatures for each thermal zone when running under dynamic TMIN control. This function allows the cooling solution to adjust dynamically in response to measured temperature and system performance. These registers allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics. Rev. C | Page 10 of 52 ADT7460 THEORY OF OPERATION SERIAL BUS INTERFACE Control of the ADT7460 is carried out using the serial System Management Bus (SMBus). The ADT7460 is connected to this bus as a slave device, under the control of a master controller. VCC ADT7460 PWM3/ADDR_EN ADDRESS = 0x2D Figure 16. SMBus Address 0x2D (Pin 9 = 1) VCC ADT7460 The device address is sampled and latched on the first valid SMBus transaction, more precisely, on the low-to-high transition at the beginning of the eighth SCL pulse, when the serial address byte matches the selected slave address. The selected slave address is chosen using the ADDRESS ENABLE /ADDRESS SELECT pins. Any attempted changes in the address has no effect after this. ADDR_SEL NC DO NOT LEAVE ADDR_EN UNCONNECTED. CAN CAUSE UNPREDICTABLE ADDRESSES CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8 (PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8 FLOATING COULD CAUSE THE ADT7460 TO POWER UP WITH AN UNEXPECTED ADDRESS. NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS SELECT MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME. Address 0101100 (0x2C) 0101101 (0x2D) 0101110 (0x2E) (default) 03228-017 Pin 9 State Low (10 kΩ to GND) High (10 kΩ pull-up) Don’t Care 10kΩ 9 8 PWM3/ADDR_EN Table 5. Address Select Mode Figure 17. Unpredictable SMBus Address if Pin 8 is Unconnected 9 10kΩ 8 PWM3/ADDR_EN ADDRESS = 0x2E 03228-014 ADDR_SEL The facility to make hardwired changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADT7460 is used in a system. VCC ADT7460 The serial bus protocol operates as follows: 1. Figure 14. Default SMBus Address 0x2E ADT7460 ADDR_SEL PWM3/ADDR_EN 9 10kΩ 8 ADDRESS = 0x2C 03228-015 Pin 8 State 0 0 1 8 03228-016 ADDR_SEL The ADT7460 has a 7-bit serial bus address. When the device is powered up with Pin 8 (PWM3/ADDRESS ENABLE) high, the ADT7460 has a default SMBus address of 0101110 or 0x2E. If more than one ADT7460 is to be used in a system, each ADT7460 should be placed in address select mode by strapping Pin 8 low on power-up. The logic state of Pin 9 then determines the device’s SMBus address. The logic state of these pins is sampled on power-up. 10kΩ 9 The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the star condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determine the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Figure 15. SMBus Address 0x2C (Pin 9 = 0) Rev. C | Page 11 of 52 ADT7460 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADT7460, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written in that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. This is illustrated in Figure 18. The device address is sent over the bus followed by R/W being set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at 1 9 9 1 SCL 0 1 0 1 1 A1 A0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE D7 R/W D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7460 ACK. BY ADT7460 FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 FRAME 3 DATA BYTE D2 D1 D0 ACK. BY ADT7460 Figure 18. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register Rev. C | Page 12 of 52 STOP BY MASTER 03228-018 SDA ADT7460 If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. When reading data from a register, there are two possibilities: If the ADT7460’s address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7460 as before, but only the data byte containing the register address is sent because data is not to be written to the register. This is shown in Figure 19. Write Operations The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7460 are discussed below. The following abbreviations are used in the diagrams: S—start P—stop R—read W—write A—acknowledge A—no acknowledge A read operation is then performed, consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 20. If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so Figure 19 can be omitted. The ADT7460 uses the following SMBus write protocols: Send Byte It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. In this operation, the master device sends a single command byte to a slave device as follows: In Figure 18 to Figure 20, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are set by the address select mode function previously defined. In addition to supporting the Send Byte and Receive Byte protocols, the ADT7460 also supports the Read Byte protocol (see System Management Bus specifications Rev. 2.0 for more information). 1 9 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. 9 1 SCL SDA 0 1 START BY MASTER 0 1 1 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7460 FRAME 1 SERIAL BUS ADDRESS BYTE ACK. BY ADT7460 STOP BY MASTER FRAME 2 ADDRESS POINTER REGISTER BYTE 03228-019 • Figure 19. Writing to the Address Pointer Register Only 1 9 9 1 SCL SDA START BY MASTER 0 1 0 1 1 A1 FRAME 1 SERIAL BUS ADDRESS BYTE A0 R/ W D7 D6 D5 D4 D3 D2 D1 ACK. BY ADT7460 NO ACK. BY STOP BY MASTER MASTER FRAME 2 DATA BYTE FROM ADT7460 Figure 20. Reading Data from a Previously Selected Register Rev. C | Page 13 of 52 D0 03228-020 • ADT7460 1 S 2 3 SLAVE W A ADDRESS 4 5 6 REGISTER ADDRESS A P 03228-021 For the ADT7460, the send byte protocol is used to write to the address pointer register for a subsequent single-byte read from the same address. This is illustrated in Figure 21. 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. Figure 21. Setting a Register Address for Subsequent Read In the ADT7460, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or by write byte operation. 1 2 3 4 5 6 SLAVE REGISTER S W A A P ADDRESS ADDRESS Write Byte 03228-023 If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition. Figure 23. Single-Byte Read from a Register In this operation, the master device sends a command byte and one data byte to the slave device as follows: Alert Response Address 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. 5. The slave asserts ACK on SDA. The SMBALERT output can be used as an interrupt output or can be used as an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following occurs: 6. The master sends a data byte. 1. SMBALERT is pulled low. 7. The slave asserts ACK on SDA. 2. 8. The master asserts a stop condition on SDA to end the transaction. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address, which must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known, and it can be interrogated in the usual way. 4. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the ADT7460 has responded to the alert response address, the master must read the status registers and the SMBALERT is cleared only if the error condition has gone away. This is illustrated in Figure 22. S 2 3 SLAVE W A ADDRESS 4 REGISTER ADDRESS 5 6 7 8 A DATA A P 03228-022 1 Figure 22. Single-Byte Write to a Register Read Operations The ADT7460 uses the following SMBus read protocols. Receive Byte This is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). Rev. C | Page 14 of 52 ADT7460 SMBus Timeout Input Circuitry The ADT7460 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7460 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. The internal structure for the 2.5 V analog input is shown in Figure 24. The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives the input immunity to high frequency noise. Table 6. Configuration Register 1 (Reg. 0x40) Register 0x20 0x22 Description 0: SMBus timeout enabled (default) 1: SMBus timeout disabled VOLTAGE MEASUREMENT INPUT The ADT7460 has one external voltage measurement channel. It can also measure its own supply voltage, VCC. Pin 14 may be configured to measure a 2.5 V supply. The VCC supply voltage measurement is carried out through the VCC pin (Pin 3). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADT7460 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. Description 2.5 V reading VCC reading Associated with the voltage measurement channels are a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Table 8. 2.5 V Limit Registers Register 0x44 0x45 0x48 0x49 Description 2.5 V low limit 2.5 V high limit VCC low limit VCC high limit 2.5VIN Analog-to-Digital Converter All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the input has built-in attenuators to allow measurement of 2.5 V without any external components. To allow the tolerance of the supply voltage, the ADC produces an output of 3/4 full scale (768d or 0x300) for the nominal input voltage and so has adequate headroom to deal with overvoltages. Default 0x00 0x00 Default 0x00 0xFF 0x00 0xFF 45kΩ 94kΩ 30pF 03228-024 Bit TODIS TODIS Table 7. Voltage Measurement Registers Figure 24. Structure of Analog Inputs Table 9 shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 711 µs and averages 16 conversions to reduce noise; a measurement takes nominally 11.38 ms. Rev. C | Page 15 of 52 ADT7460 Table 9. 10-Bit A/D Output Code vs. VIN 5 VIN 6.6634 1 Input Voltage VCC (3.3 VIN)1 4.3957 2.5 VIN 3.3267 Decimal 0 1 2 3 4 5 6 7 8 • • • 256 (1/4 scale) • • • 512 (1/2 scale) • • • 768 (3/4 scale) • • • 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 A/D Output Binary (10 Bits) 00000000 00 00000000 01 00000000 10 00000000 11 00000001 00 00000001 01 00000001 10 00000001 11 00000010 00 • • • 01000000 00 • • • 10000000 00 • • • 11000000 00 • • • 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 11111111 11 The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), the VCC output codes are the same as for the 5 VIN column. Rev. C | Page 16 of 52 ADT7460 ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS TEMPERATURE MEASUREMENT SYSTEM A number of other functions are available on the ADT7460 to offer the systems designer increased flexibility. The ADT7460 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). As both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table 12. Theoretically, the temperature sensor and ADC can measure temperatures from −128°C to +127°C with a resolution of 0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside this range are not possible. Local Temperature Measurement Turn-Off Averaging For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. If the user wants to speed up conversion, setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This effectively gives a reading 16 times faster (711 µs), but the reading may be noisier. Bypass Voltage Input Attenuator Remote Temperature Measurement Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes the attenuation circuitry from the 2.5 V input. This allows the user to directly connect external sensors or to rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V. The ADT7460 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pins 12 and 13, or Pins 10 and 11. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about −2 mV/°C. Unfortunately, the absolute value of VBE varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADT7460 is to measure the change in VBE when the device is operated at two different currents. This is given by Single-Channel ADC Conversion Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7460 into single-channel ADC conversion mode. In this mode, the ADT7460 can be made to read a single voltage channel only. If the internal ADT7460 clock is used, the selected input is read every 711 µs. The appropriate ADC channel is selected by writing to Bits of the TACH1 Minimum High Byte register (Reg. 0x55). ∆ VBE = KT q × In(N ) Table 10. Configuration Register 2 (Reg. 0x73) where: Description 1: averaging off 1: bypass input attenuators 1: single-channel convert mode K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in Kelvins. N is the ratio of the two currents. Table 11. TACH1 Minimum High Byte (Reg. 0x55) Bit Figure 25 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors. It could equally well be a discrete transistor, such as a 2N3904. Description Selects ADC channel for single-channel convert mode Value Channel Selected 000 2.5 V 010 VCC I N × I IBIAS VDD CPU REMOTE SENSING TRANSISTOR THERMDA D+ THERMDC D– VOUT+ BIAS DIODE LPF fC = 65kHz Figure 25. Signal Conditioning for Remote Diode Temperature Sensors Rev. C | Page 17 of 52 TO ADC VOUT– 03228-025 Bit ADT7460 If a discrete transistor is used, the collector is not grounded, and it should be linked to the base. If a PNP transistor is used, the base is connected to the D− input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D− input, and the base to the D+ input. Figure 26 and Figure 27 show how to connect the ADT7460 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input. To measure ΔVBE, the sensor is switched between operating currents of I and N × I. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise and to a chopper stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to ΔVBE. This voltage is measured by the ADC to give a temperature output in 10-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 25.5 ms. The results of remote temperature measurements are stored in 10-bit, twos complement format, as illustrated in Table 12. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (Reg. 0x77). This gives temperature readings with a resolution of 0.25°C. Table 12. Temperature Data Format Digital Output (10-Bit)1 1000 0000 00 1000 0011 00 1001 1100 00 1011 0101 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 Temperature −128°C −125°C −100°C −75°C −50°C −25°C −10°C 0°C +10.25°C +25.5°C +50.75°C +75°C +100°C +125°C +127°C 1 Bold denotes 2 LSBs of measurement in the Extended Resolution Register 2 (Reg. 0x77) with 0.25°C resolution. Table 13. Temperature Measurement Registers Register 0x25 0x26 0x27 0x77 Description Remote 1 temperature Local temperature Remote 2 temperature Extended Resolution 2 Default 0x80 0x80 0x80 0x00 ADT7460 Table 14. Extended Resolution Temperature Measurement Register Bits (Addr = 0x77) D+ D– 03228-026 2N3904 NPN Figure 26. Measuring Temperature by Using an NPN Transistor Bit Mnemonic TDM2 LTMP TDM1 Description Remote 2 temperature LSBs Local temperature LSBs Remote 1 temperature LSBs ADT7460 Reading Temperature from the ADT7460 D+ D– 03228-027 2N3906 PNP Figure 27. Measuring Temperature by Using a PNP Transistor It is important to note that temperature can be read from the ADT7460 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25 C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order. If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (Reg. 0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read, and vice versa. Rev. C | Page 18 of 52 ADT7460 Nulling Out Temperature Errors Table 15. Temperature Offset Registers Register 0x70 0x71 0x72 Description Remote 1 temperature offset Local temperature offset Remote 2 temperature offset Default 0x00 (0°C) 0x00 (0°C) 0x00 (0°C) Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Table 16. Temperature Measurement Limit Registers Description Remote 1 temperature low limit Remote 1 temperature high limit Local temperature low limit Local temperature high limit Remote 2 temperature low limit Remote 2 temperature high limit HYSTERESIS = (°C) TEMPERATURE 100% FANS Figure 28. THERM Limit Operation ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT A number of other functions are available on the ADT7460 to offer the systems designer increased flexibility: Turn-Off Averaging For each temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. Sometimes it may be necessary to take a very fast measurement, for example, of CPU temperature. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This takes a reading every 15.5 ms. Each remote temperature measurement takes 4 ms and the local temperature measurement takes 1.4 ms. Single-Channel ADC Conversions Temperature Measurement Limit Registers Register 0x4E 0x4F 0x50 0x51 0x52 0x53 THERM LIMIT 03228-028 As CPUs run faster, it becomes more difficult to avoid high frequency clocks when routing the D+, D− traces around a system board. Even when recommended layout guidelines are followed, there may still be temperature errors attributed to noise being coupled onto the D+/D− lines. High frequency noise generally has the effect of giving temperature measurements that are too high by a constant amount. The ADT7460 has temperature offset registers at Addresses 0x70, 0x72 for the Remote 1 and Remote 2 temperature channels. By doing a onetime calibration of the system, one can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The LSB adds 0.25°C offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to ±32°C with a resolution of 0.25°C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Default 0x81 0x7F 0x81 0x7F 0x81 0x7F Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7460 into single-channel ADC conversion mode. In this mode, the ADT7460 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits of the TACH1 minimum high byte register (Reg. 0x55). Table 17. Configuration Register 2 (Reg. 0x73) Bit Table 18. TACH1 Minimum High Byte (Reg. 0x55) Bit Overtemperature Events Description 1: Averaging off 1: single-channel convert mode Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Registers 0x6A to 0x6C are the THERM limits. When a temperature exceeds its THERM limit, all fans run at 100% duty cycle. The fans continue running at 100% until the temperature drops below THERM – Hysteresis. (This can be disabled by setting the BOOST bit in Configuration Register 3, Bit 2, Register 0x78). The hysteresis value for that THERM limit is the value programmed into Registers 0x6D and 0x6E (hysteresis registers). The default hysteresis value is 4°C. Rev. C | Page 19 of 52 Description Selects ADC channel for single-channel convert mode Value Channel Selected 101 Remote 1 temp 110 Local temp 111 Remote 2 temp ADT7460 LIMITS, STATUS REGISTERS, AND INTERRUPTS Out-of-Limit Comparisons Limit Values Once all limits have been programmed, the ADT7460 can be enabled for monitoring. The ADT7460 measures all parameters in round-robin format and sets the appropriate status bit for out-of-limit conditions. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit. Associated with each measurement channel on the ADT7460 are high and low limits. These can form the basis of system status monitoring: a status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. 8-Bit Limits The following is a list of 8-bit limits on the ADT7460. • High limit: > comparison performed • Low limit: < or = comparison performed Table 19. Voltage Limit Registers Register 0x44 0x45 0x48 0x49 Description 2.5 V low limit 2.5 V high limit VCC low limit VCC high limit Default 0x00 0xFF 0x00 0xFF NO INT Table 20. Temperature Limit Registers 0x6A 0x50 0x51 0x6B 0x52 0x53 0x6C Description Remote 1 temperature low limit Remote 1 temperature high limit Remote 1 THERM limit Local temperature low limit Local temperature high limit Local THERM limit Remote 2 temperature low limit Remote 2 temperature high limit Remote 2 THERM limit Default 0x81 0x7F LOW LIMIT 0x64 0x81 0x7F 0x64 0x81 0x7F TEMP > LOW LIMIT 03228-029 Register 0x4E 0x4F Figure 29. Temperature > Low Limit: No INT 0x64 Table 21. THERM Timer Limit Register Register 0x7A Description THERM timer limit Default 0x00 INT 16-Bit Limits The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Since fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan TACHs. Since fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan. LOW LIMIT Register 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B Description TACH1 minimum low byte TACH1 minimum high byte TACH2 minimum low byte TACH2 minimum high byte TACH3 minimum low byte TACH3 minimum high byte TACH4 minimum low byte TACH4 minimum high byte Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Rev. C | Page 20 of 52 TEMP = LOW LIMIT Figure 30. Temperature = Low Limit: INT Occurs 03228-030 Table 22. Fan Limit Registers ADT7460 The total number of channels measured is NO INT • Two supply voltage inputs (2.5 V and VCC) • Local temperature • Two remote temperatures As mentioned previously, the ADC performs round-robin conversions and takes 11.38 ms for each voltage measurement, 12 ms for a local temperature reading, and 25.5 ms for each remote temperature reading. HIGH LIMIT The total monitoring cycle time for averaged voltage and temperature monitoring is, therefore, nominally (2 × 11.38) + 12 (2 × 25.5) = 85.76 ms 03228-031 TEMP = HIGH LIMIT The round robin starts again 35 ms later. Therefore, all channels are measured approximately every 120 ms. Figure 31. Temperature = High Limit: No INT Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. STATUS REGISTERS INT The results of limit comparisons are stored in Status Registers 1 and 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limits, the corresponding status register bit is set to 1. Figure 32. Temperature > High Limit: INT Occurs Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. As the ADC is normally allowed to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, since the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The state of the various measurement channels may be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Status Register 1 (Reg. 0x41), 1 means that an out-oflimit event has been flagged in Status Register 2. This means that you need only read Status Register 2 when this bit is set. Alternatively, Pin 5 or Pin 14 can be configured as an SMBALERT output. This automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are “sticky.” Whenever a status bit is set, indicating an outof-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone away. Interrupt status mask registers (Reg. 0x74, 0x75) allow individual interrupt sources to be masked from causing an SMBALERT. However, if one of these masked interrupt sources goes out-oflimit, its associated status bit is set in the interrupt status registers. OOL = 1 DENOTES A PARAMETER MONITORED THROUGH STATUS REG 2 IS OUT-OF-LIMIT Figure 33. Status Register 1 Rev. C | Page 21 of 52 03228-033 TEMP > HIGH LIMIT 03228-032 HIGH LIMIT ADT7460 Table 23. Status Register 1 (Reg. 0x41) SMBALERT Interrupt Behavior Bit 7 Mnemonic OOL 6 R2T The ADT7460 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. 5 LT 4 R1T 3 2 VCC 1 0 2.5 V Description 1 denotes a bit in Status Register 2 is set and Status Register 2 should be read. 1 indicates that the Remote 2 temperature high or low limit has been exceeded. 1 indicates that the Local temperature high or low limit has been exceeded. 1 indicates that the Remote 1 temperature high or low limit has been exceeded. Unused 1 indicates that the VCC high or low limit has been exceeded. Unused 1 indicates that the 2.5 V high or low limit has been exceeded. Figure 35 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky since they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. Note that the SMBALERT output remains low for the entire duration that a reading is outof-limit and until the status register has been read. This has implications on how software handles the interrupt. HIGH LIMIT F4P = 1, FAN 4 OR THERM TIMER IS OUT-OF-LIMIT 03228-034 TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) “STICKY” STATUS BIT Figure 34. Status Register 2 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) 03228-035 SMBALERT Table 24. Status Register 2 (Reg. 0x42) Bit 7 Mnemonic D2 6 D1 5 F4P 4 FAN3 3 FAN2 2 FAN1 1 OVT 0 - Description 1 indicates an open or short on D2+/D2− inputs. 1 indicates an open or short on D2+/D2− inputs. 1 indicates that Fan 4 has dropped below minimum speed. Alternatively, indicates that THERM timer limit has been exceeded if the THERM timer function is used. 1 indicates that Fan 3 has dropped below minimum speed. 1 indicates that Fan 2 has dropped below minimum speed. 1 indicates that Fan 1 has dropped below minimum speed. 1 indicates that a THERM overtemperature limit has been exceeded. Unused Figure 35. SMBALERT and Status Bit Behavior HANDLING SMBALERT INTERRUPTS To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: 1. Detect the SMBALERT assertion. 2. Enter the interrupt handler. 3. Read the status registers to identify the interrupt source. 4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (Reg. 0x74, 0x75). 5. Take the appropriate action for a given interrupt source. 6. Exit the interrupt handler. 7. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 36. Rev. C | Page 22 of 52 ADT7460 Enabling the SMBALERT Interrupt Output HIGH LIMIT The SMBALERT interrupt function is disabled by default. Pin 5 or Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. TEMPERATURE Table 27. Config Register 4 (Reg. 0x7D) CLEARED ON READ (TEMP BELOW LIMIT) “STICKY” STATUS BIT Pin No. 14 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) Table 28. Config Register 3 (Reg. 0x78) INTERRUPT MASK BIT CLEARED (SMBALERT REARMED) Figure 36. How Masking the Interrupt Source Affects SMBALERT Output Masking Interrupt Sources Interrupt Mask Registers 1 and 2 are located at Addresses 0x74 and 0x75. These allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set as normal. Table 25. Interrupt Mask Register 1 (Reg. 0x74) Bit 7 Mnemonic OOL 6 R2T 5 4 LT R1T 3 2 1 0 VCC 2.5 V Description 1 masks SMBALERT for any alert condition flagged in Status Register 2. 1 masks SMBALERT for Remote 2 temperature. 1 masks SMBALERT for local temperature. 1 masks SMBALERT for Remote 1 temperature. Unused 1 masks SMBALERT for the VCC channel. Unused 1 masks SMBALERT for the 2.5 V channel. Table 26. Interrupt Mask Register 2 (Reg. 0x75) Bit 7 6 5 Mnemonic D2 D1 FAN4 4 3 2 1 FAN3 FAN2 FAN1 OVT 0 - Description 1 masks SMBALERT for Diode 2 errors. 1 masks SMBALERT for Diode 1 errors. 1 masks SMBALERT for Fan 4 failure. If the TACH4 pin is being used as the THERM input, this bit masks SMBALERT for a THERM event. 1 masks SMBALERT for Fan 3. 1 masks SMBALERT for Fan 2. 1 masks SMBALERT for Fan 1. 1 masks SMBALERT for overtemperature (exceeding THERM limits). Unused Pin No. 5 Bit Setting ALERT = 1 To Assign THERM Functionality to Pin 9 Pin 9 can be configured as the THERM pin on the ADT7460. To configure Pin 9 as the THERM pin, set the THERM ENABLE Bit (Bit 1) in Configuration Register 3 (Address 0x78) = 1. THERM as an Input When configured as an input, the THERM pin allows the user to time assertions on the pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. For more information on timing THERM assertions and generating SMBALERTs based on THERM, see the Generating Interrupts from Events section. The user can also set up the ADT7460 so when the THERM pin is driven low externally, the fans run at 100%. The fans run at 100% while the THERM pin is pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (Address 0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00 or in automatic mode when the temperature is above TMIN. If the temperature is below TMIN or if the duty cycle in manual mode is set to 0x00, pulling THERM low externally has no effect. See Figure 37 for more information. TMIN THERM THERM ASSERTED TO LOW AS AN INPUT. FANS DO NOT GO TO 100% SINCE TEMPERATURE IS BELOW TMIN. THERM ASSERTED TO LOW AS AN INPUT. FANS GO TO 100% SINCE TEMPERATURE IS ABOVE TMIN AND FANS ARE ALREADY RUNNING. Figure 37. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode Rev. C | Page 23 of 52 03228-037 INTERRUPT MASK BIT SET 03228-036 SMBALERT Bit Setting AL2.5V = 1 ADT7460 THERM TIMER When using the THERM timer, be aware of the following: The ADT7460 has an internal timer to measure THERM assertion time. For example, the THERM input may be connected to the PROCHOT output of a Pentium 4 CPU and measure system performance. The THERM input may also be connected to the output of a trip point temperature sensor. After a THERM timer read (Reg. 0x79) The timer is started on the assertion of the ADT7460’s THERM input and stopped on the negation of the pin. The timer counts THERM times cumulatively, therefore, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared on read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. If the THERM timer is read during a THERM assertion The 8-bit THERM timer register (Reg. 0x79) is designed such that Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time exceeds 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 becomes the LSB of the timer with a resolution of 22.76 ms. Figure 38 illustrates how the THERM timer behaves as the THERM input is asserted and negated. Bit 0 is set on the first THERM assertion detected. This bit remains set until the cumulative THERM assertions exceed 45.52 ms. At this time, Bit 1 of the THERM timer is set, and Bit 0 is cleared. Bit 0 now reflects timer readings with a resolution of 22.76 ms. THERM THERM TIMER (REG. 0x79) 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED ≤ 22.76ms The contents of the timer is cleared on read. • The F4P bit (Bit 5) of Status Register 2 needs to be cleared (assuming the THERM limit has been exceeded). • The contents of the timer are cleared. • Bit 0 of the THERM timer is set to 1 (since a THERM assertion is occurring). • The THERM timer increments from 0. • If the THERM limit (Reg. 0x7A) = 0x00, the F4P bit is set. Generating SMBALERT Interrupts from THERM Events The ADT7460 can generate SMBALERTs when a programmable THERM limit has been exceeded. This allows the systems designer to ignore brief, infrequent THERM assertions while capturing longer THERM events. Register 0x7A is the THERM limit register. This 8-bit register allows a limit from 0 seconds (first THERM assertion) to 5.825 seconds to be set before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM limit register. If the THERM timer value exceeds the THERM limit value, the F4P bit (Bit 5) of Status Register 2 is set and an SMBALERT is generated. Note that the F4P bit (Bit 5) of Mask Register 2 (Reg. 0x75) masks out SMBALERTs if this bit is set to 1, although the F4P bit of Interrupt Status Register 2 is still set if the THERM limit is exceeded. Figure 39 is a functional block diagram of the THERM timer, limit, and associated circuitry. Writing 0x00 to the THERM limit register (Reg. 0x7A) causes SMBALERT to be generated on the first THERM assertion. A THERM limit of 0x01 generates an SMBALERT once cumulative THERM assertions exceed 45.52 ms. THERM ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) • 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 45.52ms THERM THERM TIMER (REG. 0x79) 0 0 0 0 0 1 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms (91.04ms + 22.76ms) 03228-038 ACCUMULATE THERM LOW ASSERTION TIMES Figure 38. Understanding the THERM Timer Rev. C | Page 24 of 52 ADT7460 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 THERM THERM TIMER CLEARED ON READ COMPARATOR IN OUT F4P BIT (BIT 5) STATUS REGISTER 2 SMBALERT LATCH RESET CLEARED ON READ 1 = MASK F4P BIT (BIT 5) MASK REGISTER 2 (REG. 0x75) Figure 39. Functional Diagram of ADT7460’s THERM Monitoring Circuitry Rev. C | Page 25 of 52 03228-039 THERM LIMIT (REG. 0x7A) 2.914s 1.457s 728.32ms 364.16ms THERM TIMER (REG. 0x79) 182.08ms 91.04ms 45.52ms 22.76ms 2.914s 1.457s 728.32ms 364.16ms 182.08ms 91.04ms 45.52ms 22.76ms ADT7460 Configuring the Desired THERM Behavior Configuring the ADT7460 THERM Pin as an Output 1. Configure the THERM input. Setting Bit 1 (THERM ENABLE) of Configuration Register 3 (Reg. 0x78) enables the THERM monitoring function. 2. Select the desired fan behavior for THERM events. Setting Bit 2 (BOOST bit) of Configuration Register 3 (Reg. 0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit = 0, the fans run at their current settings and are not affected by THERM events. In addition to the ADT7460 being able to monitor THERM as an input, the ADT7460 can optionally drive THERM low as an output. The user can preprogram system critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Since the temperature for that channel is measured only every monitoring cycle, once THERM asserts, it is guaranteed to remain low for at least one monitoring cycle. 3. Select whether THERM events should generate SMBALERT interrupts. Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks out SMBALERTs when the THERM limit value is exceeded. This bit should be cleared if SMBALERTs based on THERM events are required. 4. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated on the first THERM assertion, or only if a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated on the first THERM assertion. Select a THERM monitoring time. This is how often OS or BIOS level software checks the THERM timer. For example, BIOS could read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is 182.08 ms in Hour 2, and >5.825 s in Hour 3, this can indicate that system performance is degrading significantly since THERM is asserting more frequently on an hourly basis. THERM LIMIT 0.25°C THERM LIMIT TEMP THERM ADT7460 MONITORING CYCLE 03228-040 5. The THERM pin can be configured to assert low if the Remote 1, local, or Remote 2 temperature THERM limits are exceeded by 0.25°C. The THERM limit registers are at Locations 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of Registers 0x5F, 0x60, and 0x61 enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 40 shows how the THERM pin asserts low as an output in the event of a critical overtemperature. Figure 40. Asserting THERM as an Output, Based on Tripping THERM Limits Alternatively, OS or BIOS level software can time-stamp when the system is powered on. If an SMBALERT is generated due to the THERM limit being exceeded, another time-stamp can be taken. The difference in time can be calculated for a fixed THERM limit time. For example, if it takes one week for a THERM limit of 2.914 s to be exceeded and the next time it takes only one hour, this indicates a serious degradation in system performance. Rev. C | Page 26 of 52 ADT7460 The ADT7460 uses pulse width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. A single NMOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven. Typical notebook fans draw a nominal 170 mA, so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If the user drives several fans in parallel from a single PWM output or drives larger server fans, the MOSFET needs to handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM_OUT pin. VGS can be greater than 3.3 V as long as the pull-up on the gate is tied to 5 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET. This would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. TACH/AIN 4.7kΩ 3.3V TACH 12V 12V FAN 1N4148 ADT7460 10kΩ Q1 NDT3055L 12V 10kΩ TACH/AIN 10kΩ 4.7kΩ 3.3V 12V FAN TACH 1N4148 ADT7460 470Ω PWM Q1 MMBT2222 Figure 42. Driving a 3-Wire Fan by Using an NPN Transistor Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 8 mA maximum current specified on the data sheet. 03228-041 PWM 12V Note that the ADT7460 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 43 shows how to drive two fans in parallel using low cost NPN transistors. Figure 44 is the equivalent circuit using the NDT3055L MOSFET. Note that since the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. 10kΩ 10kΩ Ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. Driving Two Fans from PWM3 Figure 41 shows how a 3-wire fan can be driven using PWM control. 12V Figure 42 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on-resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan’s current requirements. 03228-042 FAN DRIVE USING PWM CONTROL Figure 41. Driving a 3-Wire Fan by Using an N-Channel MOSFET Figure 41 uses a 10 kΩ pull-up resistor for the TACH signal. This assumes that the TACH signal is open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 5 V maximum to prevent damaging the ADT7460. If in doubt as to whether the fan used has an open-collector or totem pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section. Driving Up to Three Fans from PWM2 TACH measurements for fans are synchronized to particular PWM channels, for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same as shown in Figure 42, Figure 43, and Figure 44. The SYNC bit in Register 0x62 enables this function. Rev. C | Page 27 of 52 ADT7460 12V 3.3V 3.3V 1N4148 ADT7460 TACH3 1kΩ PWM3 TACH4 Q1 MMBT3904 2.2kΩ 10Ω Q2 MMBT2222 03228-043 10Ω Q3 MMBT2222 Figure 43. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors 3.3V 10kΩ TYPICAL TACH4 +V 3.3V ADT7460 +V 10kΩ TYPICAL TACH3 3.3V 5V OR 12V FAN TACH 1N4148 5V OR 12V FAN TACH 10kΩ TYPICAL 03228-044 Q1 NDT3055L PWM3 Figure 44. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET Table 29. SYNC : Enhance Acoustics Register 1 (Reg. 0x62) Mnemonic SYNC Description 1 synchronizes TACH2, TACH3, and TACH4 to PWM3. Driving 2-Wire Fans fan and the fan spins faster. Figure 46 shows a typical plot of the sensing waveform at a TACH/AIN pin. The most important thing is that the voltage spikes (either negative going or positive going) are more than 40 mV in amplitude. This allows fan speed to be reliably determined. +V Figure 45 shows how a 2-wire fan may be connected to the ADT7460. This circuit allows the speed of a 2-wire fan to be measured, even though the fan has no dedicated TACH signal. A series resistor, RSENSE, in the fan circuit converts the fan commutation pulses into a voltage. This is ac-coupled into the ADT7460 through the 0.01 µF capacitor. On-chip signal conditioning allows accurate monitoring of fan speed. The value of RSENSE chosen depends on the programmed input threshold and on the current drawn by the fan. For fans drawing approximately 200 mA, a 2 Ω RSENSE value is suitable when the threshold is programmed as 40 mV. For fans that draw more current, such as larger desktop or server fans, RSENSE may be reduced for the same programmed threshold. The smaller the threshold programmed the better, since more voltage is developed across the Rev. C | Page 28 of 52 ADT7460 3.3V 1N4148 5V OR 12V FAN 10kΩ TYPICAL Q1 NDT3055L PWM 0.01µF TACH/AIN RSENSE 2Ω TYPICAL Figure 45. Driving a 2-Wire Fan 03228-045 Bit ADT7460 If the fan TACH output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 48. ∆: 250 mV @: –258mV VCC 12V PULL-UP 4.7kΩ TYPICAL ADT7460 TACH OUTPUT FAN SPEED COUNTER 03228-048 TACH CH1 100mV CH3 50.0mV CH2 5.00mV CH4 50.0mV M 4.00ms T A CH1 –2.00mV –1.00000ms 03228-046 Figure 48. Fan with TACH Pull-Up to VCC If the fan output has a resistive pull-up to 12 V (or other voltage greater than 5 V), the fan output can be clamped with a Zener diode, as shown in Figure 49. The Zener diode voltage should be greater than VIH of the TACH input but less than 5 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5 V is suitable. Figure 46. Fan Speed Sensing Waveform at TACH/AIN Pin VCC 12V Laying Out 2-Wire and 3-Wire Fans Figure 47 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. Some components are not populated, depending on whether a 2-wire or 3-wire fan is used. PULL-UP 4.7kΩ TYPICAL TACH OUTPUT ADT7460 TACH FAN SPEED COUNTER *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC R1 03228-049 ZD1* 12V OR 5V Figure 49. Fan with TACH Pull-Up to Voltage . 5 V, for example, 12 V, Clamped with Zener Diode 1N4148 3.3V OR 5V If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 50. Alternatively, a resistive attenuator may be used, as shown in Figure 51. R1 and R2 should be chosen such that R5 PWM Q1 MMBT2222 R3 R4 FOR 3-WIRE FANS: POPULATE R1, R2, R3 R4 = 0Ω C1 = UNPOPULATED FOR 2-WIRE FANS: POPULATE R4, C1 R1, R2, R3 UNPOPULATED 2 V < VPULLUP ×R2/(RPULLUP + R1 + R2) < 5 V 03228-047 C1 TACH/AIN The fan inputs have an input resistance of nominally 160 kΩ to ground. This should be taken into account when calculating resistor values. Figure 47. Planning for 2-Wire or 3-Wire Fans on a PCB TACH Inputs Pins 4, 6, 7, and 9 are open-drain TACH inputs for fan speed measurement. Signal conditioning in the ADT7460 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even where VCC is less than 5 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 48 to Figure 51 show circuits for most common fan TACH outputs. With a pull-up voltage of 12 V and pull-up resistor less than 1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ. This gives a high input voltage of 3.83 V. VCC 5V OR 12V FAN PULL-UP TYP VCC or Totem-Pole Output, Clamped with Zener and Resistor Rev. C | Page 29 of 52 03228-050 R2 ADT7460 Reading Fan Speed from the ADT7460 VCC 12V If fan speeds are being measured, this involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers are read from. This prevents erroneous TACH readings. ADT7460 VCC or Totem-Pole Output, Attenuated with R1/R2 Fan Speed Measurement The fan counter does not count the fan TACH output pulses directly because the fan speed may be less than 1000 RPM. It would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (Figure 52). The accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. CLOCK The fan tachometer reading registers report the number of 11.11 µs period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Since the device is essentially measuring the fan TACH period, the higher the count value the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or that it is running very slowly ( Comparison Performed Since the actual fan TACH period is being measured, exceeding a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT. The fan TACH limit registers are 16-bit values consisting of two bytes. Table 31. Fan TACH Limit Registers PWM TACH 1 03228-052 2 3 4 Figure 52. Fan Speed Measurement Register 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B Description TACH1 minimum low byte TACH1 minimum high byte TACH2 minimum low byte TACH2 minimum high byte TACH3 minimum low byte TACH3 minimum high byte TACH4 minimum low byte TACH4 minimum high byte Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF N, the number of pulses counted, is determined by the settings of Register 0x7B (fan pulses per revolution register). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted. Fan Speed Measurement Rate The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7460. The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78), when set, updates the fan TACH readings every 250 ms. Table 30. Fan Speed Measurement Registers If any of the fans are not being driven by a PWM channel but are instead powered directly from 5 V or 12 V, its associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. Register 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Description TACH1 low byte TACH1 high byte TACH2 low byte TACH2 high byte TACH3 low byte TACH3 high byte TACH4 Low byte TACH4 high byte Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 The fan TACH readings are normally updated once every second. Rev. C | Page 30 of 52 ADT7460 Calculating Fan Speed Table 34. Configuration Register 2 (Reg. 0x73) Assuming a fan with a two pulses/revolution (and two pulses/ revolution being measured), fan speed is calculated by Bit 3 Mnemonic AIN4 2 AIN3 For example: TACH1 High Byte (Reg. 0x29) = 0x17 TACH1 Low Byte (Reg. 0x28) = 0xFF 1 AIN2 What is Fan 1 speed in RPM? Fan 1 TACH Reading = 0x17FF = 6143d RPM = (f × 60)/Fan 1 TACH Reading RPM = (90000 × 60)/6143 Fan Speed = 879 RPM 0 AIN1 Fan Pulses per Revolution AIN Switching Threshold Different fan models can output either 1, 2, 3, or 4 TACH pulses per revolution. Once the number of fan TACH pulses is determined, it can be programmed into the fan pulses per revolution register (Reg. 0x7B) for each fan. Alternatively, this register can be used to determine the number of pulses/revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses/revolution settings, the smoothest graph with the lowest ripple determines the correct pulses/revolution value. Having configured the TACH inputs as AIN inputs for 2-wire measurements, the user can select the sensing threshold for the AIN signal. Fan Speed (RPM) = 90,000 × 60/Fan TACH Reading where: Fan TACH Reading = 16-Bit Fan Tachometer Reading Description 1 indicates that Pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. 1 indicates that Pin 4 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. 1 indicates that Pin 7 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. 1 indicates that Pin 6 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Table 35. Configuration Register 4 (Reg. 0x7D) Bit Mnemonic AINL Table 32. Fan Pulses per Revolution Register (Reg. 0x7B) Bit Mnemonic FAN1 Default FAN2 Default FAN3 Default FAN4 Default Description 2 pulses per revolution 2 pulses per revolution 2 pulses per revolution 2 pulses per revolution Fan Spin-Up The ADT7460 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Once two pulses are detected, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage of this is that fans have different spin-up characteristics and take different amounts of time to overcome inertia. The ADT7460 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spinup for a given spin-up time. Table 33. Fan Pulses per Revolution Register Bit Values Value 00 01 10 11 Description These two bits define the input threshold for 2-wire fan speed measurements. 00 = ±20 mV 01 = ±40 mV 10 = ±80 mV 11 = ±130 mV Description 1 pulse per revolution 2 pulses per revolution 3 pulses per revolution 4 pulses per revolution Fan Start-Up Timeout 2-Wire Fan Speed Measurements The ADT7460 is capable of measuring the speed of 2-wire fans, that is, fans without TACH outputs. To do this, the fan must be interfaced as shown in the Fan Drive Circuitry section. In this case, the TACH inputs need to be reprogrammed as analog inputs, AIN. To prevent false interrupts being generated as a fan spins up (since it is below running speed), the ADT7460 includes a fan start-up timeout function. This is the time limit allowed for two TACH pulses to be detected on spin-up. For example, if 2 seconds fan start-up timeout is chosen and no TACH pulses occur within 2 seconds of the start of spin-up, a fan fault is detected and flagged in the interrupt status registers. Rev. C | Page 31 of 52 ADT7460 Table 36. PWM1–PWM3 Configuration (Reg. 0x5C–0x5E) Fan Speed Control Bit The ADT7460 can control fan speed by two different modes. The first is automatic fan speed control mode. In this mode, fan speed is automatically varied with temperature and without CPU intervention, once initial parameters are set up. The advantage of this is that, in the case of the system hanging, the system is protected from overheating. The automatic fan speed control incorporates a feature called dynamic TMIN calibration. This feature reduces the design effort required to program the automatic fan speed control loop. For more information on how to program the automatic fan speed control loop and dynamic TMIN calibration, see the AN-613 Programming the Automatic Fan Speed Control Loop application note (http://www.analog.com/Uploaded Files/Application_Notes/331085006AN613_0.pdf). Mnemonic SPIN Description These bits control the start-up timeout for PWM1. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s Disabling Fan Start-Up Timeout Although fan start-up makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40) disables the spin-up for two TACH pulses. Instead, the fan spins up for the fixed time as selected in Registers 0x5C to 0x5E. The PWM outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). Table 37. PWM1–PWM3 Configuration (Reg. 0x5C–0x5E) Bits Mnemonic INV Manual Fan Speed Control The ADT7460 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if you want to change fan speed in software or if you want to adjust PWM duty cycle output for test purposes. Bits of Registers 0x5C, 0x5E (PWM configuration) control the behavior of each PWM output. PWM Logic State Bit The second fan speed control method is manual fan speed control, which is described next. Description 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle Table 39. PWM1 to PWM3 Configuration (Reg. 0x5C–0x5E) Bits Bit Mnemonic BHVR 111 Description Manual mode PWM Drive Frequency The PWM drive frequency can be adjusted for the application. Registers 0x5F to 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. Once under manual control, each PWM output can be manually updated by writing to Registers 0x30, 0x32 (PWMx current duty cycle registers). Table 38. PWM1 to PWM3 Frequency Registers (Reg. 0x5F to 0x61) Programming the PWM Current Duty Cycle Registers Bit Mnemonic FREQ Description 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz The PWM current duty cycle registers are 8-bit registers, which allow the PWM duty cycle for each output to be set anywhere from 0% (0x00) to 100% (0xFF) in steps of 0.39% (256 steps). The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39 Example 1: For a PWM duty cycle of 50%, Value (decimal) = 50/0.39 = 128d Value = 128d or 0x80. Example 2: For a PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85d Value = 85d or 0x54. Rev. C | Page 32 of 52 ADT7460 Table 40. PWM Duty Cycle Registers Register 0x30 0x31 0x32 XNOR TREE TEST MODE Description PWM1 duty cycle PWM2 duty cycle PWM3 duty cycle Default 0xFF (100%) 0xFF (100%) 0xFF (100%) By reading the PWMx current duty cycle registers, users can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or in acoustic enhancement mode. The ADT7460 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens or shorts on the system board. Figure 54 shows the signals that are exercised in the XNOR tree test mode. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR tree test enable register (Reg. 0x6F). TACH1 TACH2 TACH3 TACH4 PWM3 03228-053 VARY PWM DUTY CYCLE WITH 8-BIT RESOLUTION PWM1/XTO 03228-054 PWM2 Figure 54. XNOR Tree Test Figure 53. Control PWM Duty Cycle Manually with a Resolution of 0.39% POWER-ON DEFAULT OPERATING FROM 3.3 V STANDBY The ADT7460 has been specifically designed to operate from a 3.3 V STBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. If using the dynamic TMIN mode, lowering the core voltage of the processor would change the CPU temperature and change the dynamics of the system under dynamic TMIN control. Likewise, when monitoring THERM, the THERM timer should be disabled during these states. The ADT7460 does not monitor temperature and fan speed by default on power-up. Monitoring of temperature and fan speed is enabled by setting the start bit in configuration Register 1 (Bit 0, Address 0x40) to 1. The fans run at full speed on powerup. This is because the BHVR bits (Bits ) in the PWMx configuration registers are set to 100 (fans run full speed) by default. Rev. C | Page 33 of 52 ADT7460 ADT7460 REGISTER SUMMARY Table 41. ADT7460 Registers Address 0x20 0x22 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x3D 0x3E 0x3F R/W R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R Description 2.5 V Reading VCC Reading Remote 1 Temperature Local Temperature Remote 2 Temperature TACH1 Low Byte TACH1 High Byte TACH2 Low Byte TACH2 High Byte TACH3 Low Byte TACH3 High Byte TACH4 Low Byte TACH4 High Byte PWM1 Current Duty Cycle PWM2 Current Duty Cycle PWM3 Current Duty Cycle Remote 1 Operating Point Local Temp Operating Point Remote 2 Operating Point Dynamic TMIN Control Reg. 1 Dynamic TMIN Control Reg. 2 Device ID Register Company ID Number Revision Number Bit 7 9 9 9 9 9 7 15 7 15 7 15 7 15 7 7 7 7 7 7 R2T CYR2 7 7 VER Bit 6 8 8 8 8 8 6 14 6 14 6 14 6 14 6 6 6 6 6 6 LT CYR2 6 6 VER Bit 5 7 7 7 7 7 5 13 5 13 5 13 5 13 5 5 5 5 5 5 R1T CYL 5 5 VER Bit 4 6 6 6 6 6 4 12 4 12 4 12 4 12 4 4 4 4 4 4 PHTR2 CYL 4 4 VER Bit 3 5 5 5 5 5 3 11 3 11 3 11 3 11 3 3 3 3 3 3 PHTL CYL 3 3 STP Bit 2 4 4 4 4 4 2 10 2 10 2 10 2 10 2 2 2 2 2 2 PHTR1 CYR1 2 2 STP Bit 1 3 3 3 3 3 1 9 1 9 1 9 1 9 1 1 1 1 1 1 VCCRES CYR1 1 1 STP Bit 0 2 2 2 2 2 0 8 0 8 0 8 0 8 0 0 0 0 0 0 CYR2 CYR1 0 0 STP 0x40 0x41 0x42 0x44 0x45 0x48 0x49 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W VCC OOL D2 7 7 7 7 7 7 7 7 7 7 7 15 7 15 7 15 7 15 BHVR TODIS R2T D1 6 6 6 6 6 6 6 6 6 6 6 14 6 14 6 14 6 14 BHVR FSPDIS LT 5 5 5 5 5 5 5 5 5 5 5 5 13 5 13 5 13 5 13 BHVR RES R1T FAN3 4 4 4 4 4 4 4 4 4 4 4 12 4 12 4 12 4 12 INV FSPD RES FAN2 3 3 3 3 3 3 3 3 3 3 3 11 3 11 3 11 3 11 SLOW RDY VCC FAN1 2 2 2 2 2 2 2 2 2 2 2 10 2 10 2 10 2 10 SPIN LOCK RES OVT 1 1 1 1 1 1 1 1 1 1 1 9 1 9 1 9 1 9 SPIN 0x5D R/W BHVR BHVR BHVR INV SLOW SPIN 0x5E R/W BHVR BHVR BHVR INV SLOW 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 R/W R/W R/W R/W R/W R/W R/W R/W Configuration Register 1 Interrupt Status Register 1 Interrupt Status Register 2 2.5 V Low Limit 2.5 V High Limit VCC Low Limit VCC High Limit Remote 1 Temp Low Limit Remote 1 Temp High Limit Local Temp Low Limit Local Temp High Limit Remote 2 Temp Low Limit Remote 2 Temp High Limit TACH1 Minimum Low Byte TACH1 Minimum High Byte TACH2 Minimum Low Byte TACH2 Minimum High Byte TACH3 Minimum Low Byte TACH3 Minimum High Byte TACH4 Minimum Low Byte TACH4 Minimum High Byte PWM1 Configuration Register PWM2 Configuration Register PWM3 Configuration Register Remote 1 TRANGE/PWM 1 Freq. Local TRANGE/PWM 2 Freq. Remote 2 TRANGE/PWM 3 Freq. Enhance Acoustics Reg. 1 Enhance Acoustics Reg. 2 PWM1 Min Duty Cycle PWM2 Min Duty Cycle PWM3 Min Duty Cycle RANGE RANGE RANGE MIN3 EN2 7 7 7 RANGE RANGE RANGE MIN2 ACOU2 6 6 6 RANGE RANGE RANGE MIN1 ACOU2 5 5 5 RANGE RANGE RANGE SYNC ACOU2 4 4 4 THRM THRM THRM EN1 EN3 3 3 3 Rev. C | Page 34 of 52 STRT 2.5V RES 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 8 0 8 SPIN Default 0x00 0x00 0x80 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x64 0x64 0x64 0x00 0x00 0x27 0x41 0x62 or 0x6A 0x00 0x00 0x00 0x00 0xFF 0x00 0xFF 0x81 0x7F 0x81 0x7F 0x81 0x7F 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x62 Lockable? YES SPIN SPIN 0x62 YES SPIN SPIN SPIN 0x62 YES FREQ FREQ FREQ ACOU ACOU3 2 2 2 FREQ FREQ FREQ ACOU ACOU3 1 1 1 FREQ FREQ FREQ ACOU ACOU3 0 0 0 0xC4 0xC4 0xC4 0x00 0x00 0x80 0x80 0x80 YES YES YES YES YES YES YES YES YES YES YES YES YES YES ADT7460 Address 0x67 0x68 0x69 0x6A R/W R/W R/W R/W R/W Description Remote 1 Temp TMIN Local Temp TMIN Remote 2 Temp TMIN Remote 1 THERM Limit Bit 7 7 7 7 7 Bit 6 6 6 6 6 Bit 5 5 5 5 5 Bit 4 4 4 4 4 Bit 3 3 3 3 3 Bit 2 2 2 2 2 Bit 1 1 1 1 1 Bit 0 0 0 0 0 Default 0x5A 0x5A 0x5A 0x64 Lockable? YES YES YES YES YES 0x6B R/W Local THERM Limit 7 6 5 4 3 2 1 0 0x64 0x6C R/W 7 6 5 4 3 2 1 0 0x64 YES 0x6D 0x6E 0x6F 0x70 R/W R/W R/W R/W HYSR1 HYSR2 RES 7 HYSR1 HYSR2 RES 6 HYSR1 HYSR2 RES 5 HYSR1 HYSR2 RES 4 HYSL RES RES 3 HYSL RES RES 2 HYSL RES RES 1 HYSL RES XEN 0 0x44 0x40 0x00 0x00 YES YES YES YES 0x71 0x72 R/W R/W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 0x00 0x00 YES YES 0x73 0x74 0x75 0x76 0x77 0x78 R/W R/W R/W R/W R/W R/W Remote 2 THERM Limit Remote 1 Local Hysteresis Remote 2 Temp Hysteresis XNOR Tree Test Enable Remote 1 Temperature Offset Local Temperature Offset Remote 2 Temperature Offset Configuration Register 2 Interrupt Mask Register 1 Interrupt Mask Register 2 Extended Resolution 1 Extended Resolution 2 Configuration Register 3 SHDN OOL D2 RES TDM2 DC4 CONV R2T D1 RES TDM2 DC3 ATTN LT F4P VCC LTMP DC2 AVG R1T FAN3 VCC LTMP DC1 AIN4 RES FAN2 RES TDM1 FAST AIN3 VCC FAN1 RES TDM1 BOOST AIN1 2.5V RES 2.5V RES ALERT 0x00 0x00 0x00 0x00 0x00 0x00 YES 0x79 R THERM Status Register TMR TMR TMR TMR TMR TMR AIN2 RES OVT 2.5V RES THERM ENABLE TMR 0x00 0x7A R/W THERM Limit Register LIMT LIMT LIMT LIMT LIMT LIMT LIMT ASRT/ TMR LIMT 0x7B 0x7D 0x7E 0x7F R/W R/W R R Fan Pulses per Revolution Configuration Register 4 Test Register 1 Test Register 2 FAN4 RES FAN4 RES FAN3 FAN3 FAN2 FAN2 RES RES AINL AINL DO NOT WRITE TO THESE REGISTERS DO NOT WRITE TO THESE REGISTERS FAN1 RES FAN1 AL2.5V 0x55 0x00 0x00 0x00 YES 0x00 YES YES YES Table 42. Voltage Reading Registers (Power-On Default = 0x00) Register Address 0x20 0x22 R/W Read-Only Read-Only Description 2.5 V Reading (8 MSBs of reading) VCC Reading: Measures VCC through the VCC pin (8 MSBs of reading) These voltage readings are in twos complement format. If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers are read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. Table 43. Temperature Reading Registers (Power-On Default = 0x80) Register Address 0x25 0x26 0x27 R/W Read-Only Read-Only Read-Only Description Remote 1 Temperature Reading1 (8 MSBs of reading) Local Temperature Reading (8 MSBs of reading) Remote 2 Temperature Reading (8 MSBs of reading) These voltage readings are in twos complement format. 1 Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers are read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. Rev. C | Page 35 of 52 ADT7460 Table 44. Fan Tachometer Reading Registers (Power-On Default = 0x00) Register Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F R/W Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Description TACH1 Low Byte TACH1 High Byte TACH2 Low Byte TACH2 High Byte TACH3 Low Byte TACH3 High Byte TACH4 Low Byte TACH4 High Byte The Fan Tachometer Reading registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately measured. Since a valid fan tachometer reading requires that two bytes are read, the low byte MUST be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read in to these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is 1. Stalled or Blocked (object jamming the fan) 2. Failed (internal circuitry destroyed) 3. Not Populated (The ADT7460 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low byte should be set to 0xFFFF.) 4. Alternate Function, for example, TACH4 reconfigured as THERM pin 5. 2-Wire Instead of 3-Wire Fan Table 45. Current PWM Duty Cycle Registers (Power-On Default = 0xFF) Register Address 0x30 0x31 0x32 R/W Read/Write Read/Write Read/Write Description PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF) PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF) PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF) These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7460 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers. Table 46. Operating Point Registers (Power-On Default = 0x64) Register Address 0x33 0x34 0x35 R/W Read/Write Read/Write Read/Write Description Remote 1 Operating Point Register (Default = 100°C) Local Temp Operating Point Register (Default = 100°C) Remote 2 Operating Point Register (Default = 100°C) These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers will fail. These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled. The fans being controlled are adjusted to maintain temperature about an operating point. Rev. C | Page 36 of 52 ADT7460 Table 47. Register 0x36—Dynamic TMIN Control Register 1 (Power-On Default = 0x00) Bit Name CYR2 R/W Read/Write Reserved PHTR1 Read-Only Read/Write PHTL Read/Write PHTR2 Read/Write R1T Read/Write LT Read/Write R2T Read/Write Description MSB of 3-Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic TMIN Control Register 2 (Reg. 0x37). These three bits define the delay time between making subsequent TMIN adjustments in the control loop, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Reserved for future use. PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point register reflects its programmed value. PHTL = 1 copies the local channel’s current temperature to the local operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTL = 0 ignores any THERM assertions on the THERM pin. The local temperature operating point register reflects its programmed value. PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without system performance being affected. PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point register reflects its programmed value. R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control section. LT = 1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control section. R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control section. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 37 of 52 ADT7460 Table 48. Register 0x37—Dynamic TMIN Control Register 2 (Power-On Default = 0x00) Bit Name CYR1 R/W Read/Write CYL Read/Write CYR2 Read/Write Description 3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bits Decrease Cycle Increase Cycle 000 4 Cycles (0.5 s) 8 Cycles (1 s) 001 8 Cycles (1 s) 16 Cycles (2 s) 010 16 Cycles (2 s) 32 Cycles (4 s) 011 32 Cycles (4 s) 64 Cycles (8 s) 100 64 Cycles (8 s) 128 Cycles (16 s) 101 128 Cycles (16 s) 256 Cycles (32 s) 110 256 Cycles (32 s) 512 Cycles (64 s) 111 512 Cycles (64 s) 1024 Cycles (128 s) 3-Bit Local Temperature Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for local temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bits Decrease Cycle Increase Cycle 000 4 Cycles (0.5 s) 8 Cycles (1 s) 001 8 Cycles (1 s) 16 Cycles (2 s) 010 16 Cycles (2 s) 32 Cycles (4 s) 011 32 Cycles (4 s) 64 Cycles (8 s) 100 64 Cycles (8 s) 128 Cycles (16 s) 101 128 Cycles (16 s) 256 Cycles (32 s) 110 256 Cycles (32 s) 512 Cycles (64 s) 111 512 Cycles (64 s) 1024 Cycles (128 s) 2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic TMIN Control Register 1 (Reg. 0x36). These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 2 channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bits Decrease Cycle Increase Cycle 000 4 Cycles (0.5 s) 8 Cycles (1 s) 001 8 Cycles (1 s) 16 Cycles (2 s) 010 16 Cycles (2 s) 32 Cycles (4 s) 011 32 Cycles (4 s) 64 Cycles (8 s) 100 64 Cycles (8 s) 128 Cycles (16 s) 101 128 Cycles (16 s) 256 Cycles (32 s) 110 256 Cycles (32 s) 512 Cycles (64 s) 111 512 Cycles (64 s) 1024 Cycles (128 s) This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 38 of 52 ADT7460 Table 49. Register 0x40—Configuration Register 1 (Power-On Default = 0x00) Bit Name STRT R/W Read/Write LOCK Write Once RDY Read-Only FSPD RES FSPDIS Read/Write Read-Only Read/Write TODIS Read/Write VCC Read/Write Description Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit becomes read-only and cannot be changed once Bit 1 (lock bit) has been written. All limit registers should be programmed by BIOS before setting this bit to 1. (Lockable.) Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become readonly and cannot be modified until the ADT7460 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.) This bit is set to 1 by the ADT7460 to indicate that the device is fully powered-up and ready to begin systems monitoring. When set to 1, all fans run at full speed. Power-on default = 0. (This bit cannot be locked.) Reserved for future use. Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spinup timeout selected. When set to 1, the SMBus timeout feature is disabled. This allows the ADT7460 to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.) When set to 1, the ADT7460 rescales its VCC pin to measure a 5 V supply. When set to 0, the ADT7460 measures VCC as a 3.3 V supply. (Lockable.) Table 50. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00) Bit Name 2.5V R/W Read-Only RES VCC Read-Only Read-Only RES R1T Read-Only Read-Only LT Read-Only R2T Read-Only OOL Read-Only Description A 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. Reserved for future use. A 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. Reserved for future use. A 1 indicates that the Remote 1 low or high temperature limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. A 1 indicates the local low or high temperature limit has been exceeded. This bit is cleared on a read of the Status Register only if the error condition has subsided. A 1 indicatesthat the Remote 2 low or high temperature limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. A 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit. This saves the need to read Status Register 2 every interrupt or polling cycle. Rev. C | Page 39 of 52 ADT7460 Table 51. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00) Bit Name RES OVT R/W Read-Only Read-Only FAN1 Read-Only FAN2 Read-Only FAN3 Read-Only F4P Read-Only Read-Only D1 D2 Read-Only Read-Only Description Reserved for future use. A 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below THERM − THYST. A 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is NOT set when the PWM1 output is off. A 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is NOT set when the PWM2 output is off. A 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is NOT set when the PWM3 output is off. A 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is NOT set when the PWM3 output is off. If Pin 9 is configured as the THERM timer input for THERM monitoring, this bit is set when the THERM assertion time exceeds the limit programmed in the THERM Limit Register (Reg. 0x7A). A 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. A 1 indicates either an open or short circuit on the Thermal Diode 2 inputs. Table 52. Voltage Limit Registers Register Address 0x44 0x45 0x48 0x49 R/W Read/Write Read/Write Read/Write Read/Write Description 2.5 V Low Limit 2.5 V High Limit VCC Low Limit VCC High Limit Power-On Default 0x00 0xFF 0x00 0xFF Setting the Configuration Register 1 lock bit has no effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison). Table 53. Temperature Limit Registers Register Address 0x4E 0x4F 0x50 0x51 0x52 0x53 R/W Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description Remote 1 temperature low limit Remote 1 temperature high limit Local temperature low limit Local temperature high limit Remote 2 temperature low limit Remote 2 temperature high limit Power-On Default 0x81 0x7F 0x81 0x7F 0x81 0x7F Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit has no effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison). Rev. C | Page 40 of 52 ADT7460 Table 54. Fan Tachometer Limit Registers (Power-On Default = 0xFF) Register Address 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B R/W Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description TACH1 Minimum Low Byte TACH1 Minimum High Byte TACH2 Minimum Low Byte TACH2 Minimum High Byte TACH3 Minimum Low Byte TACH3 Minimum High Byte TACH4 Minimum Low Byte TACH4 Minimum High Byte Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers. Table 55. PWM Configuration Registers (Power-On Default = 0x62) RegisterAddress 0x5C 0x5D 0x5E R/W Read/Write Read/Write Read/Write Description PWM1 Configuration PWM2 Configuration PWM3 Configuration These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers will fail. Table 56. PWM Configuration Register Bits Bit Name SPIN R/W Read/Write SLOW INV Read/Write Read/Write BHVR Read/Write Description These bits control the start-up timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan start-up timeout period, the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low byte contains 0xFFFF or 0x0000, the Status Register 2 bit is not set, even if the fan has not started. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s SLOW = 1 makes the ramp rates for acoustic enhancement four times longer. This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low output. These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = Local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed (default). 100 = PWMx is disabled. 101 = Fastest speed calculated by Local and Remote 2 Temperature Control PWMx. 110 = Fastest speed calculated by all three Temperature Channels Control PWMx. 111 = Manual mode. PWM duty cycle registers (Reg. 0x30–0x32) become writable. Rev. C | Page 41 of 52 ADT7460 Table 57. TEMP TRANGE/PWM Frequency Registers (Power-On Default 0xC4) Register Address 0x5F 0x60 0x61 R/W Read/Write Read/Write Read/Write Description Remote 1 TRANGE/PWM1 frequency Local Temp TRANGE/PWM2 frequency Remote 2 TRANGE/PWM3 frequency These registers becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 58. TEMP TRANGE/PWM Frequency Register Bits Bit Name FREQ R/W Read/Write THRM Read/Write RANGE Read/Write Description These bits control the PWMx frequency. 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz THRM = 1 causes the THERM pin (Pin 9) to assert low as an output when this temperature channel’s THERM limit is exceeded by 0.25°C. The THERM pin remains asserted until the temperature is equal to or below the THERM limit. The minimum time that THERM asserts for is one monitoring cycle. This allows clock modulation of devices that incorporate this feature. THRM = 0 makes the THERM pin act as an input only, for example, for Pentium 4 PROCHOT monitoring, when Pin 9 is configured as THERM. These bits determine the PWM duty cycle vs. temperature slope for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (Default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C Rev. C | Page 42 of 52 ADT7460 Table 59. Register 0x62—Enhance Acoustics Register 1 (Power-On Default = 0x00) Bit Name ACOU R/W Read/Write EN1 SYNC Read/Write Read/Write MIN1 Read/Write MIN2 Read/Write MIN3 Read/Write Description These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 18 s 011 = 5 7s 100 = 8 4.4 s 101 = 12 3s 110 = 24 1.6 s 111 = 48 0.8 s When this bit is 1, acoustic enhancement is enabled on PWM1 output. SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output. When the ADT7460 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN − Hysteresis value. 0 = 0% Duty Cycle below TMIN − Hysteresis 1 = PWM1 Minimum Duty Cycle below TMIN − Hysteresis When the ADT7460 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN − Hysteresis value. 0 = 0% Duty Cycle below TMIN − Hysteresis 1 = PWM2 Minimum Duty Cycle below TMIN − Hysteresis When the ADT7460 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN− Hysteresis value. 0 = 0% Duty Cycle below TMIN − Hysteresis 1 = PWM3 Minimum Duty Cycle below TMIN − Hysteresis This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 43 of 52 ADT7460 Table 60. Register 0x63—Enhance Acoustics Register 2 (Power-On Default = 0x00) Bit Name ACOU3 R/W Read/Write EN3 ACOU2 Read/Write Read/Write EN2 Read/Write Description These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 11.8 s 011 = 5 7s 100 = 8 4.4 s 101 = 12 3s 110 = 24 1.6 s 111 = 48 0.8 s When this bit is 1, acoustic enhancement is enabled on PWM3 output. These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 11.8 s 011 = 5 7s 100 = 8 4.4 s 101 = 12 3s 110 = 24 1.6 s 111 = 48 0.8 s When this bit is 1, acoustic enhancement is enabled on PWM2 output. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 61. PWM Min Duty Cycle Registers Register Address 0x64 0x65 0x66 R/W Read/Write Read/Write Read/Write Description PWM1 Min Duty Cycle PWM2 Min Duty Cycle PWM3 Min Duty Cycle Power-On Default 0x80 (50% duty cycle) 0x80 (50% duty cycle) 0x80 (50% duty cycle) These registers become read-only when the ADT7460 is in automatic fan control mode. Table 62. PWM Min Duty Cycle Register Bits Bit Name PWM Duty Cycle Read/Write Read/Write Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% Duty Cycle (Fan Off) 0x40 = 25% Duty Cycle 0x80 = 50% Duty Cycle 0xFF = 100% Duty Cycle (Fan Full Speed) Rev. C | Page 44 of 52 ADT7460 Table 63. TMIN Registers Register Address 0x67 0x68 0x69 R/W Read/Write Read/Write Read/Write Description Remote 1 Temperature TMIN Local Temperature TMIN Remote 2 Temperature TMIN Power-On Default 0x5A (90°C) 0x5A (90°C) 0x5A (90°C) These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increase with temperature according to TRANGE. These registers become read-only when the Configuration Register 1 lock bit is set. Further attempts to write to these registers have no effect. Table 64. THERM Limit Registers Register Address 0x6A 0x6B 0x6C R/W Read/Write Read/Write Read/Write Description Remote 1 THERM Limit Local THERM Limit Remote 2 THERM Limit Power-On Default 0x64 (100°C) 0x64 (100°C) 0x64 (100°C) If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM Limit – Hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output. These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to these registers have no effect. Table 65. Temperature Hysteresis Registers Register Address 0x6D 0x6E R/W Read/Write Read/Write Description Remote 1 Local Temperature Hysteresis Remote 2 Temperature Hysteresis Power-On Default 0x44 0x40 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – Hysteresis. Up to 15°C of hysteresis may be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel if its THERM limit is exceeded. The PWM output being controlled goes to 100% if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM – Hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN. These registers become read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to these registers have no effect. Table 66. XNOR Tree Test Enable Register (Power-On Default = 0x00) Register Address 0x6F R/W Read/Write Description XNOR Tree Test Enable Bit Mnmeonic XEN RES Description If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR test mode. Unused. Do not write to these bits. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 45 of 52 ADT7460 Table 67. Remote 1 Temperature Offset Register (Power-On Default = 0x00) Register Address 0x70 R/W Read/Write Read/Write Description Remote 1 Temperature Offset Allows a twos complement offset value to be automatically added to or subtracted from the Remote 1 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.25°C. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 68. Local Temperature Offset Register (Power-On Default = 0x00) Register Address 0x71 R/W Read/Write Read/Write Description Local Temperature Offset Allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. LSB value = 0.25°C. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 69. Remote 2 Temperature Offset Register (Power-On Default = 0x00) Register Address 0x72 R/W Read/Write Read/Write Description Remote 2 Temperature Offset Allows a twos complement offset value to be automatically added to or subtracted from the Remote 2 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.25°C. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 46 of 52 ADT7460 Table 70. Register 0x73—Configuration Register 2 (Power-On Default = 0x00) Bit 0 Name AIN1 R/W Read/Write 1 AIN2 Read/Write 2 AIN3 Read/Write 3 AIN4 Read/Write 4 AVG Read/Write 5 ATTN Read/Write 6 CONV Read/Write 7 SHDN Read/Write Description AIN1 = 0, Speed of 3-wire fans measured using the TACH output from the fan. AIN1 = 1, Pin 6 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). AIN2 = 0, Speed of 3-wire fans measured using the TACH output from the fan. AIN2 = 1, Pin 7 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). AIN3 = 0, Speed of 3-wire fans measured using the TACH output from the fan. AIN3 = 1, Pin 4 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). AIN4 = 0, Speed of 3-wire fans measured using the TACH output from the fan. AIN4 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). AVG = 1, Averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster. ATTN = 1, the ADT7460 removes the attenuators from the 2.5 V input. The input can be used for other functions such as connecting up external sensors. CONV = 1, the ADT7460 is put into a single-channel ADC conversion mode. In this mode, the ADT7460 can be made to read continuously from one input only, for example, Remote 1 temperature. It is also possible to start ADC conversions using an external clock on Pin 6 by setting Bit 2 of Test Register 2 (Reg. 0x7F). This mode could be useful if, for example, users wanted to characterize/profile CPU temperature quickly. The appropriate ADC channel is selected by writing to Bits of TACH1 min high byte register (Reg. 0x55). Bits Reg. 0x55 Channel Selected 000 2.5 V 010 VCC (3.3 V) 101 Remote 1 Temp 110 Local Temp 111 Remote 2 Temp SHDN = 1, ADT7460 goes into shutdown mode. All PWM outputs assert low (or high depending, on state of INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to indicate that the fans are not being driven. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 71. Register 0x74—Interrupt Mask Register 1 (Power-On Default = 0x00) Bit 0 1 2 3 4 5 6 7 Name 2.5V RES VCC RES R1T LT R2T OOL R/W Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description A 1 masks SMBALERT for out-of-limit conditions on the 2.5 V channel. Reserved for future use. A 1 masks SMBALERT for out-of-limit conditions on the VCC channel. Reserved for future use. A 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. A 1 masks SMBALERT for out-of-limit conditions on the Local temperature channel. A 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. A 1 masks SMBALERT for any out-of-limit condition in Status Register 2. Rev. C | Page 47 of 52 ADT7460 Table 72. Register 0x75—Interrupt Mask Register 2 (Power-On Default = 0x00) Bit 0 1 2 3 4 5 Name RES OVT FAN1 FAN2 FAN3 F4P R/W Read/Write Read-Only Read/Write Read/Write Read/Write Read/Write 6 7 D1 D2 Read/Write Read/Write Description Reserved for future use. A 1 masks SMBALERT for overtemperature THERM conditions. A 1 masks SMBALERT for a Fan 1 fault. A 1 masks SMBALERT for a Fan 2 fault. A 1 masks SMBALERT for a Fan 3 fault. A 1 masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input, this bit masks SMBALERT for a THERM timer event. A 1 masks SMBALERT for a diode open or short on Remote 1 channel. A 1 masks SMBALERT for a diode open or short on Remote 2 channel. Table 73. Register 0x76—Extended Resolution Register 1 Bit Name 2.5V RES VCC RES R/W Read-Only Read/Write Read-Only Read/Write Description 2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement. Reserved for future use. VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement. Reserved for future use. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 74. Register 0x77—Extended Resolution Register 2 Bit Name RES TDM1 LTMP TDM2 R/W Read/Write Read-Only Read-Only Read-Only Description Reserved for future use. Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 75. Register 0x78—Configuration Register 3 (Power-On Default = 0x00) Bit Name ALERT R/W Read/Write THERM ENABLE Read/Write BOOST FAST Read/Write Read/Write DC1 DC2 DC3 DC4 Read/Write Read/Write Read/Write Read/Write Description ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-oflimit error conditions. THERM ENABLE = 1 enables THERM monitoring functionality on Pin 9 when it is configured as THERM. When THERM is asserted, fans can be run at full speed (if the BOOST bit is set), or a timer can be triggered to time how long THERM has been asserted for. BOOST = 1, assertion of THERM causes all fans to run at 100% duty cycle for fail-safe cooling. FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second, to once every 250 ms (4×). DC1 = 1 enables TACH measurements to be continuously made on TACH1. DC2 = 2 enables TACH measurements to be continuously made on TACH2. DC3 = 1 enables TACH measurements to be continuously made on TACH3. DC4 = 1 enables TACH measurements to be continuously made on TACH4. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Rev. C | Page 48 of 52 ADT7460 Table 76. Register 0x79—THERM Status Register (Power-On Default = 0x00) Bit Name TMR R/W Read-Only ASRT/TMR0 Read-Only Description Times how long THERM input is asserted. These seven bits read 0 until the THERM assertion time exceeds 45.52 ms. Is set high on the assertion of the THERM input. Cleared on read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 s to be reported back with a resolution of 22.76 ms. Table 77. Register 0x7A—THERM Limit Register (Power-On Default = 0x00) Bit Name LIMT R/W Read/Write Description Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 s to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately upon the assertion of the THERM input. Table 78. Register 0x7B—Fan Pulses per Revolution Register (Power-On Default = 0x55) Bit Name FAN1 R/W Read/Write FAN2 Read/Write FAN3 Read/Write FAN4 Read/Write Description Sets number of pulses to be counted when measuring Fan1 speed. Can be used to determine fan’s pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (Default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring FAN2 speed. Can be used to determine fan’s pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (Default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring FAN3 speed. Can be used to determine fan’s pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (Default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring FAN4 speed. Can be used to determine fan’s pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (Default) 10 = 3 11 = 4 Rev. C | Page 49 of 52 ADT7460 Table 79. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00) Bit Name AL2.5V R/W Read/Write RES AINL Read-Only Read/Write RES Description AL2.5V = 1, Pin 14 (2.5V/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. AL2.5V = 0, Pin 14 (2.5V/SMBALERT) is configured as a 2.5 V measurement input. Reserved for future use. These two bits define the input threshold for 2-wire fan speed measurements: 00 = ±20 mV 01 = ±40 mV 10 = ±80 mV 11 = ±130 mV Reserved for future use. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect. Table 80. Register 0x7E—Manufacturer’s Test Register 1 (Power On-Default = 0x00) Bit Name RES Read/Write Read-Only Description Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes and should NOT be written to under normal operation. Table 81. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00) Bit Name RES Read/Write Read-Only Description Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes and should NOT be written to under normal operation. Rev. C | Page 50 of 52 ADT7460 OUTLINE DIMENSIONS 0.193 BSC 9 16 0.154 BSC 1 0.236 BSC 8 PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AB Figure 55. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in millimeters ORDERING GUIDE Model ADT7460ARQ ADT7460ARQ-REEL ADT7460ARQ-REEL7 ADT7460ARQZ1 ADT7460ARQZ-REEL1 ADT7460ARQZ-REEL71 EVAL-ADT7460EB 1 Temperature Range −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP Evaluation Board Z = Pb-free part. Rev. C | Page 51 of 52 Package Option RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 ADT7460 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03228–0–3/05(C) Rev. C | Page 52 of 52