ADT7468ZEVB

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Other names and brands may be claimed as the property of others. dBCool® Remote Thermal Controller and Voltage Monitor ADT7468 FEATURES GENERAL DESCRIPTION Monitors up to 5 voltages Controls and monitors up to 4 fans High and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors Series resistance cancellation on the remote channel Extended temperature measurement range, up to 191°C Dynamic TMIN control mode intelligently optimizes system acoustics Automatic fan speed control mode manages system cooling based on measured temperature Enhanced acoustic mode dramatically reduces user perception of changing fan speeds Thermal protection feature via THERM output The ADT7468 dBCool controller is a thermal monitor and multiple PWM fan controller for noise sensitive or power sensitive applications requiring active system cooling. The ADT7468 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans, so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. A unique, dynamic TMIN control mode enables the system thermals/acoustics to be intelligently managed. The effectiveness of the system’s thermal solution can be monitored using the THERM input. The ADT7468 also provides critical thermal protection to the system using the bidirectional THERM pin as an output to prevent system or component overheating. Monitors performance impact of Intel® Pentium® 4 processor Thermal control circuit via THERM input 2-wire, 3-wire, and 4-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications (fully SMBus 1.1-compliant) FUNCTIONAL BLOCK DIAGRAM SCL SDA SMBALERT VID5 VID4 ACOUSTIC ENHANCEMENT CONTROL VID3 VID2 SERIAL BUS INTERFACE VID1 VID0 PWM1 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS HF & LF AUTOMATIC FAN SPEED CONTROL ACOUSTIC ENHANCEMENT CONTROL DYNAMIC TMIN CONTROL TACH1 TACH2 ADDRESS POINTER REGISTER PWM CONFIGURATION REGISTERS FAN SPEED COUNTER TACH3 TACH4 INTERRUPT MASKING PERFORMANCE MONITORING THERMAL PROTECTION THERM VCC INTERRUPT STATUS REGISTERS VCC TO ADT7468 ADT7468 D1+ D2+ 10-BIT ADC SRC D2– INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER +5VIN +12VIN +2.5VIN VCCP BAND GAP TEMP SENSOR BAND GAP REFERENCE GND LIMIT COMPARATORS VALUE AND LIMIT REGISTERS 04499-0-001 D1– Figure 1. ©2010 SCILLC. All rights reserved. May 2010 – Rev. 3 Publication Order Number: ADT7468/D ADT7468 TABLE OF CONTENTS Specifications..................................................................................... 3 PWM Logic State ........................................................................ 33 Absolute Maximum Ratings............................................................ 5 Fan Speed Control ...................................................................... 34 ESD Caution .................................................................................. 5 Miscellaneous Functions ............................................................... 35 Pin Configuration and Function Descriptions ............................. 6 Operating from 3.3 V Standby.................................................. 35 Typical Performance Characteristics ............................................. 8 XNOR Tree Test Mode............................................................... 35 Product Description ....................................................................... 10 Power-On Default ...................................................................... 35 Comparison between ADT7463 and ADT7468 ..................... 10 Automatic Fan Control Overview ................................................ 37 Recommended Implementation ............................................... 11 Dynamic TMIN Control Mode.................................................... 38 Serial Bus Interface ......................................................................... 12 Programming the Automatic Fan Speed Control Loop ............ 40 Write Operations ........................................................................ 13 Step 1: Hardware Configuration .............................................. 40 Read Operations ......................................................................... 14 Step 2: Configuring the Mux .................................................... 43 SMBus Timeout .......................................................................... 14 Step 3: TMIN Settings for Thermal Calibration Channels....... 45 VID Code Monitoring ................................................................... 15 Step 4: PWMMIN for Each PWM (Fan) Output ...................... 46 VID Code Registers.................................................................... 15 Step 5: PWMMAX for PWM (Fan) Outputs .............................. 46 Analog-to-Digital Converter ........................................................ 16 Step 6: TRANGE for Temperature Channels ................................ 47 Voltage Measurement Input ...................................................... 16 Step 7: TTHERM for Temperature Channels ............................... 50 Additional ADC Functions for Voltage Measurements ........ 16 Step 8: THYST for Temperature Channels .................................. 51 Temperature Measurement ....................................................... 18 Step 9: Operating Points for Temperature Channels ............. 52 Additional ADC Functions for Temperature Measurement ....................................................... 21 Step 10: High and Low Limits for Temperature Channels ... 53 Limits, Status Registers, and Interrupts ....................................... 22 Limit Values................................................................................. 22 Status Registers ........................................................................... 23 Interrupts ..................................................................................... 23 Active Cooling ................................................................................ 28 Driving the Fan Using PWM Control ..................................... 28 Laying Out 2-Wire and 3-Wire Fans ....................................... 30 Fan Speed Measurement............................................................ 31 Step 11: Monitoring THERM ................................................... 56 Step 12: Ramp Rate for Acoustic Enhancement ..................... 57 Enhancing System Acoustics......................................................... 59 Acoustic Enhancement Mode Overview ................................ 59 Register Tables................................................................................. 61 ADT7468 Programming Block Diagram .................................... 80 Outline Dimensions ....................................................................... 81 Ordering Guide .......................................................................... 81 Fan Spin-Up ................................................................................ 33 REVISION HISTORY Rev. 3 | Page 2 of 81 | www.onsemi.com ADT7468 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent most likely parametric norms. Logic inputs accept input high voltages up to VMAX even when device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and are not production tested. Table 1. Parameter POWER SUPPLY Supply Voltage Supply Current, ICC Min Typ Max Unit Test Conditions/Comments 3.0 3.3 5.5 3 20 V mA µA Interface inactive, ADC active Standby mode ±1.5 +2 +2 °C °C °C °C °C °C °C °C µA µΑ µΑ 0°C ≤ TA ≤ 70°C −40°C ≤ TA ≤ +100°C −40°C ≤ TA ≤ +120°C % % LSB %/V ms ms ms ms ms kΩ kΩ For 12 V and 5 V channels For all other channels 8 bits Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging disabled For VCC channel For all other channels % % % 0°C ≤ TA ≤ 70°C , 3.3 V −40°C ≤ TA ≤ +120°C , 3.3 V −40°C ≤ TA ≤ +120°C , 5.5 V RPM RPM RPM RPM Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C kHz kHz kHz 0°C ≤ TA ≤ 70°C, VCC = 3.3 V −40°C ≤ TA ≤ +120°C, VCC = 3.3 V −40°C ≤ TA ≤ +120°C, VCC = 5.5 V TEMP-TO-DIGITAL CONVERTER Local Sensor Accuracy −3.5 −4 Resolution Remote Diode Sensor Accuracy 0.25 ±1.5 +2 +2 −3.5 −4.5 Resolution Remote Sensor Source Current 0.25 6 36 96 ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Time (Voltage Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Monitoring Cycle Time Total Monitoring Cycle Time Input Resistance ±2 ±1.5 ±1 40 80 ±0.1 11 12 38 145 19 70 140 FAN RPM-TO-DIGITAL CONVERTER Accuracy ±5 ±7 ±10 65,535 Full-Scale Count Nominal Input RPM Internal Clock Frequency 100 200 109 329 5000 10000 85.5 83.7 81 90 90 90 94.5 96.3 99 Rev. 3 | Page 3 of 81 | www.onsemi.com 0°C ≤ TA ≤ 70°C; 0°C ≤ TD ≤ 120°C −40°C ≤ TA ≤ +100°C; 0°C ≤ TD ≤ +120°C −40°C ≤ TA ≤ +120°C; 0°C ≤ TD ≤ +120°C First current Second current Third current ADT7468 Parameter OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH Typ Max Unit Test Conditions/Comments 0.1 8.0 0.4 1.0 mA V µA IOUT = −8.0 mA, VCC = +3.3 V VOUT = VCC 0.1 0.4 1.0 V µA IOUT = −4.0 mA, VCC = +3.3 V VOUT = VCC 0.4 500 V V mV Hysteresis DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+ 0.5 V V V V V p-p Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT Detect Clock Low Timeout, tTIMEOUT 0.75 × VCCP SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH Min 2.0 2.0 5.5 0.8 Input Low Voltage, VIL −0.3 tLOW Maximum input voltage Minimum input voltage V V 0.4 −1 µA µA pF 1 5 VIN = VCC VIN = 0 See Figure 2 10 400 50 4.7 4.7 4.0 4.7 4.0 50 1000 300 250 300 15 tR kHz ns µs µs µs µs µs ns µs ns ns ms 35 tF Can be optionally disabled tHD; STA SCL tHIGH tHD; DAT tSU; STA tSU; STO tSU; DAT SDA tBUF P S S Figure 2. Serial Bus Timing Diagram Rev. 3 | Page 4 of 81 | www.onsemi.com P 04499-0-002 tHD; STA ADT7468 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Positive Supply Voltage (VCC) Maximum Voltage on 12 VIN Pin Voltage on Any Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJMAX) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature For Pb-free Lead Temperature (Soldering 10 sec) ESD Rating Rating 5.5 V 20 V −0.3 V to +6.5 V ±5 mA ±20 mA 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics 24-lead QSOP package: 220°C 260°C 300°C 1000 V θJA = 150°C/W θJC = 39°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 3 | Page 5 of 81 | www.onsemi.com ADT7468 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDA 1 24 PWM1/XTO SCL 2 23 VCCP GND 3 22 +2.5VIN VCC 4 21 +12VIN/VID5 20 +5VIN/THERM VID0 5 ADT7468 VID4 TOP VIEW VID2 7 (NOT TO SCALE) 18 D1+ 19 VID3 8 17 D1– TACH3 9 16 D2+ PWM2/SMBALERT 10 15 D2– TACH1 11 14 TACH4/GPIO/THERM/SMBALERT TACH2 12 13 PWM3 04499-0-003 VID1 6 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic SDA SCL GND VCC 5 6 7 8 9 VID0 VID1 VID2 VID3 TACH3 10 PWM2 SMBALERT 11 TACH1 12 TACH2 13 PWM3 14 TACH4 GPIO THERM SMBALERT 15 D2– Description Digital I/O (Open Drain). SMBus bidirectional serial data. Requires pull-up resistor. Digital Input (Open Drain). SMBus serial clock input. Requires pull-up resistor. Ground Pin. Power Supply. Can be powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored through this pin. The ADT7468 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply. Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans. Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed. Can be configured as a high or low frequency drive. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans. Digital I/O (Open Drain). Pulse width modulated output to control speed of Fan 3 and Fan 4. Requires 10 kΩ typical pull-up. Can be configured as a high or low frequency drive. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans. General Purpose Open Drain Digital I/O. Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input. For example, this pin can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature conditions. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Cathode Connection to Second Thermal Diode. Rev. 3 | Page 6 of 81 | www.onsemi.com ADT7468 Pin No. 16 17 18 19 20 Mnemonic D2+ D1– D1+ VID4 +5VIN THERM 21 +12VIN VID5 22 23 24 +2.5VIN VCCP PWM1 XTO Description Anode Connection to Second Thermal Diode. Cathode Connection to First Thermal Diode. Anode Connection to First Thermal Diode. Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Analog Input. Monitors +5 V power supply. Alternatively, this pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input. For example, it can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature conditions. Analog Input. Monitors +12 V power supply. Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). Supports VRM10 solutions. Analog Input. Monitors +2.5 V supply, typically a chipset voltage. Analog Input. Monitors processor core voltage (0 V to 3 V). Digital Output (Open Drain). Pulse width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up. Also functions as the output from the XOR tree in XOR test mode. Rev. 3 | Page 7 of 81 | www.onsemi.com ADT7468 0 20 –10 15 TEMPERATURE ERROR (°C) TEMPERATURE ERROR (°C) TYPICAL PERFORMANCE CHARACTERISTICS –20 –30 –40 100mV 10 40mV 5 0 –50 –5 –60 0 1 2.2 3.3 CAPACITANCE (nF) 4.7 10 100 1M 10M FREQUENCY (kHz) 100M 1G Figure 7. Remote Temperature Error vs. Common Mode Noise Frequency 0 6 –10 5 –20 4 TEMPERATURE ERROR (°C) –30 –40 –50 –60 –70 –80 20mV 3 2 1 0 10mV –1 –2 –90 0 5 10 15 CAPACITANCE (nF) 20 25 04499-0-046 –3 –100 Figure 5. External Temperature Error vs. D+/D− Capacitance –4 10 100 1M 10M FREQUENCY (kHz) 100M 04499-0-049 TEMPERATURE ERROR (°C) Figure 4. Temperature Error vs. Capacitance between D+ and D− –10 10 04499-0-048 04499-0-045 60mV 1G Figure 8. Remote Temperature Error vs. Differential Mode Noise Frequency 60 1.40 1.35 20 1.30 0 1.25 D+ TO VCC –20 1.20 –40 1.15 –60 1.10 –80 0 1 3.3 10 RESISTANCE (MΩ) 20 100 1.05 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 POWER SUPPLY VOLTAGE (V) Figure 6. Remote Temperature Error vs. PCB Resistance Rev. 3 | Page 8 of 81 | www.onsemi.com Figure 9. Normal IDD vs. Power Supply 04499-0-050 IDD (mA) 40 04499-0-047 TEMPERATURE ERROR (°C) D+ TO GND ADT7468 1.0 7 0.5 6 0 5 –0.5 ERROR (°C) IDD (µA) 4 3 –1.0 –1.5 –2.0 –2.5 2 –3.0 1 –4.0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 04499-0-091 04499-0-051 –3.5 0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 POWER SUPPLY VOLTAGE (V) Figure 13. Internal Temperature Error vs. ADT7468 Temperature Figure 10. Shutdown IDD vs. Power Supply 1.0 20 0.5 15 –0.5 5 ERROR (°C) 0 –5 –1.0 –1.5 –2.0 –2.5 –10 INT ERROR, 100mV –3.0 –15 –3.5 100 1M 10M 100M POWER SUPPLY NOISE FREQUENCY (kHz) 1G 04499-0-052 –20 10 –4.0 –40 20 EXT ERROR, 250mV TEMPERATURE ERROR (°C) 15 10 5 0 EXT ERROR, 100mV –5 –10 1G 04499-0-053 –15 100 1M 10M 100M POWER SUPPLY NOISE FREQUENCY (kHz) 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 14. Remote Temperature Error vs. ADT7468 Temperature Figure 11. Internal Temperature Error vs. Power Supply –20 10 –20 Figure 12. Remote Temperature Error vs. Power Supply Noise Frequency Rev. 3 | Page 9 of 81 | www.onsemi.com 04499-0-092 TEMPERATURE ERROR (°C) 0 INT ERROR, 250mV 10 ADT7468 PRODUCT DESCRIPTION The ADT7468 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and programming functions for the ADT7468 are performed over the serial bus. In addition, a pin can be reconfigured as an SMBALERT output to signal out-of-limit conditions. On the ADT7463, the measurement range is from −127°C to +127°C. This means that the ADT7468 can measure higher temperatures. The ADT7468 also includes the ADT7463 temperature range; the temperature measurement range can be switched by setting Bit 0 of Configuration Register 5. 6. The ADT7468 maximum fan speed (% duty cycle) in the automatic fan speed control loop can be programmed. The maximum fan speed is 100% duty cycle on the ADT7463 and is not programmable. 7. The offset register in the ADT7468 is programmable up to ±64°C with 0.50°C resolution. The offset register of the ADT7463 is programmable up to ±32°C with 0.25°C resolution. 8. VCCP is monitored on Pin 23 of the ADT7468 and can be used to set the threshold for THERM (PROCHOT) (2/3 of VCCP). The threshold for THERM (PROCHOT) is set at VIH = 1.7 V and VIL = 0.8 V on the ADT7463. 9. On the ADT7463, Pin 22 can be reconfigured as SMBus ALERT. This is not available on the ADT7468; instead, SMBALERT can be enabled on Pin 14. COMPARISON BETWEEN ADT7463 AND ADT7468 The ADT7468 is an upgrade to the ADT7463. The ADT7468 and ADT7463 are almost pin and register map compatible. The ADT7468 and ADT7463 have the following differences: 1. 2. 3. On the ADT7468, the PWM drive signals can be configured as either high frequency or low frequency drives. The low frequency option is programmable between 10 Hz and 100 Hz. The high frequency option is 22.5 kHz. On the ADT7463, only the low frequency option is available. Once VCC is powered up, monitoring of temperature and fan speeds is enabled on the ADT7468 when VCCP is powered up. If VCCP is never powered up, this is enabled when the first SMBus transaction with the ADT7468 is completed. On the ADT7463, the STRT bit in Configuration Register 1 must be set to enable monitoring. The fans are switched off by default upon power-up. On the ADT7463, the fans run at full speed on power-up. Fail-safe cooling is provided such that when the measured temperature exceeds the THERM limit (100°C), the fans run at full speed. Fail-safe cooling is also provided 4.6 secs after VCCP is powered-up (see Figure 48). The fans operate at full speed if the ADT7468 has not been addressed via the SMBus within 4.6 secs of when the VCCP is powered up. This protects the system in the event that the SMBus fails. The ADT7468 can be programmed at any time, and it behaves as programmed. If VCCP is never powered-up, fail-safe cooling is effectively disabled. If VCCP is disabled, writing to the ADT7468 at any time causes the ADT7468 to operate normally. 4. Series resistance cancellation (SRC) is provided on the remote temperature channels on the ADT7468, but not on the ADT7463. SRC automatically cancels linear offset introduced by a series resistance between the thermal diode and the sensor. 5. The ADT7468 has an extended temperature measurement range. The measurement range goes from–64°C to +191°C. 10. A GPIO can also be made available on Pin 14 on the ADT7468. This is not available on the ADT7463. Set the GPIO polarity and direction in Configuration Register 5. The GPIO status bit is Bit 5 of Status Register 2 (shared with TACH4 and THERM, because only one can be enabled at a time). 11. The ADT7463 has three possible SMBus addresses, which are selectable using the address select and address enable pins. The ADT7468 has one SMBus address available at Address 0x2E. Due to the inclusion of extra functionality, the register map has changed, including an additional configuration register: Configuration Register 5 at Address 0x7C. Configuration Register 5 Bit 0: If Bit 0 is set to 1, in terms of temperature the ADT7468 is backward-compatible with the ADT7463. Measurements including the TMIN calibration circuit, and fan control work in the range of −127°C to +127°C. Also, care should be taken in reprogramming the temperature limits (TMIN, operating point, and THERM limits) to their desired twos complement value, because the power-on default for them is at Offset 64. The extended temperature range is −64°C to 191°C. The default is 1, which is in the −64°C to +191°C temperature range. Rev. 3 | Page 10 of 81 | www.onsemi.com ADT7468 Bit 1= 0 is the high frequency (22.5 kHz) fan drive signal. RECOMMENDED IMPLEMENTATION Bit 1 = 1 switches the fan drive to low frequency PWM, programmable between 10 Hz and 100 Hz, the same as the ADT7463. The default = 0 = HF PWM. Configuring the ADT7468 as in Figure 15 allows the system designer to use the following features: • Two PWM outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high. • Three TACH fan speed measurement inputs. Setting the Functionality of Pin 14 • VCC measured internally through Pin 3. Pin 14 on the ADT7468 has four possible functions: SMBALERT, THERM, GPIO, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D. • CPU temperature measured using Remote 1 temperature channel. • Ambient temperature measured through Remote 2 temperature channel. • Bidirectional THERM pin. This feature allows Intel Pentium 4 PROCHOT monitoring and can function as an overtemperature THERM output. Alternatively, it can be programmed as an SMBALERT system interrupt output. Bit 2 sets the direction for the GPIO: 0 = input, 1 = output. Table 4. Pin 14 Settings Bit 0 0 0 Bit 1 0 1 Function TACH4 THERM 1 0 SMBALERT 1 1 GPIO CPU FAN ADT7468 FRONT CHASSIS FAN TACH2 PWM1 TACH1 PWM3 REAR CHASSIS FAN TACH3 5(VRM9)/6(VRM10) VID[0:4]/VID[0:5] D2+ D2– THERM PROCHOT D1+ AMBIENT TEMPERATURE CPU D1– 3.3VSB 5V SDA 12V/VID5 VCOMP SCL CURRENT VCORE SMBALERT GND Figure 15. ADT7468 Configuration Rev. 3 | Page 11 of 81 | www.onsemi.com ICH 04499-0-004 ADP316x VRM CONTROLLER ADT7468 SERIAL BUS INTERFACE following functions. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. On PCs and servers, control of the ADT7468 is carried out using the serial system management bus (SMBus). The ADT7468 is connected to this bus as a slave device, under the control of a master controller, which is usually (but not necessarily) the ICH. The ADT7468 has a fixed 7-bit serial bus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address (01011100 or 0x5C). Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition might be interpreted as a stop signal when the clock is high. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. This write operation is illustrated in Figure 16. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities: • When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. If the ADT7468’s address pointer register value is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7468, but only the data byte containing the register address is sent, since no data is written to the register. This is shown in Figure 17. A read operation is then performed consisting of the serial bus address, R/W, bit set to 1, followed by the data byte read from the data register. This is shown in Figure 18. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. • If the address pointer register is known to be at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 18 In the ADT7468, write operations contain either one or two bytes, and read operations contain one byte and perform the 1 9 9 1 SCL 0 1 0 1 1 1 0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE D7 R/W D6 ACK. BY ADT7468 D5 D4 D3 D2 D1 D0 ACK. BY ADT7468 FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 ACK. BY STOP BY ADT7468 MASTER Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register Rev. 3 | Page 12 of 81 | www.onsemi.com 04499-0-005 SDA ADT7468 1 9 9 1 SCL 0 1 START BY MASTER 0 1 1 1 0 D7 R/W D6 ACK. BY ADT7468 FRAME 1 SERIAL BUS ADDRESS BYTE D4 D5 D2 D3 D1 D0 ACK. BY ADT7468 FRAME 2 ADDRESS POINTER REGISTER BYTE STOP BY MASTER 04499-0-006 SDA Figure 17. Writing to the Address Pointer Register Only 1 9 9 1 SCL 0 START BY MASTER 1 0 1 1 1 0 R/W D7 D6 ACK. BY ADT7468 FRAME 1 SERIAL BUS ADDRESS BYTE D5 D4 D2 D3 D1 FRAME 2 DATA BYTE FROM ADT7468 D0 NO ACK. BY STOP BY MASTER MASTER 04499-0-007 SDA Figure 18. Reading Data from a Previously Selected Register In addition to supporting the send byte and receive byte protocols, the ADT7468 also supports the read byte protocol. (See Intel’s System Management Bus Specifications Rev. 2 for more information.) If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT7468, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This operation is illustrated in Figure 19. 1 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7468 are discussed below. The following abbreviations are used in the diagrams: S: START P: STOP R: READ W: WRITE A: ACKNOWLEDGE A: NO ACKNOWLEDGE 2 3 SLAVE S W A ADDRESS 4 5 6 REGISTER ADDRESS A P 04499-0-008 It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. Figure 19. Setting a Register Address for a Subsequent Read If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition. Write Byte In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. The ADT7468 uses the following SMBus write protocols. 2. Send Byte In this operation, the master device sends a single command byte to a slave device as follows: The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 1. 5. The slave asserts ACK on SDA. The master device asserts a start condition on SDA. Rev. 3 | Page 13 of 81 | www.onsemi.com ADT7468 6. The master sends a data byte. Alert Response Address 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA to end the transaction. Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. This operation is illustrated in Figure 20. 2 3 SLAVE S W A ADDRESS 4 5 SLAVE ADDRESS 6 7 8 A DATA A P 04499-0-009 1 Figure 20. Single Byte Write to a Register The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following procedure occurs: READ OPERATIONS 1. SMBALERT is pulled low. The ADT7468 uses the following SMBus read protocols. 2. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. 4. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the ADT7468 has responded to the alert response address, the master must read the status registers and the SMBALERT is cleared only if the error condition is absent. Receive Byte This operation is useful when repeatedly reading a single register. The register address must have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. In the ADT7468, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in Figure 21. 2 3 SLAVE S R A ADDRESS 4 5 6 DATA A P 04499-0-010 1 Figure 21. Single Byte Read from a Register SMBUS TIMEOUT The ADT7468 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7468 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. Configuration Register 1 (Reg. 0x40) TODIS = 0, SMBus timeout enabled (default). TODIS = 1, SMBus timeout disabled. Rev. 3 | Page 14 of 81 | www.onsemi.com ADT7468 VID CODE MONITORING The ADT7468 has five dedicated voltage ID (VID code) inputs. These are digital inputs that can be read back through the VID register (Reg. 0x43) to determine the processor voltage required or being used in the system. Five VID code inputs support VRM9.x solutions. In addition, Pin 21 (12 V input) can be reconfigured as a sixth VID input to satisfy future VRM requirements. VID Code Input Threshold Voltage VID CODE REGISTERS Pin 21 can be reconfigured as a sixth VID code input (VID5) for VRM10-compatible systems. Because the pin is configured as VID5, it is not possible to monitor a 12 V supply. VID Code Register 0x43 = VID0, reflects the logic state of Pin 5. The switching threshold for the VID code inputs is approximately 1 V. To enable future compatibility, it is possible to reduce the VID code input threshold to 0.6 V. Bit 6 (THLD) of the VID register (Reg. 0x43) controls the VID input threshold voltage. Reconfiguring Pin 21 as VID5 Input Bit 7 of the VID register (Reg. 0x43) determines the function of Pin 21. System or BIOS software can read the state of Bit 7 to determine whether the system is designed to monitor 12 V or is monitoring a sixth VID input. = VID1, reflects the logic state of Pin 6. = VID2, reflects the logic state of Pin 7. = VID3, reflects the logic state of Pin 8. Status Register 2 (Reg. 0x42 = VID4, reflects the logic state of Pin 19. = VID5, reconfigurable 12 V input. This bit reads 0 when Pin 21 is configured as the 12 V input. This bit reflects the logic state of Pin 21 when the pin is configured as VID5. THLD = 0, VID switching threshold = 1 V, VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V 12 V/VC = 0, if Pin 21 is configured as VID5, then Logic 0 denotes no change in VID code within the last 11 µs. 12 V/VC = 1, if Pin 21 is configured as VID5, then Logic 1 means that a change has occurred on the VID code inputs within the last 11 µs. An SMBALERT is generated, if this function is enabled. VID Code Change Detect Function THLD = 1, VID switching threshold = 0.6 V, VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V VIDSEL = 0, Pin 21 functions as a 12 V measurement input. Software can read this bit to determine that there are five VID inputs being monitored. Bit 5 of Register 0x43 (VID5) always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42) reflects 12 V out-of-limit measurements. VIDSEL = 1, Pin 21 functions as the sixth VID code input (VID5). Software can read this bit to determine that there are six VID inputs being monitored. Bit 5 of Register 0x43 reflects the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42) reflects VID code changes. The ADT7468 has a VID code change detect function. When Pin 21 is configured as the VID5 input, VID code changes can be detected and reported back by the ADT7468. Bit 0 of Status Register 2 (Reg. 0x42) is the 12 V/VC bit and denotes a VID change when set. The VID code change bit is set when the logic states on the VID inputs are different than they were 11 µs previously. The change of VID code can be used to generate an SMBALERT interrupt. If an SMBALERT interrupt is not required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75), when set, prevents SMBALERTs from occurring on VID code changes. Rev. 3 | Page 15 of 81 | www.onsemi.com ADT7468 ANALOG-TO-DIGITAL CONVERTER All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter, which has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and therefore has adequate headroom to cope with overvoltages. VOLTAGE MEASUREMENT INPUT The ADT7468 has four external voltage measurement channels and can measure its own supply voltage, VCC. Pins 20 to 23 can measure 5 V, 12 V, 2.5 V supplies, and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADT7468 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. Input Circuitry The internal structure for the analog inputs is shown in Figure 22. The input circuit consists of an input protection diode, an attenuator, and a capacitor to form a first-order lowpass filter that gives input immunity to high frequency noise. 5VIN 3.3VIN 2.5VIN VCCP Voltage Limit Registers Associated with each voltage measurement channel is a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Reg. 0x44, 2.5 V low limit = 0x00 default Reg. 0x45, 2.5 V high limit = 0xFF default Reg. 0x46, VCCP low limit = 0x00 default Reg. 0x47, VCCP high limit = 0xFF default Reg. 0x48, VCC low limit = 0x00 default Reg. 0x49, VCC high limit = 0xFF default Reg. 0x4A, 5 V low limit = 0x00 default Reg. 0x4B, 5 V high limit = 0xFF default Reg. 0x4C, 12 V Low Limit = 0x00 default Reg. 0x4D, 12 V High Limit = 0xFF default Table 6 shows the input ranges of the analog inputs and output codes of the 10-bit ADC. 120kΩ 20kΩ 30pF 47kΩ 30pF 71kΩ 30pF 94kΩ 30pF When the ADC is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms. 93kΩ ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS 68kΩ A number of other functions are available on the ADT7468 to offer the system designer increased flexibility. MUX Turn-Off Averaging 45kΩ 17.5kΩ 52.5kΩ 35pF Figure 22. Structure of Analog Inputs Voltage Measurement Registers Reg. 0x20, 2.5 V reading = 0x00 default Reg. 0x21, VCCP reading = 0x00 default Reg. 0x22, VCC reading = 0x00 default Reg. 0x23, 5 V reading = 0x00 default 04499-0-011 12VIN Reg. 0x24, 12 V reading = 0x00 default For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. For instance, where faster conversions are needed, setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This effectively gives a reading 16 times faster (0.7 ms), but the reading may be noisier. Bypass Voltage Input Attenuator Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes the attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V inputs, which allows the user to directly connect external sensors or rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V. Rev. 3 | Page 16 of 81 | www.onsemi.com ADT7468 Single-Channel ADC Conversion TACH1 Minimum High Byte (Reg. 0x55) Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7468 into single-channel ADC conversion mode. In this mode, the ADT7468 can be made to read a single voltage channel only. If the internal ADT7468 clock is used, the selected input is read every 0.7 ms. The appropriate ADC channel is selected by writing to Bits of the TACH1 minimum high byte register (0x55). Selects ADC channel for single-channel convert mode. Configuration Register 2 (Reg. 0x73) = 1, averaging off. = 1, bypass input attenuators. = 1, single-channel convert mode. Table 5. Programming the Single Channel ADC Function Bits Reg. 0x55 000 001 010 011 100 101 110 111 Channel Selected 2.5 V VCCP VCC 5V 12 V Remote 1 temperature Local temperature Remote 2 temperature Table 6. 10-Bit A/D Output Code vs. VIN Input Voltage A/D Output 12 VIN 2.9970 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 11111111 11 1 The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the VCC output codes are the same as for the 5 VIN column. Rev. 3 | Page 17 of 81 | www.onsemi.com ADT7468 A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor, operated at constant current. Unfortunately, this technique requires calibration to null the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7468 is to measure the change in VBE when the device is operated at three currents. Previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. Figure 24 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D− input. C1 can optionally be added as a noise filter (the recommended maximum value is 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Noise Filtering section. for mass production. The technique used in the ADT7468 is to measure the change in VBE when the device is operated at three currents. This is given by ∆V BE = KT / q × 1n(N ) where: K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. Figure 23 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. It could also be a discrete transistor such as a 2N3904/2N3906. I N2 × I N1 × I IBIAS VDD REMOTE SENSING TRANSISTOR VOUT+ D+ TO ADC D– LPF fC = 65kHz VOUT– 04499-0-012 TEMPERATURE MEASUREMENT Local Temperature Measurement The ADT7468 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Table 7 and Table 8. Theoretically, the temperature sensor and ADC can measure temperatures from −128°C to +127°C (or −61°C to +191°C in the extended temperature range) with a resolution of 0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7468 operating temperature range are not possible. Remote Temperature Measurement The ADT7468 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pins 17 and 18, or Pins 15 and 16. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about –2 mV/°C. Unfortunately, the absolute value of VBE varies from device to device and individual calibration is required, and therefore the technique is unsuitable Figure 23. Signal Conditioning for Remote Diode Temperature Sensors If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D– input and the emitter is connected to the D+ input. If an NPN transistor is used, the emitter is connected to the D– input and the base to the D+ input. Figure 25 and Figure 26 show how to connect the ADT7468 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D– input. To measure ∆VBE, the operating current through the sensor is switched among three related currents. Shown in Figure 23, N1 × I and N2 × I are different multiples of the current I. The currents through the temperature diode are switched between I and N1 × I, giving ∆VBE1, and then between I and N2 × I, giving ∆VBE2. The temperature can then be calculated using the two ∆VBE measurements. This method can also cancel the effect of any series resistance on the temperature measurement. The resulting ∆VBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then sent to a chopperstabilized amplifier that amplifies and rectifies the waveform to Rev. 3 | Page 18 of 81 | www.onsemi.com ADT7468 produce a dc voltage proportional to ∆VBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. The results of remote temperature measurements are stored in 10-bit, twos complement format, as illustrated in Table 7. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (Reg. 0x77). This gives temperature readings with a resolution of 0.25°C. Noise Filtering For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ and D− pins to decrease the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. A capacitor of this value reduces the noise, but does not eliminate it, making use of the sensor difficult in a very noisy environment. The ADT7468 has a major advantage over other devices for eliminating the effects of noise on the external sensor. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. The effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result. typically, up to 3 kΩ of resistance. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. See the Noise Filtering section for details. Factors Affecting Diode Accuracy Remote Sensing Diode The ADT7468 is designed to work with either substrate transistors built into processors or with discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+, and the emitter is connected to D−. If a PNP transistor is used, the collector and base are connected to D− and the emitter is connected to D+. To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: • The construction of a filter allows the ADT7468 and the remote temperature sensor to operate in noisy environments. Figure 24 shows a low-pass R-C-R filter, with the following values: R = 100 Ω, C = 1 nF. ∆T = (nf − 1.008) × (273.15 K + T) This filtering reduces both common-mode noise and differential noise. To correct for this error, the user can write the ∆T value to the offset register. The ADT7468 then automatically adds or subtracts it from the temperature measurement. 100Ω 1nF 100Ω D– 04499-0-093 D+ REMOTE TEMPERATURE SENSOR The ideality factor, nf, of the transistor is a measure of the deviation of the thermal diode from ideal behavior. The ADT7468 is trimmed for an nf value of 1.008. Use the following equation to calculate the error introduced at a temperature T (°C), when using a transistor whose nf does not equal 1.008. See the processor data sheet for the nf values. Figure 24. Filter Between Remote Sensor and ADT7468 Series Resistance Cancellation Parasitic resistance to the ADT7468 D+ and D− inputs (seen in series with the remote diode) is caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.5°C offset per Ω of parasitic resistance in series with the remote diode. The ADT7468 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result, without the need for user characterization of this resistance. The ADT7468 is designed to automatically cancel, • Some CPU manufacturers specify the high and low current levels of the substrate transistors. The high current level of the ADT7468, IHIGH, is 96 µA and the low level current, ILOW, is 6 µA. If the ADT7468 current levels do not match the current levels specified by the CPU manufacturer, it might be necessary to remove an offset. The CPU’s data sheet should advise whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. It is important to note that, if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. If a discrete transistor is used with the ADT7468, the best accuracy is obtained by choosing devices according to the following criteria: Rev. 3 | Page 19 of 81 | www.onsemi.com ADT7468 Base-emitter voltage greater than 0.25 V at 6 µA, with the highest operating temperature. • Base-emitter voltage less than 0.95 V at 100 µA, with the lowest operating temperature. • Base resistance less than 100 Ω. • Small variation in hFE (from 50 to 150), which indicates tight control of VBE characteristics. Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23 packages, are suitable devices to use. Table 7. Temperature Data Format Temperature Digital Output (10-Bit)1 –128°C –125°C –100°C –75°C –50°C –25°C –10°C 0°C 10.25°C 25.5°C 50.75°C 75°C 100°C 125°C 127°C 1000 0000 00 1000 0011 00 1001 1100 00 1011 0101 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 1 Bold numbers denote 2 LSB of measurement in Extended Resolution Register 2 (Reg. 0x77) with 0.25°C resolution. Table 8. Extended Range, Temperature Data Format Temperature Digital Output (10-Bit)1 –64°C –1°C 0°C 1°C 10°C 25°C 50°C 75°C 100°C 125°C 191°C 0000 0000 00 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00 Bold numbers denote 2 LSB of measurement in Extended Resolution Register 2 (Reg. 0x77) with 0.25°C resolution. ADT7468 2N3904 NPN D+ D– 04499-0-013 1 Figure 25. Measuring Temperature Using an NPN Transistor ADT7468 D+ 2N3906 PNP D– 04499-0-014 • Figure 26. Measuring Temperature Using a PNP Transistor Nulling Temperature Errors As CPUs are developed that run faster, it is getting more difficult to avoid high frequency clocks when routing the D+/D– traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributed to noise coupled onto the D+/D– lines. Constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value. The ADT7468 has temperature offset registers at Addresses 0x70 and 0x72 for the Remote 1 and Remote 2 temperature channels. By doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it using the offset registers. The offset registers automatically add an Offset 64/twos complement 8-bit reading to every temperature measurement. The LSBs add 0.5°C offset to the temperature reading; therefore, the 8-bit register effectively allows temperature offsets up to ±64°C with a resolution of 0.5°C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Temperature Offset Registers Reg. 0x70, Remote 1 temperature offset = 0x00 (0°C default) Reg. 0x71, Local temperature offset = 0x00 (0°C default) Reg. 0x72, Remote 2 temperature offset = 0x00 (0°C default) ADT7463/ADT7468 Backwards Compatible Mode By setting Bit 1 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value registers (0x25, 0x26, and 0x27) in twos complement in the range of −64°C to +127°C (the ADT7468 makes calculations based on the Offset 64 extended range and clamps the results, if necessary.) The temperature limits must be reprogrammed in twos complement. If a twos complement temperature below −63°C is entered, the temperature is clamped to −63°C. In this mode, the diode fault condition remains at −128°C = 1000 0000, while in the extended temperature range (−64°C to +191°C) the fault condition is represented by −64°C = 0000 0000. Temperature Measurement Registers Reg. 0x25, Remote 1 temperature Reg. 0x26, Local temperature Reg. 0x27, Remote 2 temperature Reg. 0x77, Extended Resolution 2 = 0x00 default TDM2, Remote 2 temperature LSBs LTMP, local temperature LSBs TDM1, Remote 1 temperature LSBs Rev. 3 | Page 20 of 81 | www.onsemi.com ADT7468 Temperature Measurement Limit Registers Table 10. Conversion Time with Averaging Enabled Each temperature measurement channel is associated with high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Channel Voltage Channels Remote Temperature Local Temperature Reg. 0x4E, Remote 1 temperature low limit = 0x01 default Single-Channel ADC Conversions Reg. 0x4F, Remote 1 temperature high limit = 0x7F default Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7468 into single-channel ADC conversion mode. In this mode, the ADT7468 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits of the TACH1 minimum high byte register (0x55). Reg. 0x50, local temperature low limit = 0x01 default Reg. 0x51, local temperature high limit = 0x7F default Reg. 0x52, Remote 2 temperature low limit = 0x01 default Reg. 0x53, Remote 2 temperature high limit = 0x7F default Reading Temperature from the ADT7468 Measurement Time 11 ms 39 ms 12 ms It is important to note that temperature can be read from the ADT7468 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order. Table 11. Channel Selection If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (Reg. 0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read and vice versa. Configuration Register 2 (Reg. 0x73) Channel Selected Remote 1 temperature Local temperature Remote 2 temperature = 1, averaging off. = 1, single-channel convert mode. TACH1 Minimum High Byte (Reg. 0x55) selects ADC channel for single-channel convert mode. Overtemperature Events ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT A number of other functions are available on the ADT7468 to offer the system designer increased flexibility. Turn-Off Averaging For each temperature measurement read from a value register, 16 readings are made internally and the results are averaged before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. Table 9. Conversion Time with Averaging Disabled Measurement Time 0.7 ms 7 ms 7 ms 1.3 ms Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Register 0x6A to Register 0x6C are the THERM temperature limits. When a temperature exceeds its THERM temperature limit, all PWM outputs run at the maximum PWM duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A). This effectively runs the fans at the fastest allowed speed. The fans stay running at this speed until the temperature drops below THERM minus hysteresis. (This can be disabled by setting the boost bit in Configuration Register 3, Bit 2, Reg. 0x78.) The hysteresis value for that THERM temperature limit is the value programmed into Reg. 0x6D and Reg. 0x6E (hysteresis registers). The default hysteresis value is 4°C. THERM LIMIT HYSTERESIS (°C) TEMPERATURE FANS 100% Figure 27. THERM Temperature Limit Operation Rev. 3 | Page 21 of 81 | www.onsemi.com 04499-0-015 Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Bits Reg. 0x55 101 110 111 ADT7468 LIMITS, STATUS REGISTERS, AND INTERRUPTS LIMIT VALUES 16-Bit Limits Each measurement channel on the ADT7468 is associated with high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Because slow or stalled fans are normally the only conditions of interest, only high limits exist for fan TACHs. Because the fan TACH period is measured, exceeding the limit indicates a slow or stalled fan. 8-Bit Limits Fan Limit Registers Reg. 0x54, TACH1 minimum low byte = 0x00 default The following is a list of 8-bit limits on the ADT7468. Voltage Limit Registers Reg. 0x44, 2.5 V low limit = 0x00 default, Register 0x44 2.5 V low limit = 0x00 default Reg. 0x55, TACH1 minimum high byte = 0x00 default Reg. 0x56, TACH2 minimum low byte = 0x00 default Reg. 0x57, TACH2 minimum high byte = 0x00 default Reg. 0x45, 2.5 V high limit = 0xFF default Reg. 0x58, TACH3 minimum low byte = 0x00 default Reg. 0x46, VCCP low limit = 0x00 default Reg. 0x59, TACH3 minimum high byte = 0x00 default Reg. 0x47, VCCP high limit = 0xFF default Reg. 0x5A, TACH4 minimum low byte = 0x00 default Reg. 0x48, VCC low limit = 0x00 default Reg. 0x5B, TACH4 minimum high byte = 0x00 default Out-of-Limit Comparisons Reg. 0x49, VCC high limit = 0xFF default Once all limits have been programmed, the ADT7468 can be enabled for monitoring. The ADT7468 measures all voltage and temperature measurements in a round-robin format and sets the appropriate status bit for out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured value is compared to a high or low limit. Reg. 0x4A, 5 V low limit = 0x00 default Reg. 0x4B, 5 V high limit = 0xFF default Reg. 0x4C, 12 V low limit = 0x00 default Reg. 0x4D, 12 V high limit = 0xFF default Reg. 0x46, VCCP low limit = 0x00 default Reg. 0x47, VCCP high limit = 0xFF default High limit: > comparison performed Low limit: ≤ comparison performed Reg. 0x48, VCC low limit = 0x00 default Reg. 0x49, VCC high limit = 0xFF default Temperature Limit Registers Reg. 0x4E, Remote 1 temperature low limit = 0x01 default Reg. 0x4F, Remote 1 temperature high limit = 0x7F default Reg. 0x6A, Remote 1 THERM limit = 0x64 default Reg. 0x50, local temperature low limit = 0x01 default Reg. 0x51, local temperature high limit = 0x7F default Reg. 0x6B, local THERM limit = 0x64 default Reg. 0x52, Remote 2 temperature low limit = 0x01 default Reg. 0x53, Remote 2 Temperature high limit = 0x7F default Reg. 0x6C, Remote 2 THERM limit = 0x64 default THERM Limit Register Reg. 0x7A, THERM limit = 0x00 default Voltage and temperature channels use a window comparator for error detecting and therefore have high and low limits. Fan speed measurements use only a low limit, which is needed only in manual fan control mode. Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). By default, the ADT7463 powers up with this bit set. The ADC measures each analog input and as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. Since the ADC normally runs freely in this manner, the time taken to monitor all the analog inputs is usually not of interest, because the most recently measured value of any input can be read at any time. Rev. 3 | Page 22 of 81 | www.onsemi.com ADT7468 For applications where the monitoring cycle time is important, it can be calculated easily. Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has been exceeded. The measured channels are Bit 5 (LT) = 1, local temperature high or low limit has been exceeded. • Four dedicated supply voltage inputs • Supply voltage (VCC pin) • Local temperature • Two remote temperatures Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has been exceeded. Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded. Bit 2 (VCC) = 1, VCC high or low limit has been exceeded. As mentioned previously, the ADC performs round-robin conversions and takes 11 ms for each voltage measurement, 12 ms for a local temperature reading, and 39 ms for each remote temperature reading. The total monitoring cycle time for averaged voltage and temperature monitoring is, therefore, nominally (5 × 11) + 12 + (2 × 39) = 145 ms Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. STATUS REGISTERS Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded. Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. Status Register 2 (Reg. 0x42) Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs. Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs. Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum speed. Alternatively, indicates that the THERM limit has been exceeded, if the THERM function is used. Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum speed. The results of limit comparisons are stored in Status Registers 1 and 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limit, the corresponding status register bit is set to 1. Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum speed. The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event has been flagged in Status Register 2. This means that the user also needs to read Status Register 2. Alternatively, Pin 10 or Pin 14 can be configured as an SMBALERT output. This hard interrupt automatically notifies the system supervisor of an outof-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are sticky. The status bits are referred to as sticky, because they remain set until read by software. Whenever a status bit is set, indicating an out-oflimit condition, it remains set even if the event that caused it has ceased (until read). The only way to clear the status bit is to read the status register after the event has ceased. Interrupt status mask registers (0x74, and 0x75) allow individual interrupt sources to be masked from causing an SMBALERT. However, if one of these masked interrupt sources goes out-of-limit, its associated status bit is set in the interrupt status registers. Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been exceeded. If the VID code change function is used, this bit indicates a change in VID code on the VID0 to VID5 inputs. Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum speed. Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has been exceeded. INTERRUPTS SMBALERT Interrupt Behavior The ADT7468 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. HIGH LIMIT TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) “STICKY” STATUS BIT TEMP BACK IN LIMIT (STATUS BIT STAYS SET) Status Register 1 (Reg. 0x41) Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read. Rev. 3 | Page 23 of 81 | www.onsemi.com 04499-0-022 SMBALERT Figure 28. SMBALERT and Status Bit Behavior ADT7468 Figure 28 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. This ensures that an outof-limit event cannot be missed, if software is polling the device periodically. Note that the SMBALERT output remains low for the entire duration that a reading is out-of-limit and until the status register has been read. This has implications on how software handles the interrupt. Figure 29. How Masking the Interrupt Source Affects SMBALERT Output Interrupt Mask Register 1 (Reg. 0x74) Bit 7 (OOL) = 1, masks SMBALERT for any alert condition flagged in Status Register 2. Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature. Bit 5 (LT) = 1, masks SMBALERT for local temperature. Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature. Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel. Handling SMBALERT Interrupts Bit 2 (VCC) = 1, masks SMBALERT for VCC channel. To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: Bit 0 (VCCP) = 1, masks SMBALERT for VCCP channel. 1. Detect the SMBALERT assertion. 2. Enter the interrupt handler. 3. Read the status registers to identify the interrupt source. 4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (Reg. 0x74 and Reg. 0x75). Interrupt Mask Register 2 (Reg. 0x75) Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors. Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors. Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure. If the TACH4 pin is being used as the THERM input, this bit masks SMBALERT for a THERM event. Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3. Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2. 5. Take the appropriate action for a given interrupt source. Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1. 6. Exit the interrupt handler. 7. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 29. Bit 1 (OVT) = 1, masks SMBALERT for overtemperature (exceeding THERM temperature limits). Masking Interrupt Sources Interrupt Mask Registers 1 and 2 are located at Addresses 0x74 and 0x75. These allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set normally. Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or for a VID code change, depending on the function used. Enabling the SMBALERT Interrupt Output The SMBALERT interrupt function is disabled by default. Pin 10 or Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. Table 12. Configuring Pin 10 as SMBALERT Output Register Configuration Register 3 (Reg. 0x78) Assigning THERM Functionality to a Pin HIGH LIMIT Pin 14 on the ADT7468 has four possible functions: SMBALERT, THERM, GPIO, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D. TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) “STICKY” STATUS BIT INTERRUPT MASK BIT SET INTERRUPT MASK BIT CLEARED (SMBALERT REARMED) 04499-0-023 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) SMBALERT Bit Setting Pin 10 = alert Pin 10 = PWM2 Rev. 3 | Page 24 of 81 | www.onsemi.com ADT7468 If THERM is enabled (Bit 1, Configuration Register 3 at Address 0x78): THERM Timer • Pin 20 becomes THERM. • If Pin 14 is configured as THERM (Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D), then THERM is enabled on this pin. If THERM is not enabled: • The timer is started on the assertion of the ADT7468’s THERM input and stopped when THERM is unasserted. The timer counts THERM times cumulatively, that is, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared on read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. Pin 20 becomes a 5 V measurement input. • If Pin 14 is configured as THERM, then THERM is disabled on this Pin. Table 13. Configuring Pin 14 Bit 0 0 0 Bit 1 0 1 Function TACH4 THERM 1 0 SMBALERT 1 1 GPIO The ADT7468 has an internal timer to measure THERM assertion time. The THERM input can be connected to the PROCHOT output of a Pentium 4 CPU to measure system performance or be connected to the output of a trip point temperature sensor, to name a couple of functions of the timer. The 8-bit THERM timer register (Reg. 0x79) is designed such that Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time has exceeded 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 now becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 31). THERM as an Input When THERM is configured as an input, the user can time assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. When using the THERM timer, be aware of the following after a THERM timer read (Reg. 0x79): The user can also set up the ADT7468 to run the fans at 100% whenever the THERM pin is driven low externally by setting the boost bit (Bit 2) in Configuration Register 3 (Address 0x78) to 1. Note that to set this up, the fan must be already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above TMIN. If the temperature is below TMIN or if the duty cycle in manual mode is set to 0x00, then pulling the THERM low externally has no effect. See Figure 30 for more information. TMIN 1. The contents of the timer are cleared on read. 2. The F4P bit (Bit 5) of Status Register 2 needs to be cleared (assuming that the THERM timer limit has been exceeded). If the THERM timer is read during a THERM assertion, then the following happens: 1. The contents of the timer are cleared. 2. Bit 0 of the THERM timer is set to 1 (because a THERM assertion is occurring). 3. The THERM timer increments from 0. 4. If the THERM timer limit (Reg. 0x7A) = 0x00, then the F4P bit is set. THERM THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS ABOVE TMIN AND FANS ARE ALREADY RUNNING 04499-0-024 THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS BELOW TMIN Figure 30. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode Rev. 3 | Page 25 of 81 | www.onsemi.com ADT7468 Generating SMBALERT Interrupts from THERM Timer Events THERM The ADT7468 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions while capturing longer THERM timer events. Register 0x7A is the THERM timer limit register. This 8-bit register allows a limit from 0 secs (first THERM assertion) to 5.825 secs to be set before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM timer limit register. If the THERM timer value exceeds the THERM timer limit value, then the F4P bit (Bit 5) of Status Register 2 is set and an SMBALERT is generated. Note that the F4P bit (Bit 5) of Mask Register 2 (Reg. 0x75) masks out SMBALERTs if this bit is set to 1, although the F4P bit of Interrupt Status Register 2 stays set if the THERM timer limit is exceeded. THERM TIMER (REG. 0x79) 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED ≤ 22.76ms THERM ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 45.52ms THERM THERM TIMER (REG. 0x79) 0 0 0 0 0 1 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms (91.04ms + 22.76ms) 04499-0-025 ACCUMULATE THERM LOW ASSERTION TIMES Figure 31.Understanding the THERM Timer Figure 32 is a functional block diagram of the THERM timer, limit, and associated circuitry. Writing a value of 0x00 to the THERM timer limit register (Reg. 0x7A) causes SMBALERT to be generated on the first THERM assertion. A THERM timer limit value of 0x01 generates an SMBALERT, once cumulative THERM assertions exceed 45.52 ms. 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 THERM THERM TIMER CLEARED ON READ COMPARATOR IN OUT F4P BIT (BIT 5) STATUS REGISTER 2 SMBALERT LATCH RESET CLEARED ON READ 1 = MASK F4P BIT (BIT 5) MASK REGISTER 2 (REG. 0x75) Figure 32. Functional Block Diagram of THERM Monitoring Circuitry Rev. 3 | Page 26 of 81 | www.onsemi.com 04499-0-026 THERM LIMIT (REG. 0x7A) 2.914s 1.457s 728.32ms 364.16ms THERM TIMER (REG. 0x79) 182.08ms 91.04ms 45.52ms 22.76ms 2.914s 1.457s 728.32ms 364.16ms 182.08ms 91.04ms 45.52ms 22.76ms ADT7468 Configuring the Relevant THERM Behavior Configure the desired pin as the THERM timer input. Setting Bit 1 (THERM timer enable) of Configuration Register 3 (Reg. 0x78) enables the THERM timer monitoring functionality. This is disabled on Pins 14 and 20 by default. Setting Bits 0 and 1 (PIN14FUNC) of Configuration Register 4 (Reg. 0x7D) enables THERM timer output functionality on Pin 20 (Bit 1 of Configuration Register 3, THERM, must also be set). Pin 14 can also be used as TACH4. 2. Select the desired fan behavior for THERM timer events. Assuming that the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (Reg. 0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit is 0, the fans run at their current settings and are not affected by THERM events. If the fans are not already running when THERM is asserted, the fans do not run to full speed. 3. Select whether THERM timer events should generate SMBALERT interrupts. Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks out SMBALERTs when the THERM timer limit value is exceeded. This bit should be cleared, if SMBALERTs based on THERM events are required. 4. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated on the first THERM assertion, or only if a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated on the first THERM assertion. 5. Configuring the THERM Pin as an Output In addition to monitoring THERM as an input, the ADT7468 can optionally drive THERM low as an output. In cases where PROCHOT is bidirectional, THERM can be used to throttle the processor by asserting PROCHOT. The user can preprogram system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, after THERM asserts it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low, if the Remote 1, local, or Remote 2 THERM temperature limits are exceeded by 0.25°C. The THERM temperature limit registers are at Registers 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of Registers 0x5F, 0x60, and 0x61 enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 33 shows how the THERM pin asserts low as an output in the event of a critical overtemperature. THERM LIMIT +0.25°C THERM LIMIT TEMP THERM Select a THERM monitoring time. This value specifies how often OS or BIOS level software checks the THERM timer. For example, BIOS could read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is 182.08 ms in Hour 2, and >5.825 secs in Hour 3, this can indicate that system performance is degrading significantly, because THERM is asserting more frequently on an hourly basis. Alternatively, OS or BIOS level software can timestamp ADT7468 MONITORING CYCLE 04499-0-027 1. when the system is powered on. If an SMBALERT is generated due to the THERM timer limit being exceeded, another timestamp can be taken. The difference in time can be calculated for a fixed THERM timer limit time. For example, if it takes one week for a THERM timer limit of 2.914 secs to be exceeded and the next time it takes only one hour, then this is an indication of a serious degradation in system performance. Figure 33. Asserting THERM as an Output, Based on Tripping THERM Limits An alternative method of disabling THERM is to program the THERM temperature limit to –64°C or less in Offset 64 mode, or −128°C or less in twos complement mode; that is, for THERM temperature limit values less than –63°C or –128°C, respectively, THERM is disabled. Rev. 3 | Page 27 of 81 | www.onsemi.com ADT7468 Figure 34. Driving a 3-Wire Fan Using an N-Channel MOSFET DRIVING THE FAN USING PWM CONTROL The ADT7468 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive might need only a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in pull-up resistor. The ADT7468 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are usually used for 2-wire and 3-wire fans, while the high frequency option is usually used with 4-wire fans. For 2-wire or 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven and the input capacitance of the FET. Because a 10 kΩ (or greater) resistor must be used as a PWM pull-up, an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range. This is a requirement only when using high frequency PWM mode. Typical notebook fans draw a nominal 170 mA, and so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM_OUT pin. VGS can be greater than 3.3 V as long as the pull-up on the gate is tied to 5 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. Figure 34 uses a 10 kΩ pull-up resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 5 V maximum to prevent damaging the ADT7468. If in doubt as to whether the fan has an open-collector or totem-pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section. Figure 35 shows a fan drive circuit using an NPN transistor, such as a general-purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan’s current requirements. Ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. Because 4-wire fans are powered continuously, the fan speed is not switched on or off as with previous PWM driven/powered fans. This enables it to perform better than 3-wire fans, especially for high frequency applications. 12V 10kΩ 12V 10kΩ TACH 665Ω Q1 MMBT2222 PWM Figure 35. Driving a 3-Wire Fan Using an NPN Transistor Figure 36 shows a typical drive circuit for 4-wire fans. 12V 12V 12V, 4-WIRE FAN 10kΩ TACH/AIN VCC 10kΩ 4.7kΩ 3.3V TACH TACH PWM ADT7468 2kΩ 12V FAN PWM 1N4148 4.7kΩ 3.3V Figure 36. Driving a 4-Wire Fan ADT7468 Q1 NDT3055L 04499-0-028 10kΩ PWM 1N4148 Rev. 3 | Page 28 of 81 | www.onsemi.com 04499-0-041 10kΩ 12V FAN ADT7468 10kΩ TACH/AIN TACH 4.7kΩ 3.3V Figure 34 shows how to drive a 3-wire fan using PWM control. 12V 12V 04499-0-029 ACTIVE COOLING ADT7468 Driving Two Fans from PWM3 Driving up to Three Fans from PWM3 The ADT7468 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 37 shows how to drive two fans in parallel using low cost NPN transistors. Figure 38 shows the equivalent circuit using a MOSFET. TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, and therefore PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry is as shown in Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables this function. Because the MOSFET can handle up to 3.5 A, a second fan can be connected directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 5 mA maximum current specified in the data sheet. Synchronization is not required in high frequency mode when used with 4-wire fans. (SYNC) Enhance Acoustics Register 1 (Reg. 0x62) SYNC = 1, synchronizes TACH2, TACH3, and TACH4 to PWM3. 12V 3.3V 3.3V 1N4148 ADT7468 TACH3 1kΩ PWM3 2.2kΩ TACH4 Q1 MMBT3904 10Ω Q2 MMBT2222 04499-0-030 10Ω Q3 MMBT2222 Figure 37. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors 3.3V 10kΩ TYPICAL TACH4 +V 3.3V ADT7468 +V 10kΩ TYPICAL TACH3 3.3V TACH 5V OR 12V FAN 1N4148 TACH 5V OR 12V FAN PWM3 Q1 NDT3055L 04499-0-031 10kΩ TYPICAL Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET Rev. 3 | Page 29 of 81 | www.onsemi.com ADT7468 Driving 2-Wire Fans The ADT7468 can support 2-wire fans only when the low frequency PWM mode is selected in Configuration Register 5, Bit 2. If this bit is not set to 1, the ADT7468 cannot measure the speed of 2-wire fans. Figure 39 shows how a 2-wire fan can be connected to the ADT7468. This circuit allows the speed of a 2-wire fan to be measured, although the fan has no dedicated TACH signal. A series resistor, RSENSE, in the fan circuit converts the fan commutation pulses into a voltage, which is ac-coupled into the ADT7468 through the 0.01 µF capacitor. On-chip signal conditioning allows accurate monitoring of fan speed. The value of RSENSE chosen depends upon the programmed input threshold and the current drawn by the fan. For fans drawing approximately 200 mA, a 2 Ω RSENSE value is suitable when the threshold is programmed as 40 mV. For fans that draw more current, such as larger desktop or server fans, RSENSE can be reduced for the same programmed threshold. The smaller the threshold programmed the better, because more voltage is developed across the fan and the fan spins faster. Note that when the voltage spikes (either negative or positive) are more than 40 mV in amplitude, the fan speed can be reliably determined. LAYING OUT 2-WIRE AND 3-WIRE FANS Figure 41 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. Some components are not populated, depending on whether a 2-wire or 3-wire fan is used. 12V OR 5V R1 1N4148 3.3V OR 5V R2 R5 +V PWM TACH ADT7468 3.3V 1N4148 5V OR 12V FAN R3 10kΩ TYPICAL FOR 3-WIRE FANS: POPULATE R1, R2, R3 R4 = 0W C1 = UNPOPULATED Figure 41. Planning for 2-Wire or 3-Wire Fans on a PCB 0.01µF RSENSE 2Ω TYPICAL TACH Inputs 04499-0-032 TACH R4 FOR 2-WIRE FANS: POPULATE R4, C1 R1, R2, R3 UNPOPULATED Q1 NDT3055L PWM Q1 MMBT2222 04499-0-042 C1 Pins 9, 11, 12, and 14 (when configured as TACH inputs) are open-drain TACH inputs intended for fan speed measurement. Figure 39. Driving a 2-Wire Fan Figure 40 shows a typical plot of the sensing waveform at the TACH/AIN pin. Signal conditioning in the ADT7468 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even when VCC is less than 5 V. When these inputs are supplied from fan outputs that exceed 0 V to 5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 42 to Figure 45 show circuits for most common fan TACH outputs. If the fan TACH output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 42. VCC 12V TACH OUTPUT 04499-0-033 TACH FAN SPEED COUNTER ADT7468 Figure 42. Fan with TACH Pull-Up to VCC Figure 40. Fan Speed Sensing Waveform at TACH/AIN Pin Rev. 3 | Page 30 of 81 | www.onsemi.com 04499-0-034 PULL-UP 4.7kΩ TYPICAL ADT7468 If the fan output has a resistive pull-up to 12 V (or other voltage greater than 5 V) then the fan output can be clamped with a Zener diode, as shown in Figure 43. The Zener diode voltage should be chosen so that it is greater than VIH of the TACH input but less than 5 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5 V is suitable. VCC PULL-UP 4.7kΩ TYPICAL TACH OUTPUT TACH ZD1* FAN SPEED COUNTER ADT7468 *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC 04499-0-035 12V Figure 43. Fan with TACH Pull-Up Greater than 5 V, for example, 12 V), Clamped with Zener Diode If the fan has a strong pull-up ( OP1 OPERATING POINT TEMPERATURE OP1 04499-0-079 Remote 2 = CYR2 = Bits of Calibration Control Register 2 and Bit 0 of Calibration Control Register 1 (Address = 0x36). 04499-0-078 Local = CYL = Bits of Calibration Control Register 2 (Address = 0x37). DO NOTHING (SYSTEM IS COOLING OF FOR CONSTANT) YES IS T1(n) – T1(n – 1) = 0.5 – 0.75°C IS T1(n) – T1(n – 1) = 1.0 – 1.75°C IS T1(n) – T1(n – 1) > 2.0°C DECREASE TMIN BY 1°C DECREASE TMIN BY 2°C DECREASE TMIN BY 4°C Figure 71. Short Cycle Steps Figure 72 shows the steps taken during the long cycle. The following examples illustrate some of the circumstances that might cause TMIN to increase, decrease, or stay the same. Normal Operation—No TMIN Adjustment 1. If measured temperature never exceeds the programmed operating point minus the hysteresis temperature, then TMIN is not adjusted, that is, remains at its current setting. 2. If measured temperature never drops below the low temperature limit, then TMIN is not adjusted. 04499-0-077 NO Operating Point Exceeded—TMIN Reduced When the measured temperature is below the operating point temperature minus the hysteresis, TMIN remains the same. Once the temperature exceeds the operating temperature minus the hysteresis (OP − Hyst), TMIN starts to decrease. This occurs during the short cycle (see Figure 71). The rate at which TMIN decreases depends on the programmed value of n. It also depends on how much the temperature has increased between this monitoring cycle and the last monitoring cycle, that is, if the temperature has increased by 1°C, then TMIN is reduced by 2°C. Decreasing TMIN has the effect of increasing the fan speed, thus providing more cooling to the system. If the temperature is slowly increasing only in the range (OP − Hyst), that is, ≤0.25°C per short monitoring cycle, then TMIN does not decrease. This allows small changes in temperature in the desired operating zone without changing TMIN. The long cycle makes no change to TMIN in the temperature range (OP − Hyst), because the temperature has not exceeded the operating temperature. Rev. 3 | Page 54 of 81 | www.onsemi.com ADT7468 Once the temperature exceeds the operating temperature, the long cycle causes TMIN to be reduced by 1°C every long cycle while the temperature remains above the operating temperature. This takes place in addition to the decrease in TMIN that would occur due to the short cycle. In Figure 74, because the temperature is increasing at a rate ≤0.25°C per short cycle, no reduction in TMIN takes place during the short cycle. Once the temperature has fallen below the operating temperature, TMIN stays the same. Even when the temperature starts to increase slowly, TMIN stays the same, because the temperature increases at a rate ≤0.25°C per cycle. TMIN can increase if • The measured temperature has fallen below the low temperature limit. This means the user must choose the low limit carefully. It should not be so low that the temperature never falls below it, because TMIN would never increase and the fans would run faster than necessary. • TMIN is below the high temperature limit. TMIN is never allowed to increase above the high temperature limit. As a result, the high limit should be carefully chosen, because it determines how high TMIN can go. • TMIN is below the operating point temperature. TMIN should never be allowed to increase above the operating point temperature, because the fans would not switch on until the temperature rose above the operating point. • The temperature is above TMIN. The dynamic TMIN control is turned off below TMIN. Increasing the TMIN Cycle When the temperature drops below the low temperature limit, TMIN can increase in the long cycle. Increasing TMIN has the effect of running the fan slower and, therefore, quieter. The long cycle diagram in Figure 74 shows the conditions that need to be true for TMIN to increase. Here is a quick summary of those conditions and the reasons they need to be true. THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS ACTUAL TEMP TMIN NO CHANGE IN T MIN HERE DUE TO ANY CYCLE, BECAUSE T1(n) – T1 (n – 1) ≤ 0.25°C AND T1(n) < OP = > TMIN STAYS THE SAME LOW TEMP LIMIT DECREASE HERE DUE TO LONG CYCLE ONLY T1(n) – T1 (n – 1) ≤ 0.25°C AND T1(n) > OP = > TMIN DECREASES BY 1°C EVERY LONG CYCLE 04499-0-080 DECREASE HERE DUE TO SHORT CYCLE ONLY T1(n) – T1 (n – 1) = 0.5°C OR 0.75°C = > T MIN DECREASES BY 1°C EVERY SHORT CYCLE Figure 74. Effect of Exceeding Operating Point Minus Hysteresis Temperature THERM LIMIT HIGH TEMP LIMIT OPERATING POINT LOW TEMP LIMIT HYSTERESIS ACTUAL TEMP 04499-0-081 Figure 75 shows how TMIN increases when the current temperature is above TMIN and below the low temperature limit, and TMIN is below the high temperature limit and below the operating point. Once the temperature rises above the low temperature limit, TMIN stays the same. TMIN Figure 75. Increasing TMIN for Quieter Operation Rev. 3 | Page 55 of 81 | www.onsemi.com ADT7468 Preventing TMIN from Reaching Full Scale Because TMIN is dynamically adjusted, it is undesirable for TMIN to reach full scale (127°C), because the fan would never switch on. As a result, TMIN is allowed to vary only within a specified range: The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. 1. The lowest possible value for TMIN is –127°C (twos complement mode) or −64°C (Offset 64 mode). 2. TMIN cannot exceed the high temperature limit. 3. If the temperature is below TMIN, the fan is switched off or is running at minimum speed, and dynamic TMIN control is disabled. PHTL = 1, copies the local current temperature to the local temperature operating point register, if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. THERM LIMIT LOW TEMP LIMIT ACTUAL TEMP HIGH TEMP LIMIT TMIN PHTL = 0, ignores any THERM assertions. The local temperature operating point register reflects its programmed value. HYSTERESIS TMIN PREVENTED FROM INCREASING 04499-0-082 OPERATING POINT PHTR2 = 0, ignores any THERM assertions. The Remote 2 operating point register reflects its programmed value. Figure 76. TMIN Adjustments Limited by the High Temperature Limit STEP 11: MONITORING THERM Using the operating point limit ensures that the dynamic TMIN control mode is operating in the best possible acoustic position while ensuring that the temperature never exceeds the maximum operating temperature. Using the operating point limit allows TMIN to be independent of system level issues because of its self-corrective nature. In PC design, the operating point for the chassis is usually the worst-case internal chassis temperature. The optimal operating point for the processor is determined by monitoring the thermal monitor in the Intel Pentium 4 processor. To do this, the PROCHOT output of the Pentium 4 is connected to the THERM input of the ADT7468. The operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the PROCHOT output pulls the THERM input low on the ADT7468. This gives the maximum temperature at which the Pentium 4 can run before clock modulation occurs. Enabling the THERM Trip Point as the Operating Point Bits of dynamic TMIN control Register 1 (Reg. 0x36) enable/disable THERM monitoring to program the operating point. Dynamic TMIN Control Register 1 (0x36) PHTR2 = 1, copies the Remote 2 current temperature to the Remote 2 operating point register, if THERM is asserted. PHTR1 = 1, copies the Remote 1 current temperature to the Remote 1 operating point register, if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTR1 = 0, ignores any THERM assertions. The Remote 1 operating point register reflects its programmed value. Enabling Dynamic TMIN Control Mode Bits of dynamic TMIN control Register 1 (Reg. 0x36) enable/disable dynamic TMIN control on the temperature channels. Dynamic TMIN Control Register 1 (0x36) R2T = 1, enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R2T = 0, disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section. LT = 1, enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. LT = 0, disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section. R1T = 1, enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0, disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section. Rev. 3 | Page 56 of 81 | www.onsemi.com ADT7468 STEP 12: RAMP RATE FOR ACOUSTIC ENHANCEMENT The optimal ramp rate for acoustic enhancement can be found through system characterization after the thermal optimization has been finished. The effect of each ramp rate should be logged, if possible, to determine the best setting for a given solution. settings, it takes approximately 0.76 secs to go from 33% duty cycle to 100% duty cycle (full speed). Even though the temperature increases very rapidly, the fan ramps up to full speed gradually. 140 120 RTEMP (°C) 120 100 100 80 Enhanced Acoustics Register 1 (Reg. 0x62) 80 ACOU, selects the ramp rate for PWM1. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots =3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec 60 60 PWM CYCLE (%) 40 40 0 0 0 0.76 TIME (s) 04499-0-086 20 20 Figure 77. Enhanced Acoustics Mode with Ramp Rate = 48 Figure 78 shows how changing the ramp rate from 48 to 8 affects the control loop. The overall response of the fan is slower. Because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. In this case, it takes approximately 4.4 sec for the fan to reach full speed. Enhance Acoustics Register 2 (Reg. 0x63) ACOU3, selects the ramp rate for PWM3. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots = 3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec 120 140 RTEMP (°C) 120 100 100 80 PWM DUTY CYCLE (%) 80 60 60 40 40 20 20 0 0 4.4 TIME (s) 0 04499-0-087 ACOU2, selects the ramp rate for PWM2. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots = 3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec Figure 78. Enhanced Acoustics Mode with Ramp Rate = 8 Figure 79 shows the PWM output response for a ramp rate of 2. In this instance, the fan took about 17.6 sec to reach full running speed. 140 120 RTEMP (°C) Another way to view the ramp rates is to measure the time it takes for the PWM output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. This can be tested by putting the ADT7468 into manual mode and changing the PWM output from 0% to 100% PWM duty cycle. The PWM output takes 35 secs to reach 100%, when a ramp rate of one time slot is selected. 120 Figure 77 shows remote temperature plotted against PWM duty cycle for enhanced acoustics mode. The ramp rate is set to 48, which corresponds to the fastest ramp rate. Assume that a new temperature reading is available every 115 ms. With these 20 100 100 80 80 PWM DUTY CYCLE (%) 60 60 40 40 0 0 TIME (s) 17.6 0 Figure 79. Enhanced Acoustics Mode with Ramp Rate = 2 Rev. 3 | Page 57 of 81 | www.onsemi.com 04499-0-088 20 ADT7468 Figure 80 shows how the control loop reacts to temperature with the slowest ramp rate. The ramp rate is set to 1, while all other control parameters remain the same. With the slowest ramp rate selected, it takes 35 sec for the fan to reach full speed. 140 120 RTEMP (°C) 120 100 100 80 80 60 60 PWM DUTY CYCLE (%) 40 40 20 0 0 35 TIME (s) 04499-0-089 20 0 Figure 80. Enhanced Acoustics Mode with Ramp Rate = 1 As Figure 77 to Figure 80 show, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. The higher the ramp rate, the faster the fan reaches the newly calculated fan speed. Figure 81 shows the behavior of the PWM output as temperature varies. As the temperature increases, the fan speed ramps up. Small drops in temperature do not affect the ramp-up function, because the newly calculated fan speed is still higher than the previous PWM value. Enhanced acoustics mode allows the PWM output to be made less sensitive to temperature variations. This is dependent on the ramp rate selected and programmed into the enhanced acoustics registers. 90 80 70 PWM DUTY CYCLE (%) 60 50 40 Slower Ramp Rates The ADT7468 can be programmed for much longer ramp times by slowing the ramp rates. Each ramp rate can be slowed by a factor of 4. PWM1 Configuration Register (Reg. 0x5C) slow, 1 slows the ramp rate for PWM1 by 4. PWM2 Configuration Register (Reg. 0x5D) slow, 1 slows the ramp rate for PWM2 by 4. PWM3 Configuration Register (Reg. 0x5E) slow, 1 slows the ramp rate for PWM3 by 4. The following sections list the ramp-up times when the slow bit is set for each PWM output. Enhanced Acoustics Register 1 (Reg. 0x62) ACOU, selects the ramp rate for PWM1. 000 = 140 sec 001 = 70.4 sec 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec Enhance Acoustics Register 2 (Reg. 0x63) ACOU3, selects the ramp rate for PWM3. 000 = 140 sec 001 = 70.4 sec 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec ACOU2, selects the ramp rate for PWM2. 000 = 140 sec RTEMP (°C) 30 001 = 70.4 sec 04499-0-090 20 10 0 Figure 81. How Fan Reacts to Temperature Variation in Enhanced Acoustics Mode 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec Rev. 3 | Page 58 of 81 | www.onsemi.com ADT7468 ENHANCING SYSTEM ACOUSTICS Automatic fan speed control mode reacts instantaneously to changes in temperature, that is, the PWM duty cycle responds immediately to temperature change. Any impulses in temperature can cause an impulse in fan noise. For psycho-acoustic reasons, the ADT7468 can prevent the PWM output from reacting instantaneously to temperature changes. Enhanced acoustic mode controls the maximum change in PWM duty cycle at a given time. The objective is to prevent the fan from cycling up and down, annoying the user. ACOUSTIC ENHANCEMENT MODE OVERVIEW Figure 82 gives a top-level overview of the automatic fan control circuitry on the ADT7468 and shows where acoustic enhancement fits in. Acoustic enhancement is intended as a postdesign tweak made by a system or mechanical engineer evaluating best settings for the system. Having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. The goal is to implement a system that is acoustically acceptable without causing user annoyance due to fan cycling. It is important to realize that although a system might pass an acoustic noise requirement specification (for example, 36 dB), if the fan is annoying, it fails the consumer test. ACOUSTIC ENHANCEMENT PWM MIN 100% PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT) TMIN REMOTE 2 = CPU TEMP TRANGE THERMAL CALIBRATION PWM MIN 100% LOCAL = VRM TEMP TRANGE THERMAL CALIBRATION TMIN PWM MIN 0% TACHOMETER 1 MEASUREMENT RAMP CONTROL (ACOUSTIC ENHANCEMENT) 0% 100% TRANGE PWM1 0% MUX TMIN PWM GENERATOR TACHOMETER 2 MEASUREMENT RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT TACH1 PWM CONFIG PWM GENERATOR CPU FAN SINK PWM2 TACH2 PWM CONFIG FRONT CHASSIS PWM GENERATOR PWM3 TACH3 REMOTE 1 = AMBIENT TEMP REAR CHASSIS Figure 82. Acoustic Enhancement Smoothes Fan Speed Variations under Automatic Fan Speed Control Rev. 3 | Page 59 of 81 | www.onsemi.com 04499-0-083 THERMAL CALIBRATION ADT7468 The fan-centric approach to system acoustic enhancement controls the PWM duty cycle, driving the fan at a fixed rate (for example, 6%). Each time the PWM duty cycle is updated, it is incremented by a fixed 6%. As a result, the fan ramps smoothly to its newly calculated speed. If the temperature starts to drop, the PWM duty cycle immediately decreases by 6% at every update. Therefore, the fan ramps smoothly up or down without inherent system delay. Consider, for example, controlling the same CPU cooler fan (on PWM1) and chassis fan (on PWM2) using Remote 1 temperature. The TMIN and TRANGE settings have already been defined in automatic fan speed control mode, that is, thermal characterization of the control loop has been optimized. Now the chassis fan is noisier than the CPU cooling fan. Using the fan-centric approach, PWM2 can be placed into acoustic enhancement mode independently of PWM1. The acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the CPU cooling fan, although both fans are controlled by Remote 1 temperature. Enabling Acoustic Enhancement for Each PWM Output Enhance Acoustics Register 1 (Reg. 0x62) = 1, enables acoustic enhancement on PWM1 output Enhance Acoustics Register 2 (Reg. 0x63) = 1, enables acoustic enhancement on PWM2 output = 1, enables acoustic enhancement on PWM3 output Effect of Ramp Rate on Enhanced Acoustics Mode The PWM signal driving the fan has a period, T, given by the PWM drive frequency, f, because T = 1/f. For a given PWM PWM_OUT 33% DUTY CYCLE 85 TIME SLOTS 170 TIME SLOTS 04499-0-084 The temperature-centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, Remote 1 temperature). The temperature values used to calculate the PWM duty cycle values are smoothed, reducing fan speed variation. However, this approach causes an inherent delay in updating fan speed and causes the thermal characteristics of the system to change. It also causes the system fans to stay on longer than necessary, because the fan’s reaction is merely delayed. The user has no control over noise from different fans driven by the same temperature source. Consider, for example, a system in which control of a CPU cooler fan (on PWM1) and a chassis fan (on PWM2) use Remote 1 temperature. Because the Remote 1 temperature is smoothed, both fans are updated at exactly the same rate. If the chassis fan is much louder than the CPU fan, there is no way to improve its acoustics without changing the thermal solution of the CPU cooling fan. period, T, the PWM period is subdivided into 255 equal time slots. One time slot corresponds to the smallest possible increment in the PWM duty cycle. A PWM signal of 33% duty cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3 × 255 time slots. Therefore, a 33% PWM duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots. PWM OUTPUT (ONE PERIOD) = 255 TIME SLOTS Figure 83. 33% PWM Duty Cycle Represented in Time Slots The ramp rates in the enhanced acoustics mode are selectable from the values 1, 2, 3, 5, 8, 12, 24, and 48. The ramp rates are discrete time slots. For example, if the ramp rate is 8, then eight time slots are added to the PWM high duty cycle each time the PWM duty cycle needs to be increased. If the PWM duty cycle value needs to be decreased, it is decreased by eight time slots. Figure 84 shows how the enhanced acoustics mode algorithm operates. READ TEMPERATURE CALCULATE NEW PWM DUTY CYCLE IS NEW PWM VALUE > PREVIOUS VALUE? NO DECREMENT PREVIOUS PWM VALUE BY RAMP RATE YES INCREMENT PREVIOUS PWM VALUE BY RAMP RATE 04499-0-085 Approaches to System Acoustic Enhancement There are two different approaches to implementing system acoustic enhancement: temperature-centric and fan-centric. The ADT7468 uses the fan-centric approach. Figure 84. Enhanced Acoustics Algorithm The enhanced acoustics mode algorithm calculates a new PWM duty cycle based on the temperature measured. If the new PWM duty cycle value is greater than the previous PWM value, then the previous PWM duty cycle value is incremented by either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhance acoustics registers. If the new PWM duty cycle value is less than the previous PWM value, then the previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. Each time the PWM duty cycle is incremented or decremented, its value is stored as the previous PWM duty cycle for the next comparison. A ramp rate of 1 corresponds to one time slot, which is 1/255 of the PWM period. In enhanced acoustics mode, incrementing or decrementing by 1 changes the PWM output by 1/255 × 100%. Rev. 3 | Page 60 of 81 | www.onsemi.com ADT7468 REGISTER TABLES Table 17. Register Map Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable 0x20 R 2.5 V measurement 9 8 7 6 5 4 3 2 0x00 No 0x21 R VCCP measurement 9 8 7 6 5 4 3 2 0x00 No 0x22 R VCC measurement 9 8 7 6 5 4 3 2 0x00 No 0x23 R 5 V measurement 9 8 7 6 5 4 3 2 0x00 No 0x24 R 12 V measurement 9 8 7 6 5 4 3 2 0x00 No 0x25 R Remote 1 Temperature 9 8 7 6 5 4 3 2 0x01 No 0x26 R Local Temperature 9 8 7 6 5 4 3 2 0x01 No 0x27 R Remote 2 Temperature 9 8 7 6 5 4 3 2 0x01 No 0x28 R TACH1 Low Byte 7 6 5 4 3 2 1 0 0x00 No 0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00 No 0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 0x00 No 0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00 No 0x2C R TACH3 Low Byte 7 6 5 4 3 2 1 0 0x00 No 0x2D R TACH3 High Byte 15 14 13 12 11 10 9 8 0x00 No 0x2E R TACH4 Low Byte 7 6 5 4 3 2 1 0 0x00 No 0x2F R TACH4 High Byte 15 14 13 12 11 10 9 8 0x00 No 0x30 R/W PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 0x00 No 0x31 R/W PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 0x00 No 0x32 R/W PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 0x00 No 0x33 R/W Remote 1 Operating Point 7 6 5 4 3 2 1 0 0xA4 Yes 0x34 R/W Local Temp Operating Point 7 6 5 4 3 2 1 0 0xA4 Yes 0x35 R/W Remote 2 Operating Point 7 6 5 4 3 2 1 0 0xA4 Yes 0x36 R/W Dynamic TMIN Control Reg. 1 R2T LT R1T PHTR2 PHTL PHTR1 VCCPLO CYR2 0x00 Yes 0x37 R/W Dynamic TMIN Control Reg. 2 CYR2 CYR2 CYL CYL CYL CYR1 CYR1 CYR1 0x00 Yes 0x38 R/W Max PWM 1 Duty Cycle 7 6 5 4 3 2 1 0 0xFF Yes 0x39 R/W Max PWM 2 Duty Cycle 7 6 5 4 3 2 1 0 0xFF Yes 0x3A R/W Max PWM 3 Duty Cycle 7 6 5 4 3 2 1 0 0xFF Yes 0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x68 No 0x3E R Company ID Number 7 6 5 4 3 2 1 0 0x41 No 0x3F R Revision Number VER VER VER VER STP STP STP STP 0x71/0x72 No 0x40 R/W Configuration 1 VCC = 5V TODIS FSPDIS VxI FSPD RDY LOCK STRT 0x01 Yes 0x41 R Interrupt Status 1 OOL R2T LT R1T 5 V/THERM Timer Limit VCC VCCP 2.5 V 0x00 No 0x42 R Interrupt Status 2 D2 FAULT D1 FAULT FAN4/ THERM FAN3 FAN2 FAN1 THERM Temp Limit 12 V/VC 0x00 No 0x43 R/W VID Config VIDSEL THLD VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 0x00 No 0x44 R/W 2.5 V Low Limit 7 6 5 4 3 2 1 0 0x00 No 0x45 R/W 2.5 V High Limit 7 6 5 4 3 2 1 0 0xFF No 0x46 R/W VCCP Low Limit 7 6 5 4 3 2 1 0 0x00 No 0x47 R/W VCCP High Limit 7 6 5 4 3 2 1 0 0xFF No Rev. 3 | Page 61 of 81 | www.onsemi.com ADT7468 Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x48 R/W VCC Low Limit 7 6 5 4 3 2 1 0 0x00 No 0x49 R/W VCC High Limit 7 6 5 4 3 2 1 0 0xFF No 0x4A R/W 5 V Low Limit 7 6 5 4 3 2 1 0 0x00 No 0x4B R/W 5 V High Limit 7 6 5 4 3 2 1 0 0xFF No 0x4C R/W 12 V Low Limit 7 6 5 4 3 2 1 0 0x00 No 0x4D R/W 12 V High Limit 7 6 5 4 3 2 1 0 0xFF No 0x4E R/W Remote 1 Temp Low Limit 7 6 5 4 3 2 1 0 0x01 No 0x4F R/W Remote 1 Temp High Limit 7 6 5 4 3 2 1 0 0x7F No 0x50 R/W Local Temp Low Limit 7 6 5 4 3 2 1 0 0x01 No 0x51 R/W Local Temp High Limit 7 6 5 4 3 2 1 0 0x7F No 0x52 R/W Remote 2 Temp Low Limit 7 6 5 4 3 2 1 0 0x01 No 0x53 R/W Remote 2 Temp High Limit 7 6 5 4 3 2 1 0 0x7F No 0x54 R/W TACH1 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF No 0x55 R/W TACH1 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF No 0x56 R/W TACH2 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF No 0x57 R/W TACH2 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF No 0x58 R/W TACH3 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF No 0x59 R/W TACH3 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF No 0x5A R/W TACH4 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF No 0x5B R/W TACH4 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF No 0x5C R/W PWM1 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes 0x5D R/W PWM2 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes 0x5E R/W PWM3 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes 0x5F R/W Remote 1 TRANGE/PWM 1 Frequency RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes 0x60 R/W Local TRANGE/PWM 2 Frequency RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes 0x61 R/W Remote 2 TRANGE/PWM3 Frequency RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes 0x62 R/W Enhance Acoustics Reg. 1 MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0X00 Yes 0x63 R/W Enhance Acoustics Reg. 2 EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0X00 Yes 0x64 R/W PWM1 Min Duty Cycle 7 6 5 4 3 2 1 0 0X80 Yes 0x65 R/W PWM2 Min Duty Cycle 7 6 5 4 3 2 1 0 0X80 Yes 0x66 R/W PWM3 Min Duty Cycle 7 6 5 4 3 2 1 0 0X80 Yes 0x67 R/W Remote 1 Temp TMIN 7 6 5 4 3 2 1 0 0X9A Yes 0x68 R/W Local Temp TMIN 7 6 5 4 3 2 1 0 0X9A Yes 0x69 R/W Remote 2 Temp TMIN 7 6 5 4 3 2 1 0 0X9A Yes Rev. 3 | Page 62 of 81 | www.onsemi.com Lockable ADT7468 Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable 0x6A R/W Remote 1 THERM Temp Limit 7 6 5 4 3 2 1 0 0XA4 Yes 0x6B R/W Local THERM Temp Limit 7 6 5 4 3 2 1 0 0XA4 Yes 0x6C R/W Remote 2 THERM Temp Limit 7 6 5 4 3 2 1 0 0XA4 Yes 0x6D R/W Remote 1 and Local Temp/TMIN Hysteresis HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0X44 Yes 0x6E R/W Remote 2 Temp/TMIN Hysteresis HYSR2 HYSR2 HYSR2 HYRS RES RES RES RES 0X40 Yes 0x6F R/W XNOR Tree Test Enable RES RES RES RES RES RES RES XEN 0X00 Yes 0x70 R/W Remote 1 Temperature Offset 7 6 5 4 3 2 1 0 0X00 Yes 0x71 R/W Local Temperature Offset 7 6 5 4 3 2 1 0 0X00 Yes 0x72 R/W Remote 2 Temperature Offset 7 6 5 4 3 2 1 0 0X00 Yes 0x73 R/W Configuration Register 2 SHDN CONV ATTN AVG AIN4 AIN3 AIN2 AIN1 0X00 Yes 0x74 R/W Interrupt Mask 1 Register OOL R2T LT RIT 5V VCC VCCP 2.5 V 0X00 No 0x75 R/W Interrupt Mask 2 Register D2 D1 F4P FAN3 FAN2 FAN1 OVT 12 V / VC 0X00 No 0x76 R/W Extended Resolution 1 5V 5V VCC VCC VCCP VCCP 2.5 V 2.5 V 0X00 No 0x77 R/W Extended Resolution 2 TDM2 TDM2 LTMP LTMP TDM1 TDM1 12 V 12 V 0X00 No 0x78 R/W Configuration Register 3 DC4 DC3 DC2 DC1 FAST BOOST THERM ALERT Enable 0X00 Yes 0x79 R THERM Timer Status Register TMR TMR TMR TMR TMR TMR TMR ASRT/TMRO 0X00 No 0x7A R/W THERM Timer Limit Register LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0X00 No 0x7B R/W TACH Pulses per Revolution FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0X55 No 0x7C R/W Configuration Register 5 RES RES RES RES GPIOP GPIOD LF/HF TWOS COMPL 0X00 Yes 0x7D R/W Configuration Register 4 BpAtt 12 V BpAtt 5V BpAtt VCCP BpAtt 2.5 V AINL AINL Pin 14 Func Pin 14 Func 0X00 Yes 0x7E R Test Register 1 DO NOT WRITE TO THESE REGISTERS 0X00 Yes 0x7F R Test Register 2 DO NOT WRITE TO THESE REGISTERS 0X00 Yes Table 18. Voltage Reading Registers (Power-On Default = 0x00) Register Address R/W 1 Description 0x20 Read only Reflects the voltage measurement at the 2.5 V input on Pin 22 (8 MSBs of reading). 0x21 Read only Reflects the voltage measurement2 at the VCCP input on Pin 23 (8 MSBs of reading). 0x22 Read only Reflects the voltage measurement3 at the VCC input on Pin 4 (8 MSBs of reading). 0x23 Read only Reflects the voltage measurement at the 5 V input on Pin 20 (8 MSBs of reading. 0x24 Read only Reflects the voltage measurement at the 12 V input on Pin 21 (8 MSBs of reading). 1 If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2 If VCCPLow (Bit 1 of the Dynamic TMIN Control Register 1, 0x36) is set, VCCP can control the sleep state of the ADT7468. 3 VCC (Pin 4) is the supply voltage for the ADT7468. Rev. 3 | Page 63 of 81 | www.onsemi.com ADT7468 Table 19. Temperature Reading Registers (Power-On Default = 0x01)1, 2, 3 Register Address 0x25 R/W Read only 0x26 0x27 Read only Read only Description Remote 1 temperature reading3, 4 (8 MSBs of reading). Local temperature reading (8 MSBs of reading). Remote 2 temperature reading3, 4 (8 MSBs of reading). 1 If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2 These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C). 3 In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel. 4 In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel. Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)1 Register Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F R/W Read only Read only Read only Read only Read only Read only Read only Read only Description TACH1 low byte TACH1 high byte TACH2 low byte TACH2 high byte TACH3 low byte TACH3 high byte TACH4 low byte TACH4 high byte 1 These registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following: • Stalled or blocked (object jamming the fan). • Failed (internal circuitry destroyed). • Not populated. (The ADT7468 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be set to 0xFFFF.) • Alternate function, for example, TACH4 reconfigured as THERM pin. • 2-wire instead of 3-wire fan. Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0x00)1 Register Address 0x30 0x31 0x32 1 R/W Read/write Read/write Read/write Description PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7468 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers. Table 22. Operating Point Registers (Power-On Default = 0x64)1, 2, 3 Register Address 0x33 0x34 0x35 R/W3 Read/write Read/write Read/write Description Remote 1 operating point register (default = 100°C). Local temperature operating point register (default = 100°C). Remote 2 operating point register (default = 100°C). 1 These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled. The fans being controlled are adjusted to maintain temperature about an operating point. 3 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. 2 Rev. 3 | Page 64 of 81 | www.onsemi.com ADT7468 Table 23. Register 0x36—Dynamic TMIN Control Register 1 (Power-On Default = 0x00)1 Bit Name CYR2 R/W Read/write VCCPLO Read/write Description MSB of 3-bit remote 2 cycle value. The other two bits of the code reside in Dynamic TMIN Control Register 2 (Reg. 0x37). These three bits define the delay time between making subsequent TMIN adjustments in the control loop, in terms of the number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP low limit value (Reg. 0x46), the following occurs: • Status Bit 1 in Status Register 1 is set. • SMBALERT is generated, if enabled. • PROCHOT monitoring is disabled. PHTR1 Read/write PHTL Read/write PHTR2 Read/write R1T Read/write LT Read/write R2T Read/write 1 • Dynamic TMIN control is disabled. • The device is prevented from entering shutdown. • Everything is re-enabled once VCCP increases above the VCCP low limit. PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register, if THERM is asserted. The operating point contains the temperature at which THERM is asserted, which allows the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point register reflects its programmed value. PHTL = 1 copies the local channel’s current temperature to the local operating point register, if THERM is asserted. The operating point contains the temperature at which THERM is asserted, which allows the system to run as quietly as possible without affecting system performance. PHTL = 0 ignores any THERM assertions on the THERM pin. The local operating temperature point register reflects its programmed value. PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register, if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point register reflects its programmed value. R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section. LT=1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section. R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Rev. 3 | Page 65 of 81 | www.onsemi.com ADT7468 Table 24. Register 0x37—Dynamic TMIN Control Register 2 (Power-On Default = 0x00)1 Bit Name CYR1 R/W Read/write Description 3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. CYL Bits 000 001 010 011 100 101 110 111 Read/write Decrease Cycle Increase Cycle 8 cycles (1 sec) 16 cycles (2 sec) 16 cycles (2 sec ) 32 cycles (4 sec) 32 cycles (4 sec) 64 cycles (8 sec) 64 cycles (8 sec) 128 cycles (16 sec) 128 cycles (16 sec) 256 cycles (32 sec) 256 cycles (32 sec) 512 cycles (64 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) 3-bit local temperature cycle value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the local temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. CYR2 Bits 000 001 010 011 100 101 110 111 Read/write Decrease Cycle Increase Cycle 8 cycles (1 sec) 16 cycles (2 sec) 16 cycles (2 sec) 32 cycles (4 sec) 32 cycles (4 sec) 64 cycles (8 sec) 64 cycles (8 sec) 128 cycles (16 sec) 128 cycles (16 sec) 256 cycles (32 sec) 256 cycles (32 sec) 512 cycles (64 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) 2 LSBs of 3-bit Remote 2 cycle value. The MSB of the 3-bit code resides in Dynamic TMIN Control Register 1 (Reg. 0x36). These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 2 channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bits 000 001 010 011 100 101 110 111 Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 25. Maximim PWM Duty Cycle (Power-On Default = 0xFF)1, 2 Register Address 0x38 0x39 0x3A 1 2 R/W2 Read/write Read/write Read/write Description Maximum duty cycle for PWM1 output, default = 100% (0xFF). Maximum duty cycle for PWM2 output, default = 100% (0xFF). Maximum duty cycle for PWM3 output, default = 100% (0xFF). These registers set the maximum PWM duty cycle of the PWM output . This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Rev. 3 | Page 66 of 81 | www.onsemi.com ADT7468 Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x01) Bit Name STRT R/W Read/write LOCK Write once RDY Read-only FSPD VxI Read/write Read/write FSPDIS Read/write TODIS Read/write VCC Read/write Description Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit becomes read-only and cannot be changed once Bit 1 (LOCK bit) has been written. All limit registers should be programmed by BIOS before setting this bit to 1. (Lockable.) Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the ADT7468 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.) This bit is set to 1 by the ADT7468 to indicate only that the device is fully powered-up and ready to begin system monitoring. When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit never gets locked. BIOS should set this bit to a 1 when the ADT7468 is configured to measure current from an ADI ADOPT™ VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display CPU watts usage. (lockable.) Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spin-up timeout selected. When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7468 to be used with SMBus controllers that cannot handle SMBus timeouts. (lockable.) When this bit is set to 1, the ADT7468 rescales its VCC pin to measure 5 V supply. If this bit is 0, the ADT7468 measures VCC as a 3.3 V supply. (lockable.) Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00) Bit Name 2.5 V R/W Read only VCCP Read only VCC Read only Read only 5 V/ THERM timer R1T LT Read only R2T Read only OOL Read only Read only Description 2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. A one indicates the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. If Pin 20 is configured as THERM, this bit is asserted when the timer limit has been exceeded. R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. LT =1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which saves the need to read Status Register 2 during every interrupt or polling cycle. Rev. 3 | Page 67 of 81 | www.onsemi.com ADT7468 Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00) Bit Name 12V/VC R/W Read only Description A one indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. If Pin 21 is configured as VID5, this bit is the VID change bit. This bit is set when the levels on VID0 to VID5 are different than they were 11 µs previously. This pin can be used to generate an SMBALERT whenever the VID code changes. OVT Read only OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below THERM − THYST. FAN1 Read only FAN2 Read only FAN3 Read only F4P Read only FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the PWM 1 output is off. FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the PWM 2 output is off. FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the PWM 3 output is off. When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. When Pin 14 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO. If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A). D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs. Read/write Read only D1 D2 Read only Read only Table 29. Register 0x43-VID Register (Power-On Default = 0x00) Bit Name VID[4:0] R/W Read-only VID5 Read-only THLD Read/write VIDSEL Read/write Description The VID[4:0] inputs from the CPU indicate the expected processor core voltage. On power-up, these bits reflect the state of the VID pins, even if monitoring is not enabled. Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always reads back 0 (power-on default). Selects the input switching threshold for the VID inputs. THLD = 0 selects a threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V). THLD = 1 lowers the switching threshold to 0.6 V (VOL < 0.4 V, VIH > 0.8 V). VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default). Table 30. Voltage Limit Registers1 Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 1 2 R/W Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Description2 2.5 V 2.5 V VCCP low limit VCCP high limit VCC low limit VCC high limit 5 V low limit 5 V high limit 12 V low limit 12 V high limit Power-On Default 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Setting the Configuration Register 1 lock bit has no effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit (≤comparison). Rev. 3 | Page 68 of 81 | www.onsemi.com ADT7468 Table 31. Temperature Limit Registers1 Register Address 0x4E 0x4F 0x50 0x51 0x52 0x53 1 2 R/W Description2 Power-On Default Read/write Read/write Read/write Read/write Read/write Read/write Remote 1 temperature low limit Remote 1 temperature high limit Local temperature low limit Local temperature high limit Remote 2 temperature low limit Remote 2 temperature high limit 0x81 0x7F 0x81 0x7F 0x81 0x7F Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit has no effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its low limit (≤comparison). Table 32. Fan Tachometer Limit Registers1 Register Address 0x54 R/W Read/write 0x55 Read/write 0x56 0x57 0x58 0x59 0x5A 0x5B Read/write Read/write Read/write Read/write Read/write Read/write 1 Description TACH1 minimum low byte TACH1 minimum high byte/Single channel ADC channel select TACH2 minimum low byte TACH2 minimum high byte TACH3 minimum low byte TACH3 minimum high byte TACH4 minimum low byte TACH4 minimum high byte Power-On Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers. Table 33. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF) Bits Name Reserved R/W Read only SCADC Read/write Description These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode). Otherwise, these bits represent Bits of the TACH1 minimum high byte. When Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode), these bits are used to select the only channel from which the ADC makes measurements. Otherwise, these bits represent Bits of the TACH1 minimum high byte. Rev. 3 | Page 69 of 81 | www.onsemi.com ADT7468 Table 34. PWM Configuration Registers Register Address 0x5C 0x5D 0x5E R/W1 Read/write Read/write Read/write Description PWM1 configuration. PWM2 configuration. PWM3 configuration. Description These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Status Register 2 bit is not set, even if the fan has not started. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 secs 111 = 4 secs SLOW = 1 makes the ramp rates for acoustic enhancement four times longer. This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low output. These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed. 100 = PWMx disabled (default). 101 = fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = fastest speed calculated by all three temperature channel controls PWMx. 111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become writable. Bit Name SPIN R/W Read/write SLOW INV Read/write Read/write BHVR Read/write 1 Power-On Default 0x82 0x82 0x82 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. Rev. 3 | Page 70 of 81 | www.onsemi.com ADT7468 Table 35. TEMP TRANGE/PWM Frequency Registers Register Address 0x5F 0x60 0x61 R/W1 Read/write Read/write Read/write Description Remote 1 TRANGE/PWM1 frequency. Local temperature TRANGE/PWM2 frequency. Remote 2 TRANGE/PWM3 frequency. Bit Name FREQ R/W Read/write THRM Read/write RANGE Read/write Description These bits control the PWMx frequency. 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz THRM = 1 causes the THERM pin (Pin 14/20) to assert low as an output when this temperature channel’s THERM limit has been exceeded by 0.25°C. The THERM pin remains asserted until the temperature is equal to or below the THERM limit. The minimum time that THERM asserts is one monitoring cycle. This allows clock modulation of devices that incorporate this feature. THRM = 0 makes the THERM pin act as an input only, for example, for Pentium 4 PROCHOT monitoring, when Pin 14/20 is configured as THERM. These bits determine the PWM duty cycle vs. the temperature slope for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (Default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C 1 Power-On Default 0xC4 0xC4 0xC4 These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect. Rev. 3 | Page 71 of 81 | www.onsemi.com ADT7468 Table 36. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00) Bit Name ACOU R/W1 Read/write EN1 SYNC Read/write Read/write MIN1 Read/write MIN2 Read/write MIN3 Read/write Description These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 4 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, acoustic enhancement is enabled on PWM1 output. SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. When the ADT7468 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM1 minimum duty cycle below TMIN – hysteresis. When the ADT7468 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM 2 minimum duty cycle below TMIN – hysteresis. When the ADT7468 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM3 minimum duty cycle below TMIN – hysteresis. 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Rev. 3 | Page 72 of 81 | www.onsemi.com ADT7468 Table 37. Register 0x63 – Enhanced Acoustics Register 2 (Power-On Default = 0x00) Bit 1 Name ACOU3 EN3 ACOU2 EN2 R/W1 Read/write Read/write Read/write Read/write Description These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, acoustic enhancement is enabled on PWM3 output. These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec When this bit is 1, acoustic enhancement is enabled on PWM2 output. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 38. PWM Minimum Duty Cycle Registers Register Address 0x64 0x65 0x66 R/W1 Read/write Read/write Read/write Description PWM1 minimum duty cycle. PWM2 minimum duty cycle. PWM3 minimum duty cycle. Bit R/W1 Read/write Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% duty cycle (fan off). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed). Name PWM duty cycle Power-On Default 0x80 (50% duty cycle) 0x80 (50% duty cycle) 0x80 (50% duty cycle) 1 These registers become read-only when the ADT7468 is in automatic fan control mode. Table 39. TMIN Registers1 Register Address 0x67 0x68 0x69 R/W2 Read/write Read/write Read/write Description Remote 1 temperature TMIN. Local temperatue TMIN. Remote 2 temperature TMIN. 1 Power-On Default 0x5A (90°C) 0x5A (90°C) 0x5A (90°C) These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases with temperature according to TRANGE. 2 These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect. Rev. 3 | Page 73 of 81 | www.onsemi.com ADT7468 Table 40. THERM Limit Registers1 Register Address R/W2 0x6A 0x6B Read/write Description Remote 1 THERM limit. 0x64 (100°C) Read/write Local THERM limit. 0x64 (100°C) 0x6C Read/write Remote 2 THERM limit. 0x64 (100°C) Power-On Default 1 If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM limit – hysteresis. If the THERM pin is programmed as an output, then exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output. 2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect. Table 41. Temperature/TMIN Hysteresis Registers1 Register Address 0x6D R/W2 Read/write HYSL HYSR1 0x6E Read/write HYSR2 Description Remote 1 and local temperature hysteresis. Local temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the local temperature AFC and dynamic TMIN control loops. Remote 1 temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the Remote 1 temperature AFC and dynamic TMIN control loops. Remote 2 temperature hysteresis. Local temperature hyseresis. 0°C to 15°C of hysteresis can be applied to the local temperature AFC and dynamic TMIN control loops. Power-On Default 0x44 0x40 1 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN. 2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect. Table 42. XNOR Tree Test Enable Register Address 0x6F R/W1 Read/write XEN Reserved 1 Description XNOR tree test enable register. If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode. Unused. Do not write to these bits. Power-On Default 0x00 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 43. Remote 1 Temperature Offset Register Address 0x70 1 R/W1 Read/write Read/write Description Remote 1 temperature offset. Allows a twos complement offset value to be automatically added to or subtracted from the Remote 1 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C. Power-On Default 0x00 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Rev. 3 | Page 74 of 81 | www.onsemi.com ADT7468 Table 44. Local Temperature Offset Register Address 0x71 1 R/W1 Read/write Read/write Description Local temperature offset. Allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. LSB value = 0.5°C. Power-On Default 0x00 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 45. Remote 2 Temperature Offset Register Address 0x72 1 R/W1 Read/write Read/write Description Remote 2 temperature offset. Allows a twos complement offset value to be automatically added to or subtracted from the Remote 2 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C. Power-On Default 0x00 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 46. Register 0x73—Configuration Register 2 (Power-On Default = 0x00) Bit Name R/W1 Description 0 AIN1 Read/write 1 AIN2 Read/write 2 AIN3 Read/write 3 AIN4 Read/write 4 AVG Read/write 5 ATTN Read/write 6 CONV Read/write AIN1 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN1 = 1, Pin 6 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). Only relevant in low frequency mode. AIN2 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN2 = 1, Pin 7 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). Only relevant in low frequency mode. AIN3 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN3 = 1, Pin 4 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). Only relevant in low frequency mode. AIN4 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN4 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). Only relevant in low frequency mode. AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster. ATTN = 1, the ADT7468 removes the attenuators from the 2.5 V, VCCP, 5 V, and 12 V inputs. These inputs can be used for other functions such as connecting up external sensors. It is possible to remove attenuators from individual channels using Bits of Configuration Register 4 (0x7D). CONV = 1, the ADT7468 is put into a single-channel ADC conversion mode. In this mode, the ADT7468 can be made to read continuously from one input only, for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits of TACH1 minimum high byte register (0x55). Bits Reg. 0x55 000 2.5 V 001 VCCP 010 VCC (3.3 V) 011 5V 100 12 V 101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature 7 1 SHDN Read/write SHDN = 1, ADT7468 goes into shutdown mode. All PWM outputs assert low (or high depending on state of INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to indicate that the fans are not being driven. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Rev. 3 | Page 75 of 81 | www.onsemi.com ADT7468 Table 47. Register 0x74—Interrupt Mask Register 1 (Power-On Default = 0x00) Bit 0 Name 2.5V R/W Read/write Description 2.5 V = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V channel. 1 VCCP Read/write VCCP = 1, masks SMBALERT for out-of-limit conditions on the VCCP channel. 2 VCC Read/write VCC = 1, masks SMBALERT for out-of-limit conditions on the VCC channel. 3 5V Read/write 5 V = 1, masks SMBALERT for out-of-limit conditions on the 5 V channel. 4 RIT Read/write RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. 5 LT Read/write LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel. 6 R2T Read/write R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. 7 OOL Read/write OOL = 1, masks SMBALERT for any out-of-limit condition in Status Register 2. Table 48. Register 0x75—Interrupt Mask Register 2 (Power-On Default = 0x00) Bit Name R/W 0 12V/VC Read/write 1 OVT Read only Description When Pin 21 is configured as a 12 V input, 12V/VC = 1 masks SMBALERT for out-of-limit conditions on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT, if the VID5 VID code bit changes. OVT = 1, masks SMBALERT for overtemperature THERM conditions. 2 FAN1 Read/write FAN1 = 1, masks SMBALERT for a Fan 1 fault. 3 FAN2 Read/write FAN2 = 1, masks SMBALERT for a Fan 2 fault. 4 5 FAN3 F4P Read/write Read/write FAN3 = 1, masks SMBALERT for a Fan 3 fault. 6 D1 Read/write If Pin 14 is configured as TACH 4, F4P = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit. If Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is asserted. D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. 7 D2 Read/write D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel. Table 49. Register 0x76—Extended Resolution Register 11 Bit 1 Name 2.5V VCCP VCC 5V R/W Read only Read only Read only Read only Description 2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement. VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement. VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement. 5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 50. Register 0x77—Extended Resolution Register 21 Bit 1 Name 12V TDM1 LTMP TDM2 R/W Read only Read only Read only Read only Description 12 V LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement. Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Rev. 3 | Page 76 of 81 | www.onsemi.com ADT7468 Table 51. Register 0x78—Configuration Register 3 (Power-On Default = 0x00) Bit Name ALERT R/W1 Read/write THERM Read/write THERM Enable = 1 enables THERM functionality on Pin 20 and Pin 14, if Pin 14 is configured as THERM, determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is asserted, if the fans are running and the boost bit is set, the fans run at full speed. Alternatively, THERM can be programmed so that a timer is triggered to time how long THERM has been asserted. BOOST Read/write FAST Read/write DC1 Read/write DC2 Read/write DC3 Read/write DC4 Read/write When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4 ×). DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC3 = 1, enables TACH measurements to be continuously made on TACH3. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC4 = 1, enables TACH measurements to be continuously made on TACH4. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. 1 Description ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 52. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00) Bit Name TMR R/W Read only ASRT/ TMR0 Read only Description Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time exceeds 45.52 ms. This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 secs to be reported back with a resolution of 22.76 ms. Table 53. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00) Bit Name LIMT R/W Read/write Description Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 secs to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately on the assertion of the THERM input. Rev. 3 | Page 77 of 81 | www.onsemi.com ADT7468 Table 54. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55) Bit Name FAN1 FAN2 FAN3 FAN4 R/W Read/write Read/write Read/write Read/write Description Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Table 55. Register 0x7C—Configuration Register 5 (Power-On Default = 0x00) Bit Name 2sC HF/LF GPIOD GPIOP RES R/W1 Read/write Description 2sC = 1, sets the temperature range to twos complement temperature range. 2sC = 0, changes the temperature range to Offset 64. When this bit is changed, the ADT7468 interprets all relevant temperature register values as defined by this bit. Sets the PWM drive frequency to high frequency mode (0) or low frequency mode (1). GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an output (1). GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit determines whether the GPIO is active low (0) or high (1). Unused. 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Rev. 3 | Page 78 of 81 | www.onsemi.com ADT7468 Table 56. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00) Bit Name PIN14FUNC R/W1 Read/write Description These bits set the functionality of Pin 14: 00 = TACH4 (default) 01 = Bidirectional THERM 10 = SMBALERT AINL BpAtt2.5V BpAttVCCP BpAtt5V BpAtt12V 1 Read/write 11 = GPIO These two bits define the input threshold for 2-wire fan speed measurements (low frequency mode only): 00 = ±20 mV 01 = ±40 mV 10 = ±80 mV 11 = ±130 mV Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.2965 V (0xFF). Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.2965 V (0xFF). Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.2965 V (0xFF). Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.2965 V (0xFF). This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 57. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00) Bit Name Reserved R/W Read only Description Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not be written to under normal operation. Table 58. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00) Bit Name Reserved R/W Read only Description Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not be written to under normal operation. Rev. 3 | Page 79 of 81 | www.onsemi.com ALLOW SELECTED PWM TO TURN OFF WHEN TEMP IS BELOW TMIN–HYST SYNC FAN SPEED MEASUREMENTS ENABLE SELECTED PWM RAMP-UP SPEED TEMPERATURE HYSTERESIS (THYST) (0x6D, 0x6E) Figure 85. Rev. 3 | Page 80 of 81 | www.onsemi.com 04498-0-044 16°C 88.2Hz 80°C 53.33°C 40°C 32°C 26.67°C 20°C 10°C 13.33°C 58.8Hz 8°C 35.3Hz 44.1Hz 5°C 6.67°C 4°C 14.7Hz 29.4Hz 3.33°C 11.0Hz 22.1Hz 2.5°C 2°C THERM IS INPUT/OUTPUT THERM AS OVERTEMP OUTPUT THERM AS (TIMER) INPUT AUTOMATIC FAN CONTROL 0.8s (33%-100%) 1.6s (33%-100%) 3s (33%-100%) 1s 2s 4s 3 PULSE PER REV 4 PULSE PER REV XNOR Test (0x6F) THERM TEMP LIMITS (0x6A, 0x6B, 0x6C) AVERAGE TEMP AND VOLTAGE MEASUREMENTS (SEE CONFIGURATION 2, 0x73) VCCP HIGH LIMIT (0x47) VCCP LOW LIMIT (0x46) VCCP LOW (SLEEP) CYXX TMIN ADJUSTMENT CYCLE TIME ENABLE DYNAMIC TMIN CONTROL ON INDIVIDUAL CHANNEL REMOTE 1 TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) FASTEST SPEED CALCULATED BY ALL 3 TEMPERATURE CHANNEL CONTROLS THERM GENERAL INTERRUPT FANS VOLTAGES TEMPERATURE 2048 CYCLES (256s) 1024 CYCLES (128s) 512 CYCLES (64s) 256 CYCLES (32s) 128 CYCLES (16s) 64 CYCLES (8s) 32 CYCLES (4s) 16 CYCLES (2s) DECREASE CYCLE TIME 64 CYCLES (8s) 32 CYCLES (4s) 16 CYCLES (2s) 8 CYCLES (1s) 1024 CYCLES (128s) 512 CYCLES (64s) 256 CYCLES (32s) BYPASS VCCP ATTENUATOR TMIN THYST COOLING TRANGE = SLOPE THYST MIN PWM 0% DUTY CYCLE TWOS COMPLEMENT OFFSET 64 F4P T THERM HEATING AUTOMATIC FAN CONTROL TEMPERATURE GPIO POLARITY GPIO DIRECTION FAN DRIVE HIGH/LOW FREQUENCY MODE 100% DUTY CYCLE MAX PWM ±130mV ±80mV ±40mV INPUT THRESHOLD FOR 2-WIRE FANS (AINL) (ONLY USED WHEN FANS ARE POWERED BY DC AND NOT PWM) GPIO SMBALERT THERM TACH 4 TEMPERATURE RANGE CONFIGURATION 5 (0X7C) ±20mV SMBALERT PWM 2 SET PIN 14/20 FUNCTIONALITY THERM SMBALERT MASK INTERRUPT? (0x74,0x75) INTERRUPT STATUS (0x41, 0x42) DRIVE PWM OUTPUTS HIGH/LOW SHUTDOWN SINGLE CHANNEL ADC MODE RESCALE VCCP INPUT (5V/3.3V) AVERAGE TEMP AND VOLTAGE MEASUREMENTS MEASURE FROM 2- OR 3WIRE FANS INTERRUPTS ON STATUS REGISTER 2 HARDWARE INTERRUPTS FAN FAULT DIODE FAULT. FOR REMOTE CHANNELS ONLY TEMPERATURE MEASURED IS OUT OF LIMITS THERM TIMER LIMIT HAS BEEN EXCEEDED ENABLE CONTINUOUS FAN SPEED MEASUREMENT CONFIGURE PIN 10 FAST TACH MEASUREMENTS CONFIGURATION 4 (0x7D) RESCALE VCC (5V/3.3V) RUN FANS AT FULLSPEED READY LOCK SETTINGS TEMPERATURE MEASUREMENT HIGH LIMIT LOW LIMIT (0X4E-0X53) TEMPERATURE OFFSET (0x70-0x72) SOFTWARE INTERRUPTS TEMPERATURE MEASUREMENT (0X25, 0X26,0X27) START MONITORING CONFIGURATION 1 (0X40) THERM BOOST (FAN MUST BE RUNNING) ENABLE THERM 128 CYCLES (16s) CONFIGURATION 3 (0x78) MANUAL MODE. PWM DUTY CYCLE REGISTERS (0x30-0x32) BECOME WRITABLE CHANGE CYCLE TIME INCREASE CYCLE TIME MEASUREMENT LSBs (0X77) IF THESE REGISTERS ARE USED, ALL TEMPERATURE MEASUREMENT MSB REGISTERS ARE FROZEN UNTIL ALL TEMPERATURE MEASUREMENT MSB REGISTERS ARE READ. FASTEST SPEED CALCULATED BY LOCAL AND REMOTE 2 TEMP CONTROLS SELECTED PWM DRIVE SELECTED PWM DRIVE DISABLED (DEFAULT) SELECTED PWM DRIVE RUNS FULL SPEED REMOTE 2 TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) VCC HIGH LIMIT (0x49) VCC LOW LIMIT (0x48) MEASUREMENT MSBs (0x25-0x27) VCC MEASUREMENT (0x22) LOCAL TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) PHTXX CURRENT TEMPERATURE OF SELECTED CHANNEL IS COPIED TO RELEVANT OPERATING POINT REGISTER ON ASSERTION OF THERM VCCP MEASUREMENT (0x47) THERM TIMER STATUS (0x79) THERM TIMER LIMIT (0x7A) DYNAMIC TMIN CONTROL (0x36, 0x37) PWMMIN DUTY CYCLE (AUTOMATIC MODE ONLY) (0X64-0X66) PWM DUTY CYCLE (MANUAL MODE ONLY) (0x30-0x32) MAX FAN SPEED (MAX PWM DUTY CYCLE) (0x38-0x3A) 667ms 1 PULSE PER REV 2 PULSE PER REV 400ms 100ms NO TIMEOUT 4.4s (33%-100%) FAN SPINUP TIMEOUT FAN BEHAVIOR 250ms (DEFAULT) FAN TACH PULSES PER REV (0x7B) INVERT PWM OUTPUT SLOW IMPROVED ACOUSTIC RAMP-UP 7s (33%-100%) 18s (33%-100%) PWM CONFIGURATION (0x5C-0x5E) FANTACH 16-BIT MINIMUM LIMIT (0X54-0X5B) ADT7467/ADT7468 PROGRAMMING BLOCK DIAGRAM PWM FREQUENCY 35s (33%-100%) 17.6s (33%-100%) TRANGE TEMP TRANGE ,PWM FREQ,THERMENABLE (0x5F, 0x60, 0x61) OPERATING POINT (0x33-0x35) FAN 16-BIT MEASUREMENT (0x28-0x2F) LOW BYTE MUST BE READ FIRST. WHEN THE LOW BYTE IS READ, REGISTERS ARE LOCKED UNTIL THE ASSOCIATED HIGH BYTE IS READ. TMIN. MIN TEMP THAT CAUSES SELECTED FANS TO RUN (0x67-0x69) ENHANCE ACOUSTICS (0x62,0x63) SELECTED PWM RAMP-UP SPEED LOCAL TEMP REMOTE TEMP2 REMOTE TEMP1 VCC PWM DUTY CYCLE/RELATIVE FAN SPEED VCCP CONFIGURATION 2 (0X73) ADT7468 PROGRAMMING BLOCK DIAGRAM ADT7468 OUTLINE DIMENSIONS 0.341 BSC 24 13 0.154 BSC 1 0.236 BSC 12 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AE Figure 86. 24-Lead Shrink Small Outline Package [QSOP] (RQ-24) Dimensions shown in inches ORDERING GUIDE Model ADT7468ARQ ADT7468ARQ-REEL ADT7468ARQ-REEL7 ADT7468ARQZ1 ADT7468ARQZ-REEL1 ADT7468ARQZ-RL71 EVAL-ADT7468EB 1 Temperature Range –40°C to +120°C –40°C to +120°C –40°C to +120°C –40°C to +120°C –40°C to +120°C –40°C to +120°C Package Description 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP Evaluation Board Package Option RQ-24 RQ-24 RQ-24 RQ-24 RQ-24 RQ-24 Z = Pb-free part. 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