AMIS-39100

AMIS-39100 Octal High Side Driver with Protection General Description The AMIS−39100 is a general purpose IC with eight integrated high side (HS) output drivers. The device is designed to control the power of virtually any type of load in a 12 V automotive environment, such as transistor gates, relays, LEDs etc. Each of the output drivers of the AMIS−39100 is able to drive up to 275 mA continuously when connected to an inductive load of 300 mH. Even higher driver output currents can be obtained as long as the total current of the device is limited. The integrated charge−pump of the AMIS−39100, which uses only one low cost external capacitor, avoids thermal runaways even if the battery voltage is low. The HS drivers withstand short to ground (even when AMIS−39100 has lost its ground connection), short to the battery and has overcurrent limitation. In case of a potential hazardous situation, the drivers are switched off and the diagnostic state of the HS drivers can be read out via serial peripheral interface (SPI). In case of a short to ground, the output driver is deactivated after a de−bounce time. The AMIS −39100 can be connected to a 3.3 V or 5 V microcontroller by means of a SPI interface. This SPI interface is used to control each of the output drivers individually (on or off) and to read the status of each individual output driver (read−back of possible error conditions). This allows the detection of error situations for each driver individually. Furthermore, the SPI interface can be used to read−back the status of the built−in thermal shutdown protection. The AMIS−39100 has a low−power mode and excellent handling and system ESD characteristics. Features http://onsemi.com PIN ASSIGNMENT TEST1 CLK WR OUT1 VB1 OUT2 GND1 GND2 OUT3 VB2 OUT4 DIN DOUT TEST2 1 2 3 4 5 AMIS−39100 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND6 VDDN PDB OUT8 VB4 OUT7 GND5 GND4 OUT6 VB3 OUT5 CAPA1 TEST GND3 (Top View) PC20070110.1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. • Eight HS drivers • Up to 830 mA Continuous Current Per Driver Pair • • • • • • • • • • • (Resistive Load) Charge Pump with One External Capacitor Serial peripheral interface (SPI) Short−Circuit Protection Diagnostic Features Powerdown Mode Internal Thermal Shutdown 3.3 V and 5 V Microcontroller Compliant Excellent System ESD Automotive Compliant SOIC 28 Package with Low Rthja This is a Pb−Free Device* Typical Applications • • • • • • Automotive Dashboard Automotive Load Management Actuator Control LED Driver Applications Relays and Solenoids Industrial Process Control *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 January, 2009 − Rev. 2 1 Publication Order Number: AMIS−39100/D AMIS−39100 VDDN 27 5 Power on Reset OUT1 VB1 4 OUT1 Thermal shutdown OUT2 6 10 OUT2 VB2 DIN DOUT CLK WR 12 13 2 3 11 OUT4 SPI interface OUT3 9 OUT3 Diagnostic LOGIC Control OUT4 19 VB3 OUT5 Oscillator 18 OUT5 OUT6 CAPA1 17 Charge− pump OUT7 20 24 OUT6 VB4 23 OUT7 Bandgap OUT8 25 OUT8 AMIS−39100 26 1 14 16 7 8 15 21 22 28 PC20070110.4 TEST2 PDB TEST1 TEST GND3 GND5 GND1 GND4 GND6 GND2 Figure 1. Block Diagram http://onsemi.com 2 AMIS−39100 Table 1. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name TEST1 CLK WR OUT1 VB1 OUT2 GND1 GND2 OUT3 VB2 OUT4 DIN DOUT TEST2 GND3 TEST CAPA1 OUT5 VB3 OUT6 GND4 GND5 OUT7 VB4 OUT8 PDB VDDN GND6 Connect to GND Schmitt Trigger SPI CLK Input Schmitt Trigger SPI Write Enable Input HS Driver Output Battery Supply HS Driver Output Power Ground and Thermal Dissipation Path Junction−to−PCB Power Ground and Thermal Dissipation Path Junction−to−PCB HS Driver Output Battery Supply HS Driver Output SPI Input Pin (Schmitt trigger or CMOS inverter) Digital Three State Output for SPI Connect to GND Power Ground and Thermal Dissipation Path Junction−to−PCB Connect to GND Charge Pump Capacitor Pin HS Driver Output Battery Supply HS Driver Output Power Ground and Thermal Dissipation Path Junction−to−PCB Power Ground and Thermal Dissipation Path Junction−to−PCB HS Driver Output Battery Supply HS Driver Output Schmitt Trigger Powerdown Input Digital Supply Power Ground and Thermal Dissipation Path Junction−to−PCB Description http://onsemi.com 3 AMIS−39100 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VDDN VB Iout_ON Iout_OFF I_OUT_VB Vcapa1 Vdig_in VESD VESD TJ Tmr Power Supply Voltage DC Battery Supply on Pins VB1 to VB4 Load Dump, Pulse 5b 400 ms Maximum Output Current OUTx Pins (Note 1) The HS Driver is Switched On Maximum Output Current OUTx Pins (Note 1) The HS Driver is Switched Off Maximum Output Current VB1, 2, 3, 4 Pins DC Voltage on Pins capa1 Voltage on Digital Inputs CLK, PDB, WR, DIN Pins that Connect the Application (Pins VB1 − 8 and Out1 − 8) (Note 2) All Other Pins (Note 2) ESD According Charged Device Model (Note 3) Junction Temperature (T < 100 hours) Ambient Temperature Under Bias Description Min GND − 0.3 GND − 0.3 −3000 −350 −700 0 −0.3 −4 −2 −750 −40 −40 Max 6 35 350 350 3750 VB + 16.5 VDDN + 0.3 +4 +2 +750 175 105 Unit V V mA mA mA V V kV V °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The power dissipation of the chip must be limited not to exceed the maximum junction temperature Tj. 2. According to Human Body Model (HBM) standard MIL−STD−883 method 3015.7 3. According to norm EOS/ESD−STM5.3.1−1999 robotic mode Table 3. THERMAL CHARACTERISTICS OF THE PACKAGE Symbol Rth(vj−a) Description Thermal Resistance from Junction−to−Ambient in Power SOIC 28 Package Conditions In Free Air Value 145 Unit K/W Table 4. THERMAL CHARACTERISTICS OF THE AMIS−39100 ON A PCB PCB Design Two Layer (35 mm) Two Layer (35 mm) Four Layer JEDEC: EIA/JESD51−7 One Layer JEDEC: EIA/JESD51−3 Conductivity Top and Bottom Layer Copper Planes According Figure 3 to +25% Popper for the Remaining Areas Copper Planes According to Figure 3 0% Popper for the Remaining Areas 25% Copper Coverage 25% Copper Coverage Rthja (Note 4) 24 53 25 46 Unit K/W K/W K/W K/W 4. These values are informative only. Rthja = Thermal Resistance from Junction−to−Ambient Table 5. OPERATING RANGES Symbol VDDN Vdig_in VB (Note 5) TA Digital Power Supply Voltage Voltage on Digital Inputs CLK, PDB, WR, DIN DC Battery Supply on Pins VB1 to VB4 Ambient Temperature Description Min 3.1 −0.3 3.5 −40 Max 5.5 VDDN 16 105 Unit V V V °C 5. The power dissipation of the chip must be limited not to exceed maximum junction temperature TJ of 130°C. http://onsemi.com 4 AMIS−39100 TYPICAL APPLICATION DIAGRAM VBAT 5V−reg CVCC CVDDN CVB CAPA CCP 5 VB1..4 10 19 24 VCC VDDN 27 17 Micro− controller DIN 12 DOUT 13 CLK 2 WR 3 PDB 26 1 14 16 28 22 21 15 4 OUT1 Lload1 Cout1 Rload1 AMIS−39100 6 9 11 18 20 23 25 87 OUT8 Lload8 Cout8 Rload8 GND TEST1..2 GND1..6 PC20070110.2 Figure 2. Typical Application Diagram External Components It is important to properly decouple the power supplies of the chip with external capacitors that have good high frequency properties. The VB1, VB2, VB3, and VB4 pins are shorted on the PCB level. Also GND1, GND2, GND3, GND4, GND5, GND6, TEST, TEST1, and TEST2 are shorted on the PCB level. Table 6. EXTERNAL COMPONENTS Component CVB Ccharge_pump Cout (Note 7) Cout (Note 7) CVDD RLoad LLoad Function Decoupling Capacitor; X7R Charge Pump Capacitor (Note 6) EMC Capacitor on Connector Decoupling Capacitors on OUT 1 to 8; 50 V Decoupling Capacitors; 50 V Load Resistance Load Inductance at Maximum Current Min 100 0.47 1 22 22 65 300 350 $20 $20 $10 47 Value Max Tol [%] $20 Unit nF nF nF nF nF W mH 6. The capacitor must be placed close to the AMIS−39100 pins on the PCB. 7. Both capacitors are optional and depend on the final application and board layout. http://onsemi.com 5 AMIS−39100 Top PCB view 5 mm 5 mm 5 mm Bottom PCB view 114.3 5 mm GND copper Ground plane GND copper 25 % filled by GND copper 114.3 76.2 76.2 Figure 3. Layout Recommendation for Thermal Characteristics ELECTRICAL AND ENVIRONMENTAL RATINGS ELECTRICAL PARAMETERS Operation outside the operating ranges for extended periods may affect device reliability. Total cumulative dwell time above the maximum operating rating for the power supply or temperature must be less than 100 hours. The parameters below are independent from load type (see Section “Load Specific Parameters”). Table 7. ELECTRICAL CHARACTERISTICS Symbol I_VB_norm (Note 8) I_PDB_3.3 (Notes 8 and 9) Description Consumption on VB Without Load Currents In Normal Mode of Operation PDB = High Sum of VB and VDDN Consumption in Powerdown Mode of Operation PDB = Low, VDDN 3.3 V, VB = 12 V, 23°C Ambient CLK and WR are at VDDN Voltage Sum of VB and VDDN Consumption in Powerdown Mode of Operation PDB = low, VDDN 5 V, VB = 24 V, 23°C Ambient CLK and WR are at VDDN Voltage VB Consumption in Powerdown Mode of Operation PDB = Low, VB = 16 V Consumption on VDDN In Normal Mode of Operation PDB = High CLK is 500 kHz, VDDN = 5.5 V, VB = 16 V On Resistance of the Output Drivers 1 through 8 Vb= 16 V (Normal Battery Conditions and TA = 25°C) Vb = 4.6 V (Worst Case Battery Condition and TA = 25°C) Internal Overcurrent Limitation of HS Driver Outputs The Time from Short of HS Driver OUTx Pin to GND and the Driver Deactivation; Driver is Off; Detection Works from VB Minimum of 7 V; VDDN Minimum is 3 V High TSD Threshold for Junction Temperature (Temperature Rising) TSD Hysteresis for Junction Temperature 0.65 5.4 Min Max 3.5 25 Unit mA mA I_PDB_5 (Notes 8 and 9) 40 mA I_PDB_MAX_VB I_VDDN_norm (Note 8) 10 1.6 mA mA R_on_1 − 8 1 3 2 W I_OUT_lim_x (Note 8) T_shortGND_HSdoff A ms TSD_H (Note 8) TSD_HYST 130 9 170 18 °C °C 8. The power dissipation of the chip must be limited not to exceed maximum junction temperature TJ. 9. The cumulative operation time mentioned above may cause permanent device failure. http://onsemi.com 6 AMIS−39100 LOAD SPECIFIC PARAMETERS HS driver parameters for specific loads are specified in following categories: A. Parameters for inductive loads till 350 mH and TA till 105°C B. Parameters for inductive loads till 300 mH and TA till 105°C C. Parameters for resistive loads and TA till 85°C Table 8. LOAD SPECIFIC CHARACTERISTICS Symbol A. INDUCTIVE LOAD TILL 350 mH AND TA TILL 1055C I_OUT_ON_max Maximum output per HS driver, all eight drivers might be active simultaneously 240 mA Description Min Max Unit B. INDUCTIVE LOAD TILL 300 mH AND TA TILL 1055C I_OUT_ON_max Maximum output per HS driver, all eight drivers might be active simultaneously 275 mA C. RESISTIVE LOAD AND TA TILL 855C I_OUT_ON_max Maximum output per HS driver, all eight drivers might be active simultaneously Maximum output per one HS driver, only one can be active Maximum output per HS driver, only two HS drivers from a different pair can be active simultaneously Maximum output per one HS driver pair 350 650 500 830 mA mA mA mA The maximum current specified in cannot always be obtained. The practically obtainable maximum drive current heavily depends on the thermal design of the application PCB (see Section “Thermal Characteristics”). The available power in the package is: (TSD_H − TA) / Rthja With TSD_H = 130°C and Rthja according to Table 4. CHARGE PUMP 10. The parameters above are not tested in production but are guaranteed by design. The overall current capability limitations need to be respected at all times. result in the diagnostic register which is then latched in the output register at the rising edge of the WR−pin. Each driver has its corresponding diagnostic bit DIAG_x. By comparing the actual output status (DIAG_x) with the requested driver status (CMD_x) you can diagnose the correct operation of the application according to . Thermal Shutdown (TSD) Diagnostic The HS drivers use floating NDMOS transistors as power devices. To provide the gate voltages for the NDMOS of the HS drivers, a charge pump is integrated. The storage capacitor is an external one. The charge pump oscillator has typical frequency of 4 MHz. DIAGNOSTICS Short−Circuit Diagnostics In case of TSD activation, all bits DIAG 1 to DIAG 8 in the SPI output register are set into the fault state and all drivers will be switched off (see ). The TSD error condition is active until it is reset by the next correct communication on SPI interface (i.e. number of clock pulses during WR=0 is divisible by 8), provided that the device has cooled down under the TSD trip point. The diagnostic circuit in the AMIS−39100 monitors the actual output status at the pins of the device and stores the Table 9. OUT DIAGNOSTICS Requested driver status On On Off Off CMD_x 1 1 0 0 Actual output status High Low High Low DIAG_x 1 0 1 0 Normal State Short−to−Ground or TSD (Note 12) Short−to−VB or Missing Load (Note 11) or TSD (Note 12) Normal State (Note 11) Diagnosis 11. The correct diagnostic information is available after T_diagnostic_OFF time. 12. All 8 diagnostic bits DIAG_x must be in the fault condition to conclude a TSD diagnostic. http://onsemi.com 7 AMIS−39100 Ground Loss Due to its design, the AMIS−39100 is protected for withstanding module ground loss and driver output shorted to ground at the same time. Table 10. POWER LOSS VDDN 0 0 1 1 VB 0 1 0 1 System stopped Start case or sleeping mode with missing VDDN Missing VB supply VDDN normally present System functional Possible Case Nothing Eight switches in the off−state Power down consumption on VB Eight switches in the off−state Normal consumption on VDDN Nominal functionality Action SPI INTERFACE The serial peripheral interface (SPI) is used to allow an external microcontroller (MCU) to communicate with the device. The AMIS−39100 acts always as a slave and it can’t initiate any transmission. SPI Transfer Format and Pin Signals The SPI block diagram and timing characteristics are shown in and Figures 5 and 6. During an SPI transfer, data is simultaneously sent to and received from the device. A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DIN and DOUT). DOUT signal is the output from the AMIS−39100 to the external MCU and DIN signal is the input from the MCU to the AMIS−39100. The WR−pin selects the AMIS−39100 for communication and can also be used as a chip select (CS) in a multiple−slave system. The WR−pin is active low. If AMIS−39100 is not selected, DOUT is in high impedance state and it does not interfere with SPI bus activities. Since AMIS−39100 always shifts data out on the rising edge and samples the input data also on the rising edge of the CLK signal, the MCU SPI port must be configured to match this operation. SPI clock idles high between the transferred bytes. Table 11. DIGITAL CHARACTERISTICS Symbol T_CLK T_DATA_ready T_CLK_first T_setup (Note 13) T_hold (Note 13) T_DATA_next T_SPI_END T_risefall T_WR 13. Guaranteed by design. The diagram in Figure 6 represents the SPI timing diagram for 8−bit communication. Communication starts with a falling edge on the WR−pin which latches the status of the diagnostic register into the SPI output register. Subsequently, the CMD_x bits – representing the newly requested driver status – are shifted into the input register and simultaneously, the DIAG_x bits – representing the actual output status – are shifted out. The bits are shifted with x = 1 first and ending with x = 8. At the rising edge of the WR−pin, the data in the input register is latched into the command register and all drivers are simultaneously switching to the newly requested status. SPI communication is ended. In case the SPI master does only support 16−bit communication, then the master must first send 8 clock pulses with dummy DIN data and ignoring the DOUT data. For the next 8 clock pulses the above description can be applied. The required timing for serial to peripheral interface is shown in Table 11. Description Maximum applied clock frequency on CLK input Time between falling edge on WR and first bit of data ready on DOUT output (driver going from HZ state to output of first diagnostic bit) First clock edge from falling edge on WR Setup time on DIN Hold time on DIN Time between rising edge on CLK and next bit ready on DOUT (capa on DOUT is 30 pF max.) Time between last CLK edge and WR rising edge Rise and fall time of all applied signals (maximum loading capacitance is 30 pF) Time between two rising edge on WR (repetition of the same command) Min Max 500 2 Unit kHz ms ms ns ns 3 20 20 100 1 5 300 20 ns ms ns ms http://onsemi.com 8 AMIS−39100 Normal Mode Verification: • The command is the set of eight bits loaded via SPI, which drives the eight HS drivers on or off. • The command is activated with rising edge on WR pin. Table 12. DIGITAL CHARACTERISTICS Symbol T_command_L_max (Note 14) T_command_R (Note 14) T_PDB_recov Description Minimum time between two opposite commands for inductive loads and maximum HS driver current of 275 mA Minimum time between two opposite commands for resistive loads and maximum HS driver current of 350 mA The time between the rising edge on the PDB input and 90 percent of VB−1V on all HS driver outputs. (all drivers are activated, pure resistive load 35 mA on all outputs) Min 1 2 1 Max Unit s ms ms 14. Guaranteed by design. PD 50% t_PD_recov VOUTi 90% {VBi − 1V} t PC20070110.7 Figure 4. Timing for Powerdown Recovery DOUT INP UT REGISTER DIN CMD8 OUTPUT REGISTER CMD1 DIAG CMD DRIVER 8 STATE DIAG DIAG DIAG 1 COMMAND CMD8 REGISTER CMD1 MEMORY DIAG MEMO CMD 8 MEMO DIAG DIAG 1 CMDx High Side Driver DIAGx OUTx Figure 5. SPI Block Diagram http://onsemi.com 9 AMIS−39100 Transfer data from diagnostic registers to the output registers Falling edge on WR Transfer from input registers to the c ommand registers (Rising edge on WR) WR CLK DIN 1 2 3 4 5 6 7 8 CMD CMD CMD CMD CMD CMD CMD CMD 5 6 7 3 4 1 2 8 OUT DIN : DRIVER COMMAND DOUT High Z DIAG DIAG DIAG DIAG DIAG DIAG DIAG DIAG 5 6 7 2 3 4 1 8 High Z IN DOUT: OUTPUTs THE STATE OF DIAGNOSTICs OUT1 to 8 Figure 6. Timing Diagram DEVICE ORDERING INFORMATION Part Number AMIS39100PNPB3G AMIS39100PNPB3RG Temperature Range −40°C to 105°C −40°C to 105°C Package Type SOIC 28 W (Pb−Free) SOIC 28 W (Pb−Free) Shipping† 26 Units / Rail 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 AMIS−39100 PACKAGE DIMENSIONS SOIC 28 W CASE 751AR−01 ISSUE O http://onsemi.com 11 AMIS−39100 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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