AMIS-49587

AMIS-49587 Product Preview Power Line Carrier Modem ON Semiconductor’s AMIS−49587 is an IEC1334 compliant power line carrier modem using spread−FSK (S−FSK) modulation for robust low data rate communication over power lines. AMIS−49587 is built around an ARM 7TDMI processor core, and includes the MAC layer. With this robust modulation technique, signals on the power lines can pass long distances. The half−duplex operation is automatically synchronized to the mains, and can be up to 2400 bits/sec. The product configuration is done via its serial interface, which allows the user to concentrate on the development of the application. The AMIS−49587 is implemented in ON Semiconductor mixed signal technology, combining both analog circuitry and digital functionality on the same IC. Features http://onsemi.com 281 PLCC 28 Lead CASE 776AA • • • • • • • • • • • • • • • • • • Power Line Carrier Modem for 50 and 60 Hz Mains Fully Compliant to IEC1334−5−1 IEC 1334−4−32 / EN50065 Complete Handling of Protocol Layers Physical to MAC Programmable Carrier Frequencies from 9 to 95 kHz in 10 Hz Steps Half Duplex Data Rate Selectable: 300 – 600 – 1200 – 2400 baud (50 Hz) Synchronization on Mains Repetition Algorithm Boost the Robustness of Communication Other Features Under Development / Validation SCI Port to Application Microcontroller SCI Baudrate Selectable: 4.8 – 9.6 – 19.2 – 34.4 kb Power Supply 3.3 V Ambient Temperature Range: −40°C to +80°C These Devices are Pb−Free and are RoHS Compliant* AMR: Automated Remote Meter Reading (Télérelevé) Remote Security Control Streetlight Control Transmission of Alerts (Fire, Gas Leak, Water Leak) MARKING DIAGRAM ON XXXXYZZ AMIS49587 C587-NAF ARM e3 Typical Applications xx A WL, L YY, Y WW, W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. P0 1 Publication Order Number: AMIS−49587/D AMIS−49587 APPLICATION APPLICATION EXAMPLE Application Controller IO0 (TREQ) 3V3_D 17 18 21 6 20 23 RESB RXD TXD BR0 BR1 Interface  15 3V3_D  16 Meter AMIS−49587 1 27 4 5 M50HzIN * 3V3_A ½ NE5532 13 XTAL_IN REF_OUT ALC_IN 14 XTAL_OUT VSSA MAINS 3V3_A 3V3_D 12 28 26 25 TX_OUT 2 RX_OUT TX_ENB NCS5650 ½ NE5532 RX_IN 3 Figure 1. Typical Application for the AMIS−49587 S−FSK Modem A typical application example is given above. The example shows the AMIS−49587 with its companion devices. Namely the power line driver NCS5650, the application controller and a meter device interface. Between the modem chip and the line driver, an active band pass filter is used to reduce the noise outside the transmission band. The filter is realized with external passive components. From the line driver, the connection to the mains is done through a line transformer and a capacitive coupling. From the application side, the interface between the modem and the application is done through the SCI. The link to the meter device will be done easily by using the meter device interface chip. This device is used to realize the physical interface between the controller and the standard S0 pulse (DIN 19234) generator output of the meter device. http://onsemi.com 2 ( * ) Optional Auto Level Control 2x P6SM B6.8 1:2 VSS TX_DATA VDDA VDD AMIS−49587 Table 1. ORDERING INFORMATION Part No. AMIS49587C5871R AMIS49587C5871RG Package PLCC−28 (Pb−Free) PLCC−28 (Pb−Free) Shipping† Rail Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Table of Contents Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Detailed Hardware Description . . . . . . . . . . . . . . . . . . . . . . . 13 Detailed Software Description . . . . . . . . . . . . . . . . . . . . . . . . 20 AMIS−49587 Users Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OSI Architecture of AMIS−49587 . . . . . . . . . . . . . . . . . . . . . 25 Local Transfer and Configuration Commands (LTC) . . . . . . . Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medium Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repeater Call Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 31 39 40 42 44 57 58 http://onsemi.com 3 AMIS−49587 ABSOLUTE MAXIMUM RATINGS Stresses above those listed in this clause may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Power Supply Pins VDD, VDDA, VSS, VSSA Table 2. ABSOLUTE MAXIMUM RATINGS SUPPLY Rating Absolute maximum digital power supply Absolute maximum analog power supply Absolute maximum difference between digital and analog power supply Absolute maximum difference between digital and analog ground Symbol VDD_ABSM VDDA_ABSM VDD−VDDA_ABSM VSS−VSSA_ABSM Min VSS−0.3 VSSA−0.3 −0.3 −0.3 Max 3.9 3.9 0.3 0.3 Unit V V V V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Non 5V Safe Pins: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, M50HZ_IN, XIN, XOUT, TDO, TDI, TCK, TMS, TRSTB, TEST Table 3. ABSOLUTE MAXIMUM RATINGS NON 5V SAFE PINS Rating Absolute maximum input for normal digital inputs and analog inputs Absolute maximum voltage at any output pin Symbol VIN_ABSM VOUT_ABSM Min VSS*−0.3 VSS*−0.3 Max VDD*+0.3 VDD*+0.3 Unit V V 5V Safe Pins: TX_ENB, TXD, RXD, BR0, BR1, IO0, IO2, RESB Table 4. ABSOLUTE MAXIMUM RATINGS 5V SAFE PINS Rating Absolute maximum input for digital 5 V safe inputs Absolute maximum voltage at 5 V safe output pin Symbol V5VS_ABSM VOUT5V_ABSM Min VSS−0.3 VSS−0.3 Max 6.0 3.9 Unit V V Normal Operating Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the Receiver Block Diagram Section and for the reliability specifications as listed in the Local Transfer and Configuration Commands (LTC) Section. Functionality outside these limits is not implied. Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be less than 0.1% of the useful life as defined in the Local Transfer and Configuration Commands (LTC) Section. Table 5. OPERATING RANGES Rating Power Supply Voltage Range Ambient Temperature Symbol VDD TA Min 3.0 −25 Max 3.6 70 Unit V °C http://onsemi.com 4 AMIS−49587 PIN DESCRIPTION REF_OUT RX_OUT TX_OUT RX_IN ALC_IN VDDA VSSA 1 4 3 2 28 27 26 M50Hz_IN IO0 TDO TDI TCK 5 6 7 8 9 AMIS−49587 25 TX _ENB 24 TEST 23 RESB 22 IO1 21 BR0 20 BR1 19 IO2 TMS 10 TRSTB 11 12 13 14 15 16 17 18 TX_DATA/ PRE_SLOT XIN VSS XOUT VDD TXD RXD Figure 2. Pinout Table 6. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P: A: D: 5V Safe: Out: In: In/Out: Pin Name VSSA RX_OUT RX_IN REF_OUT M50HZ_IN IO0 TDO TDI TCK TMS TRSTB TX_DATA XIN XOUT VSS VDD TXD RXD IO2 BR1 BR0 IO1 RESB TEST TX_ENB TX_OUT ALC_IN VDDA Out In In/Out In In In/Out In In Out Out In Out In Out In In/Out Out In In In In Out In Out I/O Type P A A A A D,5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe A A P P D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D, 5V Safe D D, 5V Safe A A P Analog ground Output of input stage opamp Positive input of input stage opamp Reference output for stabilization 50.60 Hz input Programmable IO pin (open drain) Test data output Test data input (internal pulldown) Test clock (internal pull down) Test mode select (internal pulldown) Test reset bar (internal pull down, active low) Data output corresponding to transmitted frequency Xtal input (can be driven by an internal clock) Xtal output (output floating when XIN driven by external clock) Digital ground 3.3 V digital supply SCI transmit output (open drain) SCI receive input (Schmitt trigger output) Programmable IO pin + interrupt (open drain) SCI baud rate selection SCI baud rate selection Programmable IO pin (open drain) Master reset bar (Schmitt trigger input, active low) Test enable (internal pulldown) TX enable bar (open drain) Transmitter output Automatic level control input 3.3 V analog supply Description Power pin Analog pin Digital pin IO that support the presence of 5V on bus line Output signal Input signal Bi−directional pin http://onsemi.com 5 AMIS−49587 ELECTRICAL CHARACTERISTICS DC AND AC CHARACTERISTICS Oscillator: Pin XIN, XOUT In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator. Table 7. OSCILLATOR Parameter Crystal frequency Duty cycle with quartz connected Start−up time Maximum Capacitive load on XOUT Low input threshold voltage High input threshold voltage Low output voltage High input voltage Test Conditions (Note 1) (Note 1) (Note 1) XIN used as clock input XIN used as clock input XIN used as clock input XIN used as clock input, XOUT = 2 mA XIN used as clock input Tstartup CLXOUT VILXOUT VIHXOUT VOLXOUT VOHXOUT 0.3 VDD 0.7 VDD 0.3 VDD−0.3 Symbol fCLK Min −100 ppm 40 Typ 24 Max +100 ppm 60 50 50 Unit MHz % ms pF V V V V 1. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W. Zero Crossing Detector and 50/60Hz PLL: Pin M50HZ_IN Table 8. ZERO CROSSING DETECTOR AND 50/60HZ PLL Parameter Maximum peak input current Maximum average input current Mains voltage (ms) range Rising threshold level Falling threshold level Hysteresis Lock range for 50 Hz (Note 3) Lock range for 60 Hz (Note 3) Lock time (Note 3) Lock time (Note 3) Frequency variation without going out of lock (Note 3) Frequency variation without going out of lock (Note 3) Jitter of CHIP_CLK (Note 3) During 1 ms With protection resistor at M50HZIN (Note 2) (Note 2) (Note 2) MAINS_FREQ = 0 (50 Hz) MAINS_FREQ = 0 (60 Hz) MAINS_FREQ = 0 (50 Hz) MAINS_FREQ = 0 (60 Hz) MAINS_FREQ = 0 (50 Hz) MAINS_FREQ = 0 (60 Hz) Test Conditions Symbol ImpM50HZIN ImavgM50HZIN VMAINS VIRM50HZIN VIFM50HZIN VHY50HZIN Flock50Hz Flock60Hz Tlock50Hz Tlock60Hz DF60Hz DF50Hz JitterCHIP_CLK −25 0.9 0.4 45 54 55 66 15 20 0.1 0.1 25 Min −20 −2 90 Typ Max 20 2 550 1.9 Unit mA mA V V V V Hz Hz s s Hz/s Hz/s ms 2. Measured relative to VSS. 3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed by the digital test patterns. http://onsemi.com 6 AMIS−49587 Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz $ 100 ppm. Table 9. TRANSMITTER EXTERNAL PARAMETERS Parameter Maximum peak output level Test Conditions fTX_OUT = 23.75 kHz fTX_OUT = 95 kHz Level control at max. output fTX_OUT = 95 kHz Level control at max. output fTX_OUT = 95 kHz Level control at max. output (Notes 4 and 6) (Note 4) Symbol VTX_OUT Min 0.85 0.76 Typ Max 1.15 1.22 −56 −58 30 20 5 0.25 2.9 20.3 −0.46 −0.68 111 10 (Note 7) 0.5 3.1 21.7 −0.36 −0.54 189 35 (Note 8) Unit Vp Second order harmonic distortion Third order harmonic distortion Frequency accuracy of the generated sine wave Capacitive output load at pin TX_OUT Resistive output load at pin TX_OUT Turn off delay of TX_ENB output Automatic level control attenuation step Maximum attenuation Low threshold level on ALC_IN High threshold level on ALC_IN Input impedance of ALC_IN pin Power supply rejection ration of the transmitter section 4. 5. 6. 7. HD2 HD3 DfTX_OUT CLTX_OUT RLTX_OUT dB dB Hz pF kW ms dB dB V V kW dB (Note 5) TdTX_ENB ALCstep ALCrange VTLALC_IN VTHALC_IN RALC_IN PSRRTX_OUT This parameter will not be tested in production. This delay corresponds to the internal transmit path delay and will be defined during design. Taking into account the resolution of the DDS and an accuracy of 100 ppm of the crystal. A sinusoidal signal of 10 kHz and 100 mV ptp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The signal level at TX_OUT is measured to determine the parameter. 8. A sinusoidal signal of 50 Hz and 100 mV ptp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The signal level at TX_OUT is measured to determine the parameter. The LPF filter + amplifier must have a frequency characteristic between the limits listed below. The absolute output level depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB reference value is measured at 50 kHz with a signal amplitude of 100 mV. Table 10. TRANSMITTER FREQUENCY CHARACTERISTICS Attenuation Frequency (kHz) 10 95 130 165 330 660 1000 2000 Min −0.5 −1.3 −4.5 Max 0.5 0.5 −2.0 −3.0 −18.0 −36.0 −50 −50 Unit dB dB dB dB dB dB dB dB http://onsemi.com 7 AMIS−49587 Table 11. RECEIVER EXTERNAL PARAMETERS: Pin RX_IN, RX_OUT, REF_OUT Parameter Input offset voltage 42 dB Input offset voltage 0 dB Max. peak input voltage (corresponding to 62.5% of the SD full scale) Input referred noise of the analog receiver path Input leakage current of receiver input Max. current delivered by REF_OUT Power supply rejection ratio of the receiver input section AGC gain step AGC range Analog ground reference output voltage Signal to noise ratio at 62.5% of the SD full scale Clipping level at the output of the gain stage (Notes 9 and 13) AGC gain = 42 dB Test Conditions AGC gain = 42 dB AGC gain = 0 dB AGC gain = 0 dB (Note 9) Symbol VOFFS_RX_IN VOFFS_RX_IN VMAX_RX_IN 0.85 Min Typ Max 5 50 1.15 Unit mV mV Vp AGC gain = 42 dB (Notes 9 and 10) NFRX_IN ILE_RX_IN IMax_REF_OUT PSRRLPF_OUT AGCstep AGCrange VREF_OUT SNAD_OUT VCLIP_AGC_IN −1 −300 10 (Note 11) 35 (Note 12) 5.7 39.9 1.52 54 1.15 150 1 300 nV/√Hz mA mA dB 6.3 44.1 1.78 dB dB V dB 1.65 Vp 9. Input at RX_IN, no other external components. 10. This parameter will be characterized on a limited number of prototypes and will not be tested in production. 11. A sinusoidal signal of 10 kHz and 100 mV ptp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and REF_OUT output is measured to determine the parameter. 12. A sinusoidal signal of 50 Hz and 100mV ptp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is measured to determine the parameter. 13. These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB. The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below. The absolute output level depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB reference value is measured at 50 kHz with a signal amplitude of 100 mV. Table 12. RECEIVER FREQUENCY CHARACTERISTICS Attenuation Frequency (kHz) 10 95 130 165 330 660 1000 2000 Min −0.5 −1.3 −4.5 Max 0.5 0.5 −2.0 −3.0 −18.0 −36.0 −50 −50 Unit dB dB dB dB dB dB dB dB http://onsemi.com 8 AMIS−49587 Table 13. POWER−ON−RESET (POR) Parameter POR threshold Power supply rise time 0 V to 3 V Test Conditions Symbol VPOR TRPOR Min 1.7 1 Typ Max 2.7 Unit V ms Table 14. DIGITAL OUTPUTS: TDO, CLK_OUT Parameter Low output voltage High output voltage Test Conditions IXOUT = 4 mA IXOUT = −4 mA Symbol VOL VOH 0.85 VDD Min Typ Max 0.4 Unit V V Table 15. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_END, TXD Parameter Low output voltage Test Conditions IXOUT = 4 mA Symbol VOL Min Typ Max 0.4 Unit V Table 16. DIGITAL INPUTS: BR0, BR1 Parameter Low input level High input level Input leakage current 0 V to 3 V Test Conditions Symbol VIL VIH ILEAK 0.8 VDD −10 10 Min Typ Max 0.2 VDD Unit V V mA Table 17. DIGITAL INPUTS WITH PULL DOWN: TDI, TMS, TCK, TRSTB, TEST Parameter Low input level High input level Pull down resistor 14. Measured around a bias point of VDD/2. (Note 14) Test Conditions Symbol VIL VIH RPU 0.8 VDD 7 50 Min Typ Max 0.2 VDD Unit V V kW Table 18. DIGITAL SCHMITT TRIGGER INPUTS: RXC, RESB Parameter Rising threshold level Falling threshold level Input leakage current Test Conditions Symbol VT+ VT− ILEAK 0.9 −10 1− Min Typ Max 2.5 Unit V V mA Table 19. DIGITAL INPUT/OUTPUTS OPEN DRAIN: IO0, IO1, IO2 Parameter Low output voltage Low input level High input level Input leakage current Test Conditions ICOUT = 4 mA Symbol VOL VIL VIH ILEAK 0.8 VDD −10 10 Min Typ Max 0.4 0.2 VDD Unit V V V mA http://onsemi.com 9 AMIS−49587 Table 20. CURRENT CONSUMPTION Parameter Current consumption in receive mode Current consumption in transmit mode Current consumption when RESB = 0 15. CLKARM is < 12 MHz, fCLK = 24 MHz. Test Conditions Current through VDD and VDDA (Note 15) Current through VDD and VDDA (Note 15) Current through VDD and VDDA (Note 15) Symbol IRX ITX IRESET Min 60 60 Typ Max 80 80 4 Unit mA mA mA Main Modem Characteristics Table 21. OPERATING CHARACTERISTICS Parameter Positive supply voltage Negative supply voltage Max peak output level HD2 HD3 ALC Steps ALC Range Maximum input signal Input impedance Input sensitivity AGC steps AGC range Maximum 50 Hz variation Data rate Value 3.0 to 3.6 −0.7 to + 0.3 1, 2 −60 −60 3 (0 ... −21) 1, 15 100 0.4 6 (0 ... +42) 0, 1 300/360 (Note 23) 600/720 (Note 23) 1200/1440 (Note 23) 2400/2880(Note 23) Unit V V Vp dB dB dB dB Vp kW mV dB dB Hz/s baud baud baud baud Programmable carrier (Note 22) Frequency band Frequency minimum Frequency maximum Frequency deviation between pairs Dynamic range 9 95 >10 40 (Note 17) 60 (Note 18) 80 (Note 19) 10E−5 0, 1 Hz/s kHz kHz kHz dB dB dB Narrow band interfere BER (Note 20) Maximum 50 Hz variation 16. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W. 17. FER = 0%. 18. FER = 0.3%. 19. FER = 8.0%. 20. Signal between −60 dB and 0 dB interference signal level is 30 dB above signal level between 20 kHz and 95 kHz. 21. Input at −40 dB, duty cycle between 10 – 50% pulse noise frequency between 100 to 1000 Hz. BER: Bit error rate FER: Frame error rate (1frame is 288 bits). 22. Carriers frequency is programmable by steps of 10 Hz. 23. 60 Hz mains frequency. http://onsemi.com 10 AMIS−49587 INTRODUCTION GENERAL DESCRIPTION The AMIS−49587 is a single chip half duplex S−FSK modem dedicated to power line carrier (PLC) data transmission on low− or medium−voltage power lines. The device offers complete handling of the protocol layers from the physical up to the MAC. AMIS−49587 complies with the EN 50065 CENELEC and the IEC 1334−5−1 standards. It operates from a single 3.3 V power supply and is interfaced to the power line by an external power driver and transformer. An internal PLL is locked to the mains frequency (50 Hz or 60 Hz) and is used to synchronize the data transmission at data rates of 300, 600, 1200 and 2400 baud for a 50 Hz mains frequency, corresponding to 3, 6, 12 or 24 data bits per half cycle of the mains frequency (50 Hz or 60 Hz). S−FSK is a modulation and demodulation technique that combines some of the advantages of a classical spread spectrum system (e.g. immunity against narrow band interferers) with the advantages of the classical FSK system (low complexity). The transmitter assigns the space frequency fS to “data 0” and the mark frequency fM to “data 1”. The difference between S−FSK and the classical FSK lies in the fact that fS and fM are now placed far from each other, making their transmission quality independent from each other (the strengths of the small interferences and the signal attenuation are both independent at the two frequencies). The frequency pairs supported by the AMIS−49587 are in the range of 9−95 kHz with a typical separation of 10 kHz. The conditioning and conversion of the signal is performed at the analog front−end of the circuit. The further processing of the signal and the handling of the protocol is CLIENT Application AMIS− 49587 in MASTER mode digital. At the back−end side, the interface to the application is done through a serial interface. The digital processing of the signal is partitioned between hardwired blocks and a microprocessor block. The microprocessor is controlled by firmware. Where timing is most critical, the functions are implemented with dedicated hardware. For the functions where the timing is less critical, typically the higher level functions, the circuit makes use of the ARM 7TDMI microprocessor core. The processor runs DSP algorithms and, at the same time, handles the communication protocol. The communication protocol, in this application, contains the MAC = Medium Access Control Layer. The program running on the microprocessor is stored into an on−board ROM. The working data necessary for the processing is stored in an internal RAM. At the back−end side the link to the application hardware is provided by a SCI. The SCI is an easy to use serial interface, which allows communication between an external processor used for the application software and the AMIS−49587 modem. The SCI works on two wires: TXD and RXD. Baud rate is programmed by setting 2 bits (BR0, BR1). Because the low protocol layers are handled in the circuit, the AMIS−49587 provides an innovative architectural split. Thanks to this, the user has the benefit of a higher level interface of the link to the PLC medium. Compared to an interface at the physical level, the AMIS−49587 allows faster development of applications. The user just needs to send the raw data to the AMIS−49587 and no longer has to take care of the protocol detail of the transmission over the specific medium. This last part represents usually 50% of the software development costs. SPY Application AMIS− 49587 in MONITOR mode SERVER Application AMIS− 49587 in SLAVE mode SERVER Application AMIS− 49587 in SLAVE mode TEST Application AMIS− 49587 in TEST mode Major User Type Minor User Type Figure 3. Application Examples AMIS−49587 is an integrated circuit intended to connect equipment using Distribution Line Carrier (DLC) communication. It serves two major and two minor types of applications: • Major type: ♦ Server Applications which provide resources to a client. A typical application is an electricity meter device equipped for DLC • Client Applications which exploit remote servers. A typical application is a concentrator system is a Minor type: ♦ Spy Applications, used to monitor or test DLC communication on the channel. ♦ Test Mode, used to test the compliance of a PLC modem conforms to CENELEC. (Continuous broadcast of fS or fM). ♦ http://onsemi.com 11 AMIS−49587 FUNCTIONAL DESCRIPTION The block diagram below represents the main functional units of the AMIS−49587: TX_DATA Transmitter (S− FSK Modulator) Communication Controller TX_ENB TO Power Amplifier TxD Serial Comm. Interface TX_OUT ALC_IN LP Filter D/A Transmit Data & Sine Synthesizer RxD BR1 BR2 IO[0:2] JTAG I /F TEST RESB TO Application Micro Controller I/O ports RX_OUT FROM Line Coupler Receiver (S− FSK Demodulator) 16− bit ARM Risc Core Test Control RX_IN REF_OUT AAF AGC A/D S− FSK Demodulator POR REF Watchdog Clock and Control M50Hz_IN Zero crossing PLL Clock Generator & Timer OSC Timer 1 & 2 AMIS− 49587 VddA VssA VddD VssD XIN XOUT Data RAM Program ROM Interrupt Control Figure 4. S−FSK Modem AMIS−49587 Block Diagram Transmitter The AMIS−49587 Transmitting function block prepares the communication signal which will be sent on the transmitting channel during the transmitting phase. This block is connected to a power amplifier which injects the output signal on the mains through a coupler. Receiver circuits are also contained in this block. The support circuits include the necessary blocks to supply the references voltages for the AD and DA converters, the biasing currents and power supply sense cells to generate the right power off and startup conditions. The analog signal coming from the line−coupler is low pass filtered in order to avoid aliasing during the conversion. Then the level of the signal is automatically adapted by an automatic gain control (AGC) block. This operation maximizes the dynamic range of the incoming signal. The signal is then converted to its digital representation using sigma delta modulation. From then on, the processing of the data is done in a digital way. By using dedicated hardware, a direct quadrature demodulation is performed. The signal demodulated in the base band is then low pass filtered to reduce the noise and reject the image spectrum. Clock and Control 24 bit @ 1200 baud 20 ms Figure 5. Data Stream is in Sync with Zero Crossings of the Mains Communication Controller According to the IEC standard, the frame data is transmitted at the zero crossing of the mains voltage. In order to recover the information at the zero crossing, a zero crossing detection of the mains is performed. A phase−locked loop (PLL) structure is used in order to allow a more reliable reconstruction of the synchronization. This PLL permits as well a safer implementation of the ”repetition with credit” function (also known as chorus transmission). The clock generator makes use of a precise quartz oscillator master. The clock signals are then obtained by the use of a programmed division scheme. The support The Communication Controller block includes the micro−processor, its peripherals: RAM, ROM, UART, TIMER, and the Power on reset. The processor uses the ARM Reduced Instruction Set Computer (RISC) architecture optimized for IO handling. For most of the instructions, the machine is able to perform one instruction per clock cycle. The microcontroller contains the necessary hardware to implement interrupt mechanisms, timers and is able to perform byte multiplication over one instruction cycle. The microcontroller is programmed to handle the physical layer (chip synchronization), and the MAC layer conform to IEC 1334−5−1. The program is stored in a http://onsemi.com 12 AMIS−49587 masked ROM. The RAM contains the necessary space to store the working data. The back−end interface is done through the Serial Communication Interface block. This back−end is used for data transmission with the application micro controller (containing the application layer for concentrator, power meter, or other functions) and for the definition of the modem configuration. Local Port data (TX_DATA) or a synchronization signal with the time−slots (PRE_SLOT). Serial Communication Interface The controller uses 3 output ports to inform about the actual status of the PLC communication. IO[0] indicates if Receiving is in progress and is CRC is OK. TX_ENB is an output port for the information about the transmitter enabling. TX_DATA is the output for either the transmitting The local communication is a half duplex asynchronous serial link using a receiving input (RxD) and a transmitting output (TxD). The input port IO[2] is used to manage the local communication with the base micro (T_REQ) and the baud rate can be selected depending on the status of two local input ports (BR_0, BR_1). These two inputs are taken in account after a AMIS−49587 reset. Thus when the base micro wants to change the baud rate, it has to set the two inputs and then provoke a reset. DETAILED HARDWARE DESCRIPTION TRANSMITTER PATH DESCRIPTION (S−FSK MODULATOR) For the generation of the tones, the direct digital synthesis of the sine wave frequencies is performed under the control of the microprocessor. After a signal conditioning step, a digital to analog conversion is performed. As for the receive Transmitter (S− FSK Modulator) ALC_IN path, a sigma delta modulation technique is used. In the analog domain, the signal is low pass filtered, in order to remove the high frequency quantization noise, and passed to the automatic level controller (ACL) block, where the level of the transmitted signal can be adjusted. The determination of the signal level is done through the sense circuitry. ALC control ARM Interface & Control TX_OUT LP Filter D/A Transmit Data & Sine Synthesizer TX_DATA TX_ENB Figure 6. Transmitter Block Diagram ARM Interface and Control The interface with the ARM consists in a 8 bit data register, 2 control registers, a flag defining transmit and receive and 2 16 bit wide frequency step registers defining fM (mark frequency = data 1) and fS (space frequency = data 0) All these registers are memory mapped. The transmitter works synchronous with the BIT_CLK and BYTE_CLK signals when the register TX_RXB in R_CONF is logic 1. For good operation TX_RXB must change after an interrupt generated by PRE_BYTE_CLK. The interface between ARM and transmitter is interrupt based. At each BYTE_CLK the data from R_TX_DATA is copied into a buffer register (R_TX_DATA_BUFFER) The processing of the physical frame (preamble, MAC address, CRC) is done by the ARM Sine Wave Generator A sine wave is generated with a direct digital synthesizer DDS. The synthesizer generates in transmission mode a sine wave either for the space frequency (fS, data 0) or for the mark frequency (fM, data1). In reception the synthesizer generates the sine and cosine waves for the mixing process, fSI, fSQ, fMI, fMQ (space and mark signals in phase and quadrature). The space and mark frequencies are defined in an individual step 16 bit wide register. http://onsemi.com 13 AMIS−49587 Table 22. SPACE AND MARK FREQUENCY SELECTION (See Appendix C) ARM Register R_FS[15:0] R_FM[15:0] Reset 0000h 0000h Description Step register for the space frequency fS Step register for the mark frequency fM The space and mark frequency can be calculated as: • fS = R_FS[15:0]_dec x fDDS/218 • fM = R_FM[15:0]_dec x fDDS/218 Or the content of both R_FS[15:0] and R_FM[15:0] are defined as: • R_FS[15:0]_dec = Round(218 x fS/fDDS) • R_FM[15:0]_dec = Round(218 x fM/fDDS) ♦ Where fDDS = 3 MHz is the direct digital synthesizer clock frequency. After a hard or soft reset or at the start of the transmission (when TX_RXB goes from 0 to 1) the phase accumulator must start at it’s 0 phase position, corresponding with a 0 V output level. When switching between fM and fS the phase accumulator must give a continuous phase and not restart from phase 0. When AMIS−49587 goes into receive mode (when TX_RXB goes from 1 to 0) the sine wave generator must make sure to complete the active sine period. The control logic for the transmitter generates a signal TX_ENB to enable the external power amplifier. TX_ENB is 1 when the AMIS−49587 is in receive mode. TX_ENB is 0 when AMIS−49587 is in transmit mode. When going from transmit to receive mode (TX_RXB goes from 1 to 0) the TX_ENB signal is kept active for a short period of tdTX_ENB. The control logic for the transmitter generates a signal TX_DATA which corresponds to the transmitted SFSK signal. When transmitting fM TX_DATA is logic 1. When transmitting fS TX_DATA is logic 0. When the transmitter is not enabled (TX_RXB = 0) TX_DATA goes to logic 1 at the next BIT_CLK. BIT_CLK TX_DATA TX_RXB TX_ENB TX_OUT tdTX_ENB Figure 7. TX_ENB Timing DA Converter Amplifier with Automatic Level Control (ALC) A digital to analog SD converter converts the sine wave digital word to a pulse density modulated (PDM) signal. The PDM signal is converted to an analog signal with a first order switched capacitor filter. Low Pass Filter A 3rd order continuous time low pass filter in the transmit path filters the quantization noise and noise generated by the SD DA converter. The low pass filter has a circuit which tunes the RC time constants of the filter towards the process characteristics. The C values for the LPF filter are controlled by the ARM micro controller. The pin ALC_IN is used for level control of the transmitter output level. First a peak detection is done. The peak value is compared to 2 thresholds levels: VTLALC_IN and VTHALC_IN. The result of the peak detection is used to control the setting of the level of TX_OUT. The level of TX_OUT can be attenuated in 8 steps of 3 dB typical. After hard or soft reset the level is set at minimum level (maximum attenuation) When going to reception mode (when TX_RXB goes from 1 to 0) the level is kept in memory so that the next transmit frame starts with the old http://onsemi.com 14 AMIS−49587 level. The evaluation of the level is done during 1 CHIP_CLK period. Depending on the value of peak level on ALC_IN the attenuation is updated: − VpALC_IN < VTLALC: Increase the level with 1 step − VTLALC ≤ VpALC_IN ≤ VTHALC: Don’t change the level − VpALC_IN > VTHALC: Decrease the level with 1 step The gain changes in the next CHIP_CLK period. An evaluation phase and a level adjustment takes 2 CHIP_CLK periods. ALC operation is enabled only during the first 16 CHIP_CLK cycles after a hard or soft reset or after going into transmit mode. The automatic level control can be disabled by the ARM by setting R_ALC_CTRL[3] to 1. In case the transmitter outputs the programmed level in the register R_ALC_CTRL[2:0]. See Appendix C. The analog part of AMIS−49587 works with an analogue ground REF_OUT. When connecting AMIS−49587 to external circuitry working with another ground one must make sure to place a decoupling capacitor. RECEIVER PATH DESCRIPTION Receiver Block Diagram The receiver section is active when TX_RXB = 0. The operation mode and the baud rate are made according to the setting in R_CONF[9:0], R_FS[15:0] and R_FM[15:0]. See Appendix C. The receive signal is applied first to a high pass filter. Therefore AMIS−49587 has a low noise operational amplifier at the input stage which can be used to make a high pass active filter to attenuate the mains frequency. This high pass filter output is followed by a gain stage which is used in an automatic gain control loop. This block also performs a single ended input to differential output conversion. This gain stage is followed by a continuous time low pass filter to limit the bandwidth. A 4th order sigma delta converter converts the analog signal to digital samples. A quadrature demodulation for fS and fM is than performed by the ARM micro, as well the handling of the bits and the frames. RX_OUT LOW NOISE OPAMP Gain LPF Receiver (Analog Path ) FROM DIGITAL TO DIGITAL 4th Order SD AD RX_IN REF_OUT 1.65 V REF Figure 8. Analog Path of the Receiver Receiver (Digital Path) FROM ANALOG sin(fM ) st Quadrature Demodulator 2 nd Decimator Sliding Filter Sliding Filter Sliding Filter Sliding Filter Noise Shaper fM Decimator 1 Compen− sator cos(fM ) 2 nd Decimator sin(fS) TO GAIN AGC Control Abs value accu 2 nd Decimator cos(f S) fS Decimator 2 nd SOFTWARE Figure 9. Digital Path of the Receiver ADC and Quadrature Demodulation 50/60 Hz Suppression Filter AMIS−49587 receiver input provides a low noise input operational amplifier in a follower configuration which can be used to make a 50/60 Hz suppression filter with a minimum number of external components. This low noise operational amplifier is enabled when R_RX_MOD[7] = 0. See Appendix C. The pin RX_IN is the positive input and RX_OUT is the output of the input low noise operational amplifier. The pin REF_OUT can be use as an analog ground (1.65 V) for the external circuitry. http://onsemi.com 15 AMIS−49587 R2 Received Signal C2 C1 RX_OUT 2 LOW NOISE OPAMP TO AGC Receiver (S− FSK Demodulator) RX_IN 3 R1 REF_OUT 4 1, 65 V REF CDREF V SSA Figure 10. External Component Connection for 50/60 Hz Suppression Filter RX_IN is the positive analog input pin of the receiver low noise input op−amp. Together with the output RX_OUT an active high pass filter is realized. This filter removes the main frequency (50 Hz or 60 Hz) from the received signal. The filter characteristics are determined by external capacitors and resistors. Typical values are given in Table 23. For these values and after this filter, a typical attenuation of 80 dB at 50 Hz is obtained. Figure 9 represents external components connection. In a typical application the coupling transformer in combination with a parallel capacitance forms a high pass filter with a typical attenuation of 60 dB. The combined effect of the two filters decreases the voltage level of 230 Vrms at the mains frequency well below the sensitivity of the AMIS−49587. Figure 11. Transfer Function of 50 Hz Suppression Circuit REF_OUT is the analog output pin which provides the voltage reference used by the A/D converter. This pin must be decoupled from the analog ground by a 1 mF ceramic capacitance (CDREF). It is not allowed to load this pin. The low noise operational amplifier can be bypassed and powered down by setting the bit R_RX_MOD[7] to 1. In this mode the pin RX_OUT must be used as input of the AGC. Table 23. VALUE OF THE RESISTORS AND CAPACITORS Component C1 C2 CDREF R1 R2 Value 1.5 1.5 1 22 11 Unit nF nF mF kW kW The analog part of AMIS−49587 works with an analog ground of REF_OUT http://onsemi.com 16 AMIS−49587 CLOCK AND CONTROL Oscillator The oscillator works with a standard parallel resonance crystal of 24 MHz. XIN is the input to the oscillator inverter gain stage and XOUT is the output. XTAL _IN 24 MHz XTAL _ OUT CX V SSA RX CX V SSA Figure 12. Placement of the Capacitors and Crystal with Clock Signal Generated Internally For correct functioning the external circuit illustrated in Figure 12 must be connected to the oscillator pins. For a crystal requiring a parallel capacitance of 20 pF CX must be around 30 pF. (Values of capacitors are indicative only and are given by the crystal manufacturer). To guarantee startup the series loss resistance of the crystal must be smaller than 80 W. A parallel resistor RX = 1 MW is recommended to improve the clock symmetry. Zero Crossing Detector diodes. The zero crossing detector output is logic zero when the input is lower than the falling threshold level and a logic one when the input is higher than the rising threshold level. The falling edges of the output of the zero crossing detector are filtered by a period between 0.5 ms and 1 ms. Rising edges are not filtered. COMMUNICATION CONTROLLER Serial Communication Interface (SCI) M50HZ_IN is the mains frequency analog input pin − 50 or 60 Hz. This pin is used to detect the crossing of the zero voltage on one selected phase. This information is used, after filtering with the internal PLL, to synchronize frames with the mains frequency. In case of direct connection to the mains, the use of a series resistor of 1 MW is advised in order to limit the current flowing through the external protection IDLE (mark) Start LSB D0 D1 D2 D3 The SCI allows asynchronous communication. It can communicate with a UART = Universal Asynchronous Receiver Transmitter, ACIA = Asynchronous Communication Interface Adapter and all other chips that employ standard asynchronous serial communication. The serial communication interface allows only half duplex communication. MSB D4 D5 D6 D7 Stop IDLE (mark) t BIT 8 data bits 1 character Figure 13. Data Format tBIT The transmitting has the following characteristics: ♦ Half duplex. ♦ Standard NRZ format. ♦ Start bit, 8 data bits and 1 stop bit. ♦ ♦ ♦ Hardware programmable baud−rate (4800, 9600, 19200 and 38400 baud). 0−5 V levels with open drain for TxD. 0−5 V levels for RxD and T_REQ. http://onsemi.com 17 AMIS−49587 (PRE_SLOT ) IO2 T_REQ AMIS − 49587 TxD RxD TxD RxD Base Micro Figure 14. Connection to the Application Microcontroller SCI Physical Layer Description The following pins control the serial communication interface. TXD: Transmit data output. It is the data output of the AMIS−49587 and the input of the base micro. RXD: Receive data input. It is the data input of the AMIS−49587 and the output of the base micro. BR0, BR1: Baud rate selection inputs. These pins are externally strapped to a value or controlled by the external base microcontroller. Table 24. BR1, BR0 BAUD RATES BR_1 0 0 1 1 BR_0 0 1 0 1 Baud rate 4800 baud 9600 baud 19200 baud 38400 baud encapsulated in a local frame. The AMIS−49587 is the communication controller and has priority in a communication. This means that as soon as the AMIS−49587 wants to send a local frame (e.g. a local frame including a MA_Data_Indication), if the local communication channel is available (no local transfer has already begun), it can send this local frame. If the status message indicates a PLC buffer unavailable when the base micro wants to send a MA_Data_Request encapsulated in a local frame, this local frame will be answered by a Confirm « Resource Unavailable » if the base micro insists to send it. Transfer from Base Micro to AMIS−49587 Arbitration and Transfer In order to avoid collisions between the data sent by the AMIS−49587 and the base micro, the AMIS−49587 is chosen as the transmitting controller. This means that when there is no local transfer, the AMIS−49587 can initiate a local communication without taking account of the base micro state. In the other hand, when the base micro wants to send data (using a local frame), it must first send a request for communication through the local input port named T_REQ (Transmitting Request). Then the AMIS−49587 answers with a status message that contains information about the possibility of receiving a MA_Data_Request When the base micro wants to initiate a local transfer, it must pull down the T_REQ signal. The AMIS−49587 answers within the Tpoll delay with the status message in which the base micro can read if the communication channel is available. If the communication is possible, the base micro can start to send its local frame within the Tsr delay. It should pull up the T_REQ signal as soon as the first character (STX) has been sent. If the beginning of the local frame is not received before the Tsr delay was issued, the AMIS−49587 ignores the local frame. Remark: If the base micro only wants to know the state of the AMIS−49587, it has just to pull up the T_REQ signal after the reception of the status message. At the end of the data reception sent by the base micro on the RxD line, the AMIS−49587 sends a byte on the TxD line in order to inform about the status of the transmitting (ACK or NAK). http://onsemi.com 18 AMIS−49587 T_REQ tPOLL TxD Status ? tSR t ACK ACK RxD Local Frame from Base Micro Figure 15. Transfer from Base Micro to AMIS−49587 If the length and the checksum of the local frame are both correct, the AMIS−49587 acknowledges with an character. In other cases, it answers with a character. In case of response, or no acknowledgement from AMIS−49587 in the Tack time−out, a complete sequence must be restarted to repeat the frame. T_REQ Transfer from AMIS−49587 to Base Micro When the AMIS−49587 wants to send a frame, it can directly send it without any previous request. TxD Local Frame from AMIS − 49587 tACK t WBC Local Frame from AMIS− 49587 tACK t WBC Local Frame from AMIS− 49587 RxD NAK ACK Figure 16. Transfer from AMIS−49587 to Base Micro If the length and the checksum of the local frame are both correct, the base micro acknowledges with an character. In other cases, it answers with a character. In case of response from the Base Micro, the AMIS−49587 will repeat the frame only once after a delay corresponding to Twbc (Wait Before Continue). A non response from the base micro or a framing error when an character is awaited is considered as an acknowledgment. Character Time−out in Reception The time between two consecutive characters in a local frame should not exceed Time−out Inter Character (TIC): tIC Character Character Figure 17. Character Time−Out t After this delay, the frame reception is finished. If the length and the checksum are both correct, the local frame is taken in account otherwise all previous characters are discarded. The Time−Out Inter Character (TIC) is set by default at 10 ms after a reset. The time out Inter character http://onsemi.com 19 AMIS−49587 (TIC) is modified by the bit 7 of repeater parameter in the configuration frame : • bit 7 = 1 −> the TIC value is constant at 10 ms, • bit 7 = 0 −> the TIC value represents 5 characters depending on the communication speed (defined by two local input ports BR0 and BR1). See Appendix E: timings for Time−out values. RESET AND LOW POWER DETAILED SOFTWARE DESCRIPTION DESCRIPTION The AMIS−49587 software interface performs the time−out handling, the error checking, the acknowledgment and the reception mechanism. The reception mechanism insures that no collision will occur on the half duplex data channel. The error checking handles several controls (checksum frame, length of the frame and command syntax); an error can provoke repetitions (the base micro has to choose how many repetitions should be done). The AMIS−49587 resources are available via local commands, using the local communication serial interface. All data exchanged between the AMIS−49587 and the users should comply with the local communication protocol. PROTOCOL The AMIS−49587 and its base micro share a serial bus to communicate locally. The arbitration of this bus is performed by the AMIS−49587. The AMIS−49587 can directly transmit local frame to the base micro, but the base micro should never transmit local frame without authorization given by the AMIS−49587 (transmitted in the status message). • A Not Set AMIS−49587 only accepts the LTC requests (Reset_Request, TestMode_Request, WriteConfig_Request and WriteConfigNew_Request). • A Master AMIS−49587 accepts the LTC Reset_Request, WriteConfig_Request and WriteConfigNew_Request, the DB requests, the MAC requests and the ISA requests. • A Slave AMIS−49587 has got two different internal states. It could react differently with the base micro requests in function of these states: ♦ Not Synchronized with the mains: it only accepts the LTC Reset_Request, WriteConfig_Request and WriteConfigNew_Request, and the DB requests. ♦ Synchronized: it accepts the LTC Reset_Request, WriteConfig_Request and WriteConfigNew_Request, the DB requests, the MAC requests and the ISA requests. • A Monitor AMIS−49587 accepts the LTC Reset_Request, WriteConfig_Request and WriteConfigNew_Request, and the DB requests. When it is synchronized it supplies the SPY local frames. Remark: On the AMIS−49587 version 4, the WriteConfig_Request or WriteConfigNew_Request can be sent even if the AMIS−49587 is not in the « Not Set » state. It is not necessary to reset the AMIS−49587 before sending a WriteConfig_Request any more (NB: this is only available on AMIS−49587 version 4 and certain conditions must be respected, see Sections WriteConfig_Request (Tag 31h) and WriteConfigNew_Request (Tag 71h)). STATUS MESSAGE Time Slot Counter in Status Message The base micro has no information about the availability of the mains. To solve this problem, the AMIS−49587 supplies a hardware time−slot signal (PRE_SLOT) and a time−slot counter information included in the status message. This time−slot counter allows to the base micro to set its own counter (increased using the hardware time−slot signal). This time−slot counter is reset at the end of a communication (end of receiving, end of transmitting or end of repetition), one time−slot before the first one available for another communication (see figures below). Following time−slots are numbered from 1 to 7. The initial value of the time−slot counter is 7 (”unusable” value). The time−slot counter takes this initial value at the repetition beginning. To obtain a coherent value for the time−slot counter, the reading of the status message must be synchronized with the hardware pre−slot signal. A time−slot counter value equal to zero corresponds to the time−slot just before the first one supposed available (TSC = 1). It informs the base micro that the AMIS−49587 is ready to accept any MA_Data_Request. The following draws show how the time slot counter works: TS i Sub Frame n With1 vnv7 SubFrame n CC = 1 PAUSE TS i +1 Time Slot + 1 i TSC= 7 Pause Current Credit Time Slot counter Figure 18. Time Slot Legends http://onsemi.com 20 AMIS−49587 Status Message in NOT SET MODE: Table 25. STATUS MESSAGE IN NOT SET MODE Structure Byte 1 2 3 4 Content Start Data 1 Data 2 Data 3 SVN[7:4] Bit 7 0 x Bit 6 0 x Bit 5 1 x Bit 4 1 x RSV[7:0] SVN[3:0] Bit 3 1 x Bit 2 1 x Bit 1 1 Not SET Bit 0 1 X Where: Not SET RSV[7:0] SVN[7:4] SVN[3:0] x Indication is AMIS 49587 is set Reserved Software Version Number: major release Software Version Number: minor release Not Used Status Message in SLAVE MODE: Table 26. STATUS MESSAGE IN SLAVE MODE Structure Byte 1 2 3 4 Content Start Data 1 Data 2 Data 3 Bit 7 0 x Bit 6 0 x TS_Nb[2:0] DEP[2:0] Bit 5 1 x Bit 4 1 Not LOCKED x Bit 3 1 NEW x MDC[2:0] Bit 2 1 Not SYNC x Bit 1 1 Not SET ALARM _EN Bit 0 1 Buffer BUSY PLL _LOCK REP[1:0] Where: Not LOCKED NEW Not SYNC Not SET Buffer BUSY TS_Nb[2:0] Alarm_EN PLL_LOCK DEP[2:0] MDC[2:0] REP[1:0] x Indication if AMIS 49587 is Unlocked Indication if AMIS 49587 is New (see definition Section OSI Architecture of AMIS−49587) Indication of synchronization with mains Indication if AMIS 49587 is set Indication if PLC buffer is busy Time slot counter Alarm detection status PLL lock status Delta Electrical Phase Minimum Delta Credit Value Repeater Mode Not Used http://onsemi.com 21 AMIS−49587 Status Message in MASTER MODE: Table 27. STATUS MESSAGE IN SLAVE MODE Structure Byte 1 2 3 4 Content Start Data 1 Data 2 Data 3 Bit 7 0 x Bit 6 0 x TS_Nb[2:0] Bit 5 1 x Bit 4 1 x x Bit 3 1 x x Bit 2 1 Not SYNC x Bit 1 1 Not SET ALARM _EN Bit 0 1 Buffer BUSY PLL _LOCK InvalFrCnt[7:0] Where: Not SYNC Not SET Buffer BUSY TS_Nb[2:0] Alarm_EN PLL_LOCK InvalFrCnt[7:0] x Indication of synchronization with mains Indication is AMIS 49587 is set Indication if PLC buffer is busy Time slot counter Alarm detection status PLL lock status Invalid Frame counter Not Used Status Message in MONITOR MODE: Table 28. STATUS MESSAGE IN SLAVE MODE Structure Byte 1 2 3 4 Content Start Data 1 Data 2 Data 3 Bit 7 0 x Bit 6 0 x TS_Nb[2:0] DEP[2:0] Bit 5 1 x Bit 4 1 x x x Bit 3 1 x x x Bit 2 1 Not SYNC x x Bit 1 1 Not SET ALARM _EN x Bit 0 1 Buffer BUSY PLL _LOCK x Where: Not SYNC Not SET Buffer BUSY TS_Nb[2:0] Alarm_EN PLL_LOCK DEP[2:0] x Indication of synchronization with mains Indication is AMIS 49587 is set Indication if PLC buffer is busy Time slot counter Alarm detection status PLL lock status Delta Electrical Phase Not Used http://onsemi.com 22 AMIS−49587 GENERAL DESCRIPTION OF THE FRAME FORMAT The frame format is the same in both directions: Length Command User_Data CHK The fields are: Table 29. LOCAL FRAME DESCRIPTION Field Length Command User_Data CHK Byte Length 1 1 1 0..247 2 Value 02h 03h .. 250 00h .. FEh Byte String 0000h .. 65535 Start of text delimiter Length of the Command, UserData fields and CHK. Command code (Command Codes) Zero to 247 data bytes. The checksum of the local frame is the result of the addition of the elements of the frame, from length up to the last UserData byte, or up to the Command byte if there is no UserData byte. The CHK is sent with LSB first. Description Remark: As soon as a numeric value is greater than one byte (word, long...) it has to be sent in little endian format, that means LSByte first. AMIS−49587 USERS MODES NOT SET MODE In Not Set mode operation the AMIS−49587 software has no configuration and waits for it. The AMIS−49587 is in this mode after a power down or after a reset request. MASTER MODE (CLIENT) In MASTER mode operation the AMIS−49587 software should only know its own address (Local MAC address). The Initiator address (Initiator MAC address) is not used and initialized with the NOBODY address (000h). The Local MAC Address is in the range defined with the WriteConfig_Request command (FIMA/LIMA). SLAVE MODE (SERVER) In the Application layer there is a SMAE (system management application entity) which handles the server recording. A server is New when it starts for the first time or when the time−out not addressed has expired without a dedicated call for it. Thus its local MAC address is equal to NEW (FFE hex). After a power−up or a reset the AMIS−49587 does not know its previous setup. Then it informs the base micro it needs to be set by putting the bit « NotSet » in the status message. The base micro has to set the AMIS−49587 with the correct values using the WriteConfig_Request command. When a remote station is New (and then Unlocked), its Initiator MAC address is equal to 000h. After registration this address should be in the range FIMA/LIMA. MONITOR MODE (SPY) In MONITOR mode operation the AMIS−49587 software works only in receiving mode and supplies to the base micro all the physical sub−frames which have a good preamble and SSD. APPLICATION EXAMPLES FOR ADDRESS MAC RANGE Unlocked means that a Server has an Initiator MAC address equal to NOBODY. Locked means that a Server has a correct Initiator MAC address different from NOBODY. Therefore this slave will only answer to this initiator. http://onsemi.com 23 AMIS−49587 Table 30. MAC ADDRESS RANGE Application Mode Client AMDES Server New & Unlocked Not New & Locked Client BMS Server New & Unlocked New & Locked Not New & Locked Client ICC Server New & Unlocked New & Locked Not New & Locked Local MAC Address 400 to FEF FFE 1 to 3FF C00 to DFF FFE FFE 1 to BFF and E00 to FFB 400 to FEF FFE FFE 1 to 3FF Initiator MAC Address 000 000 400 to FEF 000 000 C00 to DFF C00 to DFF 000 000 000 400 to FEF 400 to FEF http://onsemi.com 24 AMIS−49587 OSI ARCHITECTURE OF AMIS−49587 The following figure represents the OSI architecture of the AMIS−49587. USER DataBase Services LTC Services MAC Services MAC LTC DB LOCAL MIB ISA PHY AMIS − 49587 COUPLER Power Line Figure 19. OSI Architecture of AMIS−49587 http://onsemi.com 25 ISA Services AMIS−49587 LOCAL TRANSFER AND CONFIGURATION COMMANDS (LTC) DESCRIPTION The Local Transfer and Configuration Commands (LTC) supplies the following services: • WriteConfigNew_Request: This command is used by the Base Micro to set the configuration in the AMIS−49587. The AMIS−49587 does not need to be reset before but some parameters cannot be changed without a reset • WriteConfigNew_Confirm: This command is sent by the AMIS−49587 to answer to a correct WriteConfigNew_Request. Its data is the result of the memory and register reading. WriteConfigNew_Error: This commands is sent by the AMIS−49587 to answer to an incorrect WriteConfigNew_Request. It contains an Error_Code that indicates which error has been detected. • TestMode_Request: This command is used by the Base Micro to put the AMIS−49587 in a special mode. It is used to perform tests on emission level. • Reset_Request: The Reset_Request is used to reset the AMIS−49587 by software when the Base Micro wants to do it. • Synchro_Indication: This command is sent by the AMIS−49587 to inform about the new synchronization state. Three possibilities could be performed: synchronization found, synchronization confirmed, and synchronization lost. Specific data are associated with each command. • Desynchro_Request: This command is used by the Base Micro to set the AMIS−49587 in the not synchronized state and therefore it starts looking for the synchronization. WriteConfigNew_Request (Tag 71h) CONFIGURATION COMMANDS Description The configuration allows to send to AMIS−49587 all the parameters it needs to work correctly. Most of these parameters are also accessible by a WriteDB_request. The configuration version 3 is the same as the one used on the previous versions of AMIS−49587, but some additional functionalities are available. To ensure a perfect compatibility with the old versions, make sure that: • the bits corresponding to the number of alarm repetitions are set to 0 (to disable the alarm functionality) • the bit corresponding to Bad CRC Frame transmitting is set to 0 (to disable this functionality) • The bits corresponding to the baudrate are set to 10 for 1200 bauds (since 11 will put the AMIS−49587 at 2400 bauds) • The bits corresponding to the Search Method and SINC Filter are set to 0 • Intelligent synchronization The configuration version 4 enables is a bit different than the version 3, and it enables one more functionality : the intelligent synchronization. All the new functionalities are also available with this configuration as well as with configuration version 3. Description: The field Data_Config contains the future configuration of the AMIS−49587 (36 bytes). This field is structured as shown in 7.4.4. Syntax: Initiator Base Micro Not Set Command (arguments) WriteConfigNew_Request (Data_Config) Possible Response WriteConfigNew_confirm (Data_Config_Echo) WriteConfigNew_Error (Error_Code) Since the AMIS−49587 has no non−volatile RAM memory, the information about the chip configuration are lost after each hard or soft reset and also after a power up. Therefore the AMIS−49587 software waits for a WriteConfig_Request or WriteConfigNew_Request after each reset. The software remains in this state until the configuration is correctly received. Frame Format: Length Data_Config CHK Notice: New Functionality: This command can be used to modify several parameters of the AMIS−49587 at the same time, even if AMIS−49587 is configured yet. This avoids the use of several successive Write_Db.Request. If the AMIS−49587 is set yet, some parameters cannot be changed any more and won’t be taken into account. The AMIS−49587 will return a WriteConfig_Error if the Base Micro tries to modify one of these parameters: http://onsemi.com 26 AMIS−49587 Table 31. NON CHANGEABLE PARAMETERS AFTER AMIS 49587 IS SET Field R_CONF_TX_DATA_PRE_SLOT_SEL Pad R_CONF→MODE R_CONF→BAUDRATE R_CONF→MAINS_FREQ Length 1 bit (b7) 1 bit (b6) 3 bits (b5 to b3) 2 bits (b2,b1) 1 bit (b0) Value x x xxx xx x Description No action No action No action No action No action WriteConfigNew_Confirm (Tag 72h) Description: The WriteConfigNew_Confirm is sent by the AMIS−49587 in order to indicate that the AMIS−49587 configuration has been written in registers and Data Base locations. The field Data_Config_Echo is the configuration copy read in the AMIS−49587 registers. So the base micro can check if the configuration recorded in the AMIS−49587 is correct. Its structure is the same as Data_Config (see Section WriteConfigNew_Request (Tag 71h)). Syntax: Initiator AMIS−49587 Master/Slave/Monitor Command (arguments) WriteConfigNew_Confirm (Data_Config_Echo) Possible Response Frame Format: Length Data_Config_Echo CHK WriteConfigNew_Error (Tag 73h) Description: The WriteConfigNew_Error is sent by the AMIS−49587 in order to indicate that the previous configuration received by the AMIS−49587 has not been memorized due to an error in its data. This error is due either to a bad MAC address or a Mode test. Syntax: Initiator AMIS−49587 Master/Slave/Monitor Command (arguments) WriteConfigNew_Error (Error_Code) Possible Response Frame Format: Length < WriteConfigNew_Error> Error_Code CHK General description of WriteConfigNew_Request Table 32. GENERAL DESCRIPTION OF WRITECONFIGNEW_REQUEST Field First Initiator MAC Address (FIMA) Last Initiator MAC Address (LIMA) Local MAC Address Length 2 bytes 2 bytes 2 bytes Value 0001 to 0FFF XXXX 0001 to 0FFF XXXX 0FFE or 0001 to (FIMA−1) FIMA to LIMA XXXX 0000 FIMA to LIMA XXXX 0000 to FFFF 0000 to FFFF 0000 to FFFF Description Slave: First value for Initiator MAC address Master & Monitor: don’t care Slave: Last value for Initiator MAC address Master & Monitor: don’t care Slave Mode : New Slave (Registered) Master Monitor Master, Slave (unlocked) Slave (locked on an initiator) Monitor Slave: In seconds. (Not used in Master mode) Slave: In seconds (Not used in Master mode) Slave : In minutes (Not used in Master & Monitor mode) Active Initiator Address 2 bytes Time−out−synchro−confirm Time−out−frame−not−ok Time−out−not−addressed 2 bytes 2 bytes 2 bytes http://onsemi.com 27 AMIS−49587 Table 32. GENERAL DESCRIPTION OF WRITECONFIGNEW_REQUEST Field Mac−group−addresses Fs Fm R_ZC_ADJUST NbAlarm R_ALC_CTRL→Value Max_Transmistting_Gain→Value R_ALC_CTRL→Value Max_Transmistting_Gain→Mode R_CONF_TX_DATA_PRE_SLOT_SEL Length 10 bytes 2 bytes 2 bytes 1 byte 4 bits (b7 to b4) 3 bits (b3 to b1) 1 bit (b0) 1 bit (b7) Value 0000 to 0FFF 0000 to FFFF 0000 to FFFF 00 to FF XXXX 0000 XXX 0 1 0 1 Pad R_CONF→MODE 1 bit (b6) 3 bits (b5 to b3) 0 001 010 011 00 01 10 11 0 1 0 0 1 0 1 0 XXX 1 X XXX Description Slave: 5 MAC group addresses (Not used in Master mode) Step Register for the Space Frequency Fs Step Register for the Mark Frequency Fm Value according to the voltage level of the 50 Hz information for the input of the PLL. Number of repetitions of a Phy Alarm Disable Phy Alarm functionality Attenuation value in fixed mode Automatic level control Fixed mode The output pin is the PRE_SLOT signal or Mode = Master The output pin is the transmitted DATA (for.Radio) This bit is not used (adjust length at 1 byte) Master mode for client station Slave mode for server station Monitor mode to spy and test of the DLC communication 300 baud @ 50 Hz or 360 baud @ 60 Hz 600 baud @ 50 Hz or 720 baud @ 60 Hz 1200 baud @ 50 Hz or 1440 baud @ 60 Hz 2400 baud @ 50 Hz or 2880 baud @ 60 Hz mains frequency = 50 Hz mains frequency = 60 Hz This bit is not used (adjust length at 1 byte) Method V6 Method V3 Disabled (1111) Enabled (1331) Must be set to 0 (Synchronization on sub−frame preamble) Synchro−bit value (in chip clock) in fixed mode Must be set to 1 (Fixed synchro bit) 0 Search Initiator Gain selected 1 Min Receiving Gain selected Value of the gain for Intelligent Synchronization or Min Receiving Value Min Gain of reception = (value * 6 db) Max Receiving gain value in limited mode Range of reception = (value * 6 db) Non limited Max−Receiving−Gain Limited Max−Receiving−Gain Constant of 10 ms 5 characters depending on communication speed Disables the transmitting of bad CRC frames Enables the transmitting of bad CRC frames Enables the Pad correcting Disables the Pad correcting R_CONF→BAUDRATE 2 bits (b2,b1) R_CONF→MAINS_FREQ Pad Search method SINC Filter SYNCHRO−Type→Mode SYNCHRO−Bit→Value SYNCHRO−Bit→Mode SearchInitiatorGain or Min−ReceivingGain Mode Search Initiator Gain or Min−Receiving Gain Max−Receiving−Gain→Value Max−Receiving−Gain→Mode Time out Inter Character TIC Bad CRC transmitting Pad correcting 1 bit (b0) 1 bit (b7) 2 bits (b6, b5) 1 bit (b5) 1 bit (b4) 3 bits (b3 to b1) 1 bit (b0) 1 bit (b7) 3 bits (b6 to b4) 3 bits (b3to b1) 1 bit (b0) 1 bit (b7) 1 bit (b6) 1 bit (b5) XXX 0 1 0 1 0 1 0 1 http://onsemi.com 28 AMIS−49587 Table 32. GENERAL DESCRIPTION OF WRITECONFIGNEW_REQUEST Field FSK + Alarm Filter Synchro without Gain Min Repeater Length 1 bit (b4) 1 bit (b3) 1 bit (b2) 2 bits (b1,b0) Value 0 1 0 1 x 00 01 10 11 0 to FFFF Description Disables the improvement of FSK Enables the improvement of FSK Enables the alarm filter Disables the alarm filter 0 disabled 1 enabled Never Repeater or Mode = Master Always Repeater Not Repeater (accept frame ISACall) Repeater (accept frame ISACall) In seconds (Not used in Master and Monitor mode) Time−out−search−initiator 2 bytes See Appendix C: SUMMARY of writeconfigNew_request for more details on the data for each mode. TEST MODE Description TESTMODE_REQUEST (Tag 81h) The test mode is used to perform tests on the emission level of the AMIS−49587 (for CENELEC for example – never used on the field) and on the reception. Six different modes are available: 1. Transmitting 1: the AMIS−49587 transmits the frequency corresponding to the “1” bit value non stop. 2. Transmitting 0: the AMIS−49587 transmits the frequency corresponding to the “0” bit value non stop. 3. Alternative transmission: the AMIS−49587 transmits alternatively the frequencies corresponding to the “1” and “0” bit values. 4. Reception E0/E1 (= no transmission) : the AMIS−49587 is placed in reception mode (but it is not able to interpret what it receives) and it sends on UART the envelop values. 5. Reception I0/Q0 (= no transmission) : the AMIS−49587 is placed in reception mode (but it is not able to interpret what it receives) and it sends on UART the channel 0 values of I and Q. 6. Reception I1/Q1 (= no transmission) : the AMIS−49587 is placed in reception mode (but it is not able to interpret what it receives) and it sends on UART the channel 1 values of I and Q. Description: The TestMode_Request command is used by the base micro to ask a Transmitting Test to the AMIS−49587. Then the AMIS−49587 is in Not Set mode and its data are all initialized. Remark: This means that the status will indicate that the AMIS−49587 is not set, but it won’t accept WriteConfig_Request and WriteConfigNew_Request without a reset. Be careful with using this mode, since nothing will indicate that the AMIS−49587 is in this mode. The field DataTx contains the chosen mode (transmitting1, transmitting 0, alternative transmission, E0/E1 reception, I0/Q0 reception, or I1/Q1 reception) (1 byte), the frequencies (2 * 2 bytes) and the MaxTransmisttingGain(1byte) Table 33. TESTMODES Mode Transmitting Fs Transmitting Fm Alternative transmission of Fs and Fm Reception I0/Q0 Reception I1/Q1 Reception E0/E1 Code 00 01 02 03 04 05 Syntax: Initiator Base Micro Master/Slave/Monitor Command (arguments) TestMode_Request (DataTx) Possible Response Frame Format: Length DataTx CHK http://onsemi.com 29 AMIS−49587 RESET AND SYNCHRO COMMANDS Description The reset command is used to replace the AMIS−49587 in the Not Set mode. The synchro commands are sent by the AMIS−49587 to the Base Micro to indicate the changes in the synchronization state of the AMIS−49587. Synchro_Indication (Tag 10h) Description: The Synchro_Indication is sent by the AMIS−49587 in order to indicate that something has changed in the synchronization state. The field Synchro_Data contains the change reason (see Section Synchronization State Codes) and data corresponding with this change. Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) Synchro_Indication (Synchro_Data) Possible Response Frame Format: Length Synchro_Data CHK Table 34. GENERAL DESCRIPTION OF SYNCHRO_INDICATION Change Reason Field Synchronisation Found (01h) Length and Synchro_data description 1 byte: Pad 2 bytes: Signal S0 2 bytes: Noise N0 2 bytes: Signal S1 2 bytes: Noise N1 2 bytes: ASK Threshold or FSK factor 1 byte : Method 1 byte : Synchro−Bit and Gain values 1 byte: Pad 2 bytes: Source MAC Address 2 bytes: Destination MAC Address Remark See Table 8: Description of the SpyData field for more details Synchronisation Confirmed (02h) Synchronisation Lost (04h) Time−out not addressed has expired (01h) Time−out frame not OK has expired (02h) Time−out synchro confirm has expired (03h) Addressed by a wrong initiator (04h) External desynchro command (05h) Search Initiator active (06h) 2 bytes: Local MAC Add 2 bytes: Initiator MAC Add 2 bytes: Local MAC Add 2 bytes: Initiator MAC Add 2 bytes: Local MAC Add 2 bytes: Initiator MAC Add 2 bytes: Source MAC Add 2 bytes: Dest. MAC Add 2 bytes: Local MAC Add 2 bytes: Initiator MAC Add 2 bytes: Last initiator MAC Address received 2 bytes: Current initiator MAC Address choice Slave mode Master and Slave mode Master and Slave mode Slave mode Master and Slave mode Slave mode http://onsemi.com 30 AMIS−49587 Desynchro_Request (Tag 11h) Description: The Desynchro_Request command is used by the base micro to enforce the not synchronized state in the AMIS−49587 and therefore it starts looking for a new synchronization. Syntax: Initiator Base Micro Master/Slave/Monitor Command (arguments) Desynchro_Request () Possible Response Frame Format: Length CHK Reset_Request (Tag 21h) Description: The Reset_Request command is used by the base micro to ask a reset to the AMIS−49587. Then the AMIS−49587 is in Not Set mode and its data are all initialized. This command has no data. The base micro can send this command at anytime. Syntax: Initiator Base Micro Master/Slave/Monitor Command (arguments) Reset_Request () Possible Response Frame Format: Length CHK SCENARIO OF STARTING AFTER RESET This scenario is achieved at the starting time and after a Reset_Request command. T_REQ TxD Status Massage ACK WriteConfig _Conf RxD WriteConfig _Req ACK Figure 20. Scenario of starting DATABASE DESCRIPTION These commands allow the access to variables in the Data Base which is constituted by a MIB array and a local data array. The communication between the AMIS−49587 and the base micro is performed through the asynchronous serial interface (UART) by using the WriteDB_Request, the WriteDB_Confirm and the WriteDB_Error commands. THE COMMANDS AVAILABLE WriteDB_Request (Tag 41h) Description: The WriteDB_Request is sent by the base micro in order to write one data in the AMIS−49587 data base. The field DB_Data_Id is coded on several bytes in Hex and is structured as follow: − 2 bytes for the Identifier field (Ident) that indicates which data has to be modified (transmitted LSByte first). − 0 to 20 bytes for the data depending on the Identifier field. http://onsemi.com 31 AMIS−49587 See Section The Objects Available on and The Objects Available Only on AMIS−49587 versions for more details on each object. Syntax: Initiator Base Micro Master/Slave Command (arguments) WriteDB_Request (DB_Data_Id) Possible Response WriteDB_Confirm (DB_Data_Id_Echo) WriteDB_Error (Error_Code) Frame Format: Length < WriteDB_Request > DB_Data_Id CHK Table 35. LIST OF WRITEDB ITEMS Field Name FIMA/LIMA LocalMacAdd/InitMacAdd Time−out−synchro−confirm Time−out−frame−not−ok Time−out−not−addressed Mac−group−addresses Invalid−frame−counter Min−delta−credit Max_Transmitting_Gain : Mode and Value (R_ALC_CTRL ) SYNCHRO−Type:Mode SYNCHRO−Bit:Value Max−Receiving−Gain: Mode and Value Repeater Frequency Counters Ident 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D Description Changes the value of First Initiator MAC Address (FIMA) and Last Initiator MAC Address (LIMA) Changes the value of Local MAC Address and Active Initiator Address Changes the value of the TO synchro confirm (In seconds.) Changes the value of the TO frame not ok (In seconds) Changes the value of the TO not addressed (In minutes) Changes the value of the 5 MAC group addresses Read the value of the invalid−frame counter and then set to 0 Read the value of the Min delta credit and then set to 7 Changes the mode and the value of the max transmitting gain Changes sychro mode and the synchro bit value Changes the mode and the value of the Max Receiving gain Changes the repeater state Changes the value of the frequencies Fs and Fm Read the value of the data counters:Counter Crc Ok, Counter Crc Not Ok, Repeater counter, Transmit counter, corrected frames counter, and then set to 0 or not Request the transmission of a Phy Alarm Read the value of the Data statistics, and then set to 0 or not. Changes the value of the TO Search Initiator (In seconds) To get an echo of the current configuration of the FPMA Read the version of the FPMA Changes the value of the Min Receiving Gain Changes the value of the Gain−SearchInitiator PhyAlarmRequest DataStats Time−SearchInitiator ReadConfig Read SoftVersion Min−ReceivingGain Value Gain−SearchInitiator 000F 0010 0011 0012 0013 0014 0015 http://onsemi.com 32 AMIS−49587 WriteDB_Confirm (Tag 42h) Description: The WriteDB_Confirm has to be sent by the FPMA when new data have been correctly recorded. The DB_Data_Id_Echo contains the identifier of the data and the value read at its memory location. It may have the same structure as DB_Data_Id or be different (see Section “The Objects Available” for more details on each object). Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) WriteDB_Confirm (Data_Config_Echo) Possible Response Frame Format: Length < WriteDB_Confirm > DB_Data_Id_Echo CHK WriteDB_Error (Tag 43h) Description: The FPMA software checks the MAC addresses, the Synchro−bit and if the modification of that field is allowed. If it detects an error, it sends back a WriteDB_Error command with the corresponding Error_Code (see Section “The Objects Available”). Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) WriteDB_Error (Error_Code) Possible Response Frame Format: Length < WriteDB_Error > Error_Code CHK THE OBJECTS AVAILABLE FIMA/LIMA Description: This request is used to modify the value of the FIMA and LIMA addresses. The values of FIMA and LIMA must be in the field 0001 to 0FFF, and must be compatible with current value of LocalMacAdd and InitMacAdd. Request Format: Length 41h 0000h FIMA (2 bytes), LIMA (2 bytes) CHK Confirm Format: Length 42h 0000h FIMA (2 bytes), LIMA (2 bytes) CHK LocalMacAdd/InitMacAdd Description: This request is used to modify the value of the Local Mac Address and the Initiator Mac Address. The values of LocalMacAdd and InitMacAdd must be in the field 0001 to 0FFF, and must be compatible with current value of FIMA and LIMA. Request Format: Length 41h 0100h LocalMacAdd (2 bytes), InitMacAdd (2 bytes) CHK Confirm Format: Length 42h 0100h LocalMacAdd (2 bytes), InitMacAdd (2 bytes) CHK http://onsemi.com 33 AMIS−49587 TimeoutSynchro Description: This request is used to modify the value of the timeout synchro confirmation. The Timeout Synchro Confirm is set in seconds. Request Format: Length 41h 0200h TO Synchro Confirm (2 bytes) CHK Confirm Format: Length 42h 0200h TO Synchro Confirm (2 bytes) CHK Description: This request is used to modify the value of the timeout Frame Not OK. The Timeout Frame Not OK is set in seconds. Request Format: Length 41h 0300h TO Frame Not OK (2 bytes) CHK TimeoutNotOK Confirm Format: Length 42h 0300h TO Frame Not OK (2 bytes) CHK TimeoutNotAddressed Description: This request is used to modify the value of the timeout Not Addressed. The Timeout Not Addressed is set in minutes. Request Format: Length 41h 0400h TO Not Addressed (2 bytes) CHK Confirm Format: Length 42h 0400h TO Not Addressed (2 bytes) CHK MacGroupAddress Description: This request is used to modify the values of the 5 Mac Group Addresses. The Mac Group Addresses must be in the field LIMA(not included) to 0FFB. If the first address of the 5 MacGroup addresses is set to 0xFFF, every frame with destination MAC address in the field LIMA(not included) to 0FFB will be transmitted by the FPMA. This makes it possible to manage more than 5 MAC address of group by the external micro controller. Request Format: Length 41h 0500h Mac Group Addresses (5 *2 bytes) CHK Confirm Format: Length 42h 0500h Mac Group Addresses (5 *2 bytes) CHK Invalid Frame Counter Description: This request is used to read the Invalid Frame Counter of the AMIS−49587. Once the request sent to the AMIS−49587, the Invalid Frame counter is automatically set to 0. The AMIS−49587 answers with the value of the Invalid Frame Counter Request Format: Length 41h 0600h Pad (0 to 1 byte) CHK Confirm Format: Length 42h 0600h Invalid Frame Counter (0 to 1 byte) CHK http://onsemi.com 34 AMIS−49587 Min Delta Credit Description: This request is used to read the Min Delta Credit in the AMIS−49587. Once the request sent to the AMIS−49587, the Min Delta Credit is automatically set to 7. The AMIS−49587 answers with the value of the Min Delta Credit (before it was set to 7) Request Format: Length 41h 0700h Pad (0 to 1 byte) CHK Confirm Format: Length 42h 0700h Min Delta Credit (1 byte) CHK MaxTransmittingGain Description: This request is used to modify the Max Transmitting Gain of the AMIS−49587. The Max Transmitting Gain can be reduced from 0 to 21 dB by step of step 3 dB. The data value for the request is in the field 01 to 0F by step of 2, it indicates an attenuation of ((N − 1) / 2) dB. The data value for the Confirm is in the field 00 to 07, indicating an attenuation of N * 3 dB. Request Format: Length 41h 0800h Transmitting Attenuation (1 byte) CHK Confirm Format: Length 42h 0800h Transmitting Attenuation (1 byte) CHK Synchro Description: This request is used to modify the synchro parameters: the synchro type and the synchro bit. The value of the synchro bit field is 0 if the synchro bit is automatic, or (2 * N) + 1 if the synchro bit is fixed, where N is the synchro bit value (0 < N < 7). You can add 16 to this value to enable synchronization on special frame Request Format: Length 41h 0900h Synchro−Type−bit (1 byte) CHK Confirm Format: Length 42h 0900h Synchro−Type−bit (1 byte) CHK MaxReceivingGain Description: This request is used to modify the Max Receiving Gain of the AMIS−49587. The Max Receiving Gain can be set from 1 to 42 dB by step of step 6dB, or unlimited. The data value for the request is in the field 01 to 0F by step of 2, it indicates a Max Receiving Gain of ((N − 1) / 2) * 6 dB; or 00, which indicates an unlimited Max Receiving Gain. The data value for the Confirm is in the field 00 to 07, indicating a Max Receiving Gain of (N * 6) dB, or 08, which indicates an unlimited Max Receiving Gain. Request Format: Length 41h 0A00h Max Receiving Gain (1 byte) CHK Confirm Format: Length 42h 0A00h Max Receiving Gain (1 byte) CHK http://onsemi.com 35 AMIS−49587 Repeater Description: This request is used to modify the repeater state of the AMIS−49587. The repeater state can be Repeater, No Repeater, Repeater Isacall or No Repeater Isacall. Only the 2 last bits are used for this command, so the value is in the field 00 to 03. Request Format : Length 41h 0B00h Repeater State (1 byte) CHK Confirm Format: Length 42h 0B00h Repeater State (1 byte) CHK Frequency Description: This request is used to modify the values of the frequencies Fs and Fm used for the PLC communication. See calculation method Sine Wave Generator on Page 13. Request Format: Length 41h 0C00h Fs (2 bytes), Fm (2 bytes) CHK Confirm Format: Length 42h 0C00h Fs (2 bytes), Fm (2 bytes) CHK Description: This request is used to read the value of the data counters in the AMIS−49587. It contains one byte which is used to know whether the counters must be reset or not (00: no reset, 01: reset) There are 6 counters coded on 4 bytes each, which indicates: − Number of CRC OK frames received − Number of CRC not OK frames received − Number of repeated frames − Number of transmitted frames − Number of corrected frames (with option Pad Correcting) − Number of frames with bad Frame Indicator received Request Format : Length 41h 0D00h Request Counters (1 byte) + Pad (0 to 19 bytes) CHK Data Counters Confirm Format : Length 42h 0D00h CRC_OK (4 bytes), CRC_NOK (4 bytes), Rep_Frames (4 bytes), Tr_Frames (4 bytes), Corr_Frames (4 bytes), FI_NOK (4 bytes) CHK PhyAlarmRequest Description: This request is used to send a physical alarm pattern. No data is transmitted to indicate the number of repetitions, the FPMA already knows this number because it is in its config. Request Format: Length 41h 0F00h Pad (0 to 1 byte) CHK Confirm Format: Length 42h 0F00h Number of alarm Transmissions (1 byte) CHK http://onsemi.com 36 AMIS−49587 DataStats Description: This request is used to read the value of the current data statistics in the AMIS−49587. The request contains one byte which is used to know whether the counters must be reset or not (00: no reset, 01: reset). These statistics are coded this way: If the AMIS−49587 is synchronized (30 bytes): − The value of signal and noise (S0, N0, S1, N1) for the last subframe received (4 * 2 bytes) + the method and gain used to demodulate this subframe (2 * 1 byte) − The method, gain and SNR (S0/N0, S1/N1) on the 5 last time slots in reception mode (5 * 4 bytes) + 1 byte to know the actual position in the table If the AMIS−49587 is not synchronized (36 bytes): − The values of the real and imaginary parts of the signal for each frequency (I0, Q0, I1, Q1), for the 4 last calculated time−slots (4 * (4 * 2 bytes)) − The current position in the board (1 byte) − The software reception gain (1 byte) − The hardware reception gain (1 byte) − The R_ALC value (1 byte) Request Format: Length 41h 1000h Reset Counters (1 byte) + Pad (0 to 35 bytes) CHK Confirm Format: If the AMIS−49587 is synchronized: Length 42h 1000h Signal_noise_subframe (10 bytes), SNRreception (20 bytes) CHK If the AMIS−49587 is not synchronized: Length 42h 1000h I0,I1,Q1 (32 bytes), Pos (1 byte), GainSoft (1 byte), GainHard (1 byte), R_ALC (1 byte) CHK TimeoutSearchInitiator Description: This request is used to modify the value of the timeout Search Initiator. The timeout Search Initiator is set in seconds. Request Format: Length 41h 1100h TO Search Initiator (2 bytes) CHK Confirm Format: Length 42h 1100h TO Search Initiator (2 bytes) CHK ReadConfig Description: This request is used to get an echo of the configuration of the AMIS−49587. Request Format: Length 41h 1200h Pad (0 to 36 bytes ) CHK Confirm Format: Length 42h 1200h Pad (0 to 36 bytes ) CHK http://onsemi.com 37 AMIS−49587 Read Version Soft Description: This request is used to read the soft version of the AMIS−49587. Request Format: Length 41h 1300h Pad (0 to 1 byte ) CHK Confirm Format: Length 42h 1300h Soft Version (1 byte ) CHK Min−ReceivingGain Description: This request is used to modify the Min Receiving Gain of the AMIS−49587. The Min Receiving Gain can be set from 1 to 42 dB by step of step 6dB, or unlimited. The data value for the request is in the field 01 to 0F by step of 2, it indicates a Min Receiving Gain of ((N − 1) / 2) * 6 dB; or 00, which indicates that the Min Receiving Gain is not used. The data value for the Confirm is in the field 00 to 07, indicating a Min Receiving Gain of (N * 6) dB, or 08, which indicates an unlimited Max Receiving Gain. Request Format: Length 41h 1400h Min Receiving Gain (1 byte ) CHK Confirm Format: Length 42h 1400h Min Receiving Gain (1 byte ) CHK Gain Search Initiator Description: This request is used to modify the value of the Gain Search Initiator. Request Format: Length 41h 1500h Gain Search Initiator (1 byte ) CHK Confirm Format: Length 42h 1500h Gain Search Initiator (1 byte ) CHK http://onsemi.com 38 AMIS−49587 MEDIUM ACCESS CONTROL DESCRIPTION The local communication exchanges data with the MAC sub−layer. These data (included into local frames) contain information about the DLC frame transmission on the mains (Initial credit, current credit, delta credit, local and destination MAC addresses) and the data field. Other information for transmission such as the Preamble, the Start Sub−frame Delimiter, the Frame Indicator and the Frame Check Sequence are directly managed by the MAC THE COMMANDS AVAILABLE MA_DATA_Request (Tag 51h) sub−layer and the PHYsical layer. In case of transmission from AMIS−49587 to the mains, if necessary, the MAC sub−layer will separate the frame into one or several sub−frame(s) (maximum 7 sub−frames). In case of frame reception made up of several sub−frames, the AMIS−49587 will send back the complete frame (without Pre, SSD, FI, FCS) to the local communication after the last sub−frame reception and only if the frame is correct and dedicated for this application. Description: The MA_Data_Request is sent from the base micro local LLC sub−layer to the AMIS−49587 local MAC sub−layer to request a DLC frame transmission. This request must be received by the AMIS−49587 in the time−slot preceding the transmitting one. Syntax: Initiator Base Micro Master/Slave Command (arguments) MA_Data_Request (MAC_Frame) Possible Response MA_Data_Confirm (Transmission_Status) Frame Format : Length < MA_Data_Request > MAC_Frame CHK Table 36. DESCRIPTION OF THE MAC_FRAME FIELD Field name Initial Credit Current Credit Delta Credit Source Address Destination Address Pad length M_sdu Length 3 bits b7−b5 3 bits b4−b2 2 bits b1,b0 12 bits b23−b12 12 bits b11−b0 1 byte up to 242 bytes Value 0h to 7h 0h to 7h 0h to 3h Not used 000h to FFFh 000h to FFFh Not used Description Initial Credit Current Credit = Initial Credit Delta Credit = Received Delta Credit (Slave) = 0 (Master) Slave Mode (Filled by MAC layer) Master Mode Destination MAC address of the target station DLC Filled by MAC layer MAC service data unit MA_DATA_Confirm (Tag 52h) Description: The MA_DATA_Confirm is sent from AMIS−49587 to a base micro (SLAVE or MASTER) either as positive acknowledgment when a MA_DATA_Request has successfully been transmitted by the physical layer, or as negative acknowledgment when the transmission has been refused. The positive acknowledgment is sent after the frame transmission on the mains and before the beginning of the repetition (if the credit is higher than zero). The Transmission_Status byte contains a value corresponding at this positive or negative acknowledgment. The different values for the Transmission_Status field are described in the Table 45: Transmission Status. Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) MA_Data_Confirm (Transmission_Status) Possible Response Frame Format : Length < MA_Data_Confirm > Transmission_Status CHK http://onsemi.com 39 AMIS−49587 MA_DATA_Indication (Tag 50h) Description: The MA_Data_Indication is sent from the AMIS−49587 (Client or Server) to the base micro to deliver the received DLC frame to the base micro LLC sub−layer. Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) MA_Data_Indication (MAC_Frame) Possible Response Frame Format : Length < MA_Data_Indication > MAC_Frame CHK See Table 36 Description of the Mac Frame field. MA_DATA_Indication_Bad_CRC (Tag 53h) Description: The MA_Data_Indication_Bad_CRC is sent from the AMIS−49587 (Client or Server) to the base micro to deliver an erroneous received DLC frame to the base micro LLC sub−layer. This command is only used if the Bad CRC transmitting option is chosen during the configuration (see Sections WriteConfig_Request (Tag 31h) and WriteConfigNew_Request (Tag 71h)) Syntax: Initiator AMIS−49587 Master/Slave Command (arguments) MA_Data_Indication_Bad_CRC (MAC_Frame) Possible Response Frame Format : Length < MA_Data_Indication_Bad_CRC > MAC_Frame CHK Table 36 − Description of the Mac Frame field. Caution: The Mac Frame transmitted with this command is erroneous. It may be used by the base Micro to try and rebuild a correct frame (by using the repetitions for example), but is cannot be used just as it is. REPEATER CALL FUNCTION ISA_REQUEST (TAG 61H) Description: In client mode, the ISA_Request command is normally sent by the base micro, when it wants to start a special sequence named « ISACall ». In server mode, the ISA_Request command is normally sent by the base micro, when it has received a MA_Data_Indication corresponding with an ISACall indication. The ISA_Request command is sent from the base micro local LLC sub−layer to the AMIS−49587 local MAC sublayer to switch the AMIS−49587 in special mode called « ISACall ». This service is an internal service and should not be used. Without correct handling at the system level it can disable the communication. Internal Service Request. Syntax: Initiator Base Micro Slave Command (arguments) ISA_Request (DataRepeater) Possible Response ISA_Confirm (Transmission_Status) Frame Format : Length < ISA_Request > Data_ISA CHK http://onsemi.com 40 AMIS−49587 Table 37. FORMAT OF THE DATA_ISA FIELD Field Name Level Transmission_Position Length 2 bytes 2 bytes Value 0 to FFFF 0 to FFFF When ISA_Request command is received, AMIS−49587 enters in RepeaterCall function and is listening for the repeater call pattern, which is 2 bytes long (2E5C), and waiting to transmit this pattern if no other module has transmitted before. So next frames are divided in 21 SubTslots of 2 bytes. After ISA_Request, if AMIS−49587 is set as Repeater or NoRepeater, it is listening until a pattern is detected, or until the SubTslot counter is equal to the parameter Transmission_Position. If a pattern is detected, AMIS−49587 is set to NoRepeater and exits RepeaterCall function. If no pattern detected and SubTslot counter is equal to Transmission_Position, the AMIS−49587 transmits the pattern, is set as Repeater, and exits the function. If AMIS−49587 is set as AlwaysRepeater, it will always transmit pattern when SubTslot counter is equal to Transmission_Position, even if a pattern has already been transmitted before. If it is set as NeverRepeater or is in Slave mode, ISA_Request command will not be accepted, and AMIS−49587 will not take part in RepeaterCall function. Transmission_Position value depends on the mode: − In Client mode, it is 0: pattern is transmitted at the first SubTslot. − In Server mode, Transmission_Position is equal to the Mac Adress (values from 1 to MaxAdrMac). Syntax: Initiator AMIS−49587 − If Server is “New” (no Mac address defined), a random number is chosen and will determine a position in the reserved Tslots for New at the end of the Repeater Call function. (values from MaxAdrMac to MaxAdrMac + 21*NB_TslotForNew) (with MaxAdrMac and NB_TslotForNew parameters from CIASE RepeaterCall service) Level parameter is used when listening for repeater call pattern: at each SubTslot, if the signal is over this level parameter multiplied by the number of bits listened, than the pattern is detected. So, on the network, there will be more Repeater if this level is set high. The default value is 1000, which is equivalent of a signal on the network between 102 and 106 dBmV. ISA_CONFIRM (TAG 62H) Description: The ISA_Confirm is sent by the AMIS−49587 to a base micro (SLAVE or MASTER) either as positive acknowledgment when a ISA_Request has successfully been transmitted by the physical layer, or as negative acknowledgment when the ISA_Request command has been received too late or if the transmitting position is wrong or if the repeater state is equal to never. In both cases the Transmission_Status byte contains a value corresponding with this positive or negative acknowledgment. The different values for the Transmission_Status field are described in the Appendix C (Transmission Status) This service is an internal service and should not be used. Without correct handling at the system level it can disable the communication. Slave Command (arguments) ISA_Confirm (Transmission_Status) Possible Response Frame Format : Length < ISA_Confirm > Transmission_Status CHK http://onsemi.com 41 AMIS−49587 MONITOR MODE COMMANDS DESCRIPTION The monitor mode is used to spy the exchanged frames on the mains. It allows the user to check the transmission quality in a definite point of the mains. In this mode, all the LTC and DB requests are allowed, but no MAC requests. The Physical layer supplies directly the frames to the base micro. THE COMMANDS AVAILABLE SPY_No_SubFrame (Tag A0h) Description: The SPY_No_SubFrame is sent by the AMIS−49587 local PHY layer to indicate that a sub−frame has not been received correctly, due to either a method not found, or a non recognition of the Start Sub−frame Delimiter (SSD). Syntax: Initiator AMIS−49587 Monitor Command (arguments) SPY_No_SubFrame (SpyData) Possible Response Frame Format : Length < SPY_No_SubFrame > SpyData CHK Table 38. DESCRIPTION OF THE SPYDATA FIELD Field Name S0 N0 S1 N1 Threshold Method Length 2 Bytes 2 Bytes 2 Bytes 2 Bytes 2 Bytes 1 Byte Value of the zero signal envelope Value of the zero noise envelope Value of the one signal envelope Value of the one noise envelope Indicates the threshold value for ASK method or the FSK factor. Indicates the found method: 0 ⇒ No method 1 ⇒ ASK0 2 ⇒ ASK1 3 ⇒ FSK (S0 ≅ S1) 4 ⇒ FSK0 (S0 > S1) 5 FSK1 (S1 > S0) 0 Synchronisation bit value when synchronisation was found 0 Indicates the gain value (0 to 7) used during the synchronization Description PAD Synchro_bit Value PAD Reception Gain 1 Bit (b7) 3 Bits (b6,b5,b4) 1 Bit (b3) 3 Bits (b2,b1,b0) SPY_SubFrame (Tag B0h) Description: The SPY_SubFrame is sent by the AMIS−49587 local PHY layer to indicate that a sub−frame has been correctly received. All information concerning the reception conditions (SpyData) and the data (PHY_sdu) are supplied in this command. Format of the SpyData field: see Table 38: Description of the SpyData field. Format of the PHY_sdu field: see [2] Sections Status Message and Master Mode (Client). Syntax: Initiator AMIS−49587 Monitor Command (arguments) Spy_SubFrame (SpyData, PHY_sdu) Possible Response Frame Format : Length < Spy_SubFrame > SpyData, PHY_sdu CHK http://onsemi.com 42 AMIS−49587 SPY_Search_Synchro (Tag C0h) Description: The SPY_Search_Synchro is sent periodically by the AMIS−49587 local MAC sub−layer to indicate synchronization is in progress. Syntax: Initiator AMIS−49587 Monitor Command (arguments) Spy_Search_Synchro () Possible Response Frame Format : Length < Spy_Search_Synchro > CHK SPY_Synchro_Found (Tag D0h) Description: The SPY_Synchro_Found is sent by the AMIS−49587 local MAC sub−layer as soon as it has correctly found synchronization when it was receiving a sub−frame. Thus, it is now synchronized and it is waiting for another correct frame for confirmation. Format of the SpyData field: see Table 38: Description of the SpyData field Syntax: Initiator AMIS−49587 Monitor Command (arguments) Spy_ Synchro_Found (SpyData) Possible Response Frame Format : Length < Spy_ Synchro_Found > SpyData CHK SPY_No_Alarm_Found (Tag E0h) Description: The SPY_No_Alarm_Found is sent by the AMIS−49587 local MAC sub−layer at the end of a time−slot, when has not found an Alarm indication in the pause time. Format of the SpyData field: see Table 38: Description of the SpyData field Format of the AlarmPattern: 2 bytes Syntax: Initiator AMIS−49587 Monitor Command (arguments) Spy_ Alarm_Found (SpyData,AlarmPattern) Possible Response Frame Format : Length < SPY_ No_Alarm_Found > SpyData, AlarmPattern CHK SPY_Alarm_Found (Tag F0h) Description: The SPY_Alarm_Found is sent by the AMIS−49587 local MAC sub−layer as soon as it has correctly found a Alarm indication in the pause time. Format of the SpyData field: see Table 38: Description of the SpyData field Format of the AlarmPattern: 2 bytes Syntax: Initiator AMIS−49587 Monitor Command (arguments) Spy_ Alarm_Found (SpyData,AlarmPattern) Possible Response Frame Format: Length < SPY__Alarm_Found > SpyData, AlarmPattern CHK http://onsemi.com 43 AMIS−49587 APPENDICES APPENDIX A: SPECIFIC BEHAVOURS Envelope calculation method The envelops are calculated using sqrt values or absolute values, depending on the baudrate and on the main frequency. The following table describes the different modes : 300, 600, 1200 bps 50 Hz Synchro Reception Sqrt Sqrt 60 Hz Sqrt Sqrt 50 Hz ABS Sqrt 2400 bps 60 Hz ABS ABS Improvement of FSK When FSK+ option is enabled, new thresholds are calculated. Than if the two envelops are under the threshold, the envelop which has the smallest gap with his threshold is used to determinate which bit is received. Or, if the two envelops are over the threshold, the envelop which has the biggest gap with his threshold is used. Conflict Between Mains And Base Micro When the AMIS−49587 receives in the same time (same time−slot) an MA_Data_Request from the base micro and a frame made up of one sub−frame with a repetition credit at zero from the mains, it ignores the frame received from the mains. In all other conflict cases, it refuses the base micro request as described in Section Arbitration and Transfer. Modifications of Time−Out Values in Slave Mode When a time−out is written with a NULL value using either the WriteConfig_Request or the WriteDB_Request command, this time−out will not be activated. After a WriteDB_Request for either the Time−out−not−addressed or the Time−out−frame−not−ok, the new value is immediately taken in account (the time−out is restarted) excepted when the local mac address is NEW and the initiator mac address is nobody. Modifications of MAC−Addresses in Slave Mode A modification of Local and/or Initiator MAC address using the WriteConfig_Request or the WriteDB_Request, can provoke some modifications of data. It is supposed that the Local MAC address (LMAC) and the Initiator MAC address (IMAC) are both corrects (LMAC < FIMA and FIMA