AR0132AT6C00XPW90

‡ AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features 1/3-Inch CMOS Digital Image Sensor AR0132AT Datasheet, Rev. 9 For the latest data sheet, please visit www.onsemi.com Features • • • • • • • • • Table 1: Superior low-light performance HD video (720p60) Linear or high dynamic range capture Video/Single Frame modes On-chip AE and statistics engine Parallel and serial output Auto black level calibration Context switching Temperature Sensor Applications • • • • Automotive imaging Video surveillance 720p60 video applications High dynamic range imaging General Description ON Semiconductor's AR0132AT is a 1/3-inch CMOS digital image sensor with an active-pixel array of 1280H x 960V. It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as auto exposure control, windowing, and both video and single frame modes. It is designed for both low light and high dynamic range scene performance. It is programmable through a simple two-wire serial interface. The AR0132AT produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. AR0132AT/D Rev. 9, 2/16 EN Key Parameters Parameter Typical Value Optical format Active pixels Pixel size Color filter array Shutter type Input clock range Output clock maximum Output Serial Parallel Frame Full resolution rate 720p Responsivity SNRMAX Maximum dynamic range Supply I/O voltage Digital Analog HiSPi Power consumption (typical) 1/3-inch (6 mm) 1280 x 960 = 1.2 Mp 3.75 m RGB Bayer, or monochrome Electronic rolling shutter 6 – 50 MHz 74.25 MHz HiSPi 12-, 14-, or 20-bit 12-bit 45 fps 60 fps 5.48 V/lux-sec 43.9 dB >115 dB 1.8 or 2.8 V* 1.8 V 2.8 V 0.4V or 1.8V 270 mW (1280 x 720 60 fps Parallel output Linear Mode) 460 mW (1280x720 60 fps Parallel output HDR Mode) –40°C to + 105° C (ambient) –40°C to + 120° C (junction) 9x9 mm iBGA Bare die Operating temperature Package options Note: *1.8V VDD_IO is recommended for better row noise performance 1 ©Semiconductor Components Industries, LLC 2016, AR0132AT: 1/3-Inch CMOS Digital Image Sensor Ordering Information Ordering Information Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0132AT6C00XPEA0-DPBR1 AR0132AT6C00XPEA0-DRBR1 AR0132AT6C00XPEA0-TPBR AR0132AT6C00XPEA0-TRBR AR0132AT6C00XPD20 AR0132AT6C00XPW90 AR0132AT6B00XPEA0-DRBR1 AR0132AT6B00XPW90 AR0132AT6G00XPEA0-DPBR1 AR0132AT6G00XPEA0-DRBR1 AR0132AT6G00XPEA0-TPBR AR0132AT6G00XPEA0-TRBR AR0132AT6M00XPEA0-DPBR1 AR0132AT6M00XPEA0-DRBR1 AR0132AT6M00XPEA0-TPBR AR0132AT6M00XPW90 AR0132AT6R00XPEA0-DPBR1 AR0132AT6R00XPEA0-DRBR1 AR0132AT6R00XPEA0-TPBR AR0132AT6R00XPEA0-TRBR AR0132AT6R00XPW90 AR0132AT6C00XPEAD3-GEVK AR0132AT6C00XPEAH3-GEVB AR0132AT6C00XPEAD3-S215-GEVK AR0132AT6C00XPEAH3-S215-GEVB AR0132AT6B00XPEAD3-GEVK AR0132AT6B00XPEAH3-GEVB AR0132AT6G00XPEAD3-GEVK AR0132AT6G00XPEAH3-GEVB AR0132AT6M00XPEAD3-GEVK AR0132AT6M00XPEAH3-GEVB AR0132AT6R00XPEAD3-GEVK AR0132AT6R00XPEAH3-GEVB RGB, 0deg CRA, iBGA Package RGB, 0deg CRA, iBGA Package RGB, 0deg CRA, iBGA Package RGB, 0deg CRA, iBGA Package RGB, 0deg CRA, Reconstruct Die RGB, 0deg CRA, Wafer RCCB, 0deg CRA, iBGA Package RCCB, 0deg CRA, Wafer RGBC, 0deg CRA, iBGA Package RGBC, 0deg CRA, iBGA Package RGBC, 0deg CRA, iBGA Package RGBC, 0deg CRA, iBGA Package Mono, 0deg CRA, iBGA Package Mono, 0deg CRA, iBGA Package Mono, 0deg CRA, iBGA Package Mono, 0deg CRA, Wafer RCCC, 0deg CRA, iBGA Package RCCC, 0deg CRA, iBGA Package RCCC, 0deg CRA, iBGA Package RCCC, 0deg CRA, iBGA Package RCCC, 0deg CRA, Wafer RGB Demo Kit, Sunex DSL945D RGB Headboard, Sunex DSL945D RGB Demo Kit, Sunex DSL215 RGB Headboard, Sunex DSL215 RCCB Demo Kit, Sunex DSL945D RCCB Headboard, Sunex DSL945D RGBC Demo Kit, Sunex DSL945D RGBC Headboard, Sunex DSL945D Mono Demo Kit, Sunex DSL945D Mono Headboard, Sunex DSL945D RCCC Demo Kit, Sunex DSL945D RCCC Headboard, Sunex DSL945D Drypack, Protective Film, Anti-Reflective Glass Drypack, Anti-Reflective Glass Tape & Reel, Protective Film, Anti-Reflective Glass Tape & Reel, Anti-Reflective Glass Drypack, Anti-Reflective Glass Drypack, Protective Film, Anti-Reflective Glass Drypack, Anti-Reflective Glass Tape & Reel, Protective Film, Anti-Reflective Glass Tape & Reel, Anti-Reflective Glass Drypack, Protective Film, Anti-Reflective Glass Drypack, Anti-Reflective Glass Tape & Reel, Protective Film, Anti-Reflective Glass Drypack, Protective Film, Anti-Reflective Glass Drypack, Anti-Reflective Glass Tape & Reel, Protective Film, Anti-Reflective Glass Tape & Reel, Anti-Reflective Glass See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. AR0132AT/D Rev. 9, 2/16 EN 2 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 High Dynamic Range Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Package Dimensions (Case 503AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 AR0132AT/D Rev. 9, 2/16 EN 3 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor General Description General Description The ON Semiconductor AR0132AT can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 960presolution image at 45 frames per second (fps). In linear mode, it outputs 12-bit raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs 12-bit compressed data using parallel output, or 12-bit or 14-bit compressed or 20-bit linearized data using the HiSPi port. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0132AT includes additional features to allow application-specific tuning: windowing and offset, adjustable auto-exposure control, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in first and last two lines of the image frame. The sensor is designed to operate in a wide temperature range (–40°C to +105°C). Functional Overview The AR0132AT is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram OTPM Active Pixel Sensor (APS) Array Timing and Control (Sequencer) Power Memory External Clock Auto Exposure and Stats Engine Pixel Data Path (Signal Processing) Analog Processing and A/D Conversion PLL Serial Output Parallel Output Trigger Two-Wire Serial Interface Control Registers User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active-Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and AR0132AT/D Rev. 9, 2/16 EN 4 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Functional Overview readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analogto-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 20-bit per pixel value. A compressing mode is further offered to allow this 20-bit pixel value to be transmitted to the host system as a 12- or 14-bit value with close to zero loss in image quality. The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. Typical Configuration: Serial Four-Lane HiSPi Interface VDD_IO 1.5kΩ2, 3 1.5kΩ2 Digital Digital I/O Core power1 power1 Master clock (6–50 MHz) EXTCLK SADDR SDATA SCLK TRIGGER OE_BAR STANDBY RESET_BAR TEST From controller VDD_IO VDD Notes: AR0132AT/D Rev. 9, 2/16 EN VDD_SLVS VDD HiSPi power1 VDD_SLVS Figure 2: VDD_PLL VAA Analog Analog PLL power1 power1 power1 VDD_PLL VAA VAA_PIX SLVS0P SLVS0N SLVS1P SLVS1N SLVS2P SLVS2N SLVS3P SLVS3N SLVSCP SLVSCN DGND AGND Digital ground Analog ground To controller VAA_PIX 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the AR0132AT demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 5 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Functional Overview Figure 3: Typical Configuration: Parallel Pixel Data Interface 1.5kΩ2, 3 1.5kΩ2 Digital Digital core I/O power1 power1 VDD_IO PLL Analog Analog power1 power1 power1 VDD Master clock (6–50 MHz) EXTCLK From Controller SADDR SDATA SCLK TRIGGER OE_BAR STANDBY RESET_BAR VDD_PLL VAA VAA_PIX DOUT [11:0] PIXCLK LINE_VALID FRAME_VALID To controller TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: AR0132AT/D Rev. 9, 2/16 EN AGND Analog ground 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the AR0132AT demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 6 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Functional Overview Table 3: Pin Descriptions, 9 x 9 mm, 63-ball iBGA Name iBGA Pin SLVS0N SLVS0P SLVS1N SLVS1P STANDBY VDD_PLL SLVSCN SLVSCP SLVS2N SLVS2P VAA EXTCLK VDD_SLVS SLVS3N SLVS3P DGND VDD AGND SADDR SCLK SDATA VAA_PIX LINE_VALID FRAME_VALID PIXCLK VDD_IO DOUT8 DOUT9 DOUT10 DOUT11 TEST DOUT4 DOUT5 DOUT6 DOUT7 TRIGGER OE_BAR DOUT0 DOUT1 DOUT2 DOUT3 RESET_BAR FLASH NC Reserved AR0132AT/D Rev. 9, 2/16 EN Type Description A2 A3 A4 A5 A8 B1 B2 B3 B4 B5 B7, B8 C1 C2 C3 C4 C5, D4, D5, E5, F5, G5, H5 A6, A7, B6, C6, D6 C7, C8 D1 D2 D3 D7, D8 E1 E2 E3 E6, F6, G6, H6, H7 F1 F2 F3 F4 F7 G1 G2 G3 G4 G7 G8 H1 H2 H3 H4 H8 Output Output Output Output Input Power Output Output Output Output Power Input Power Output Output Power Power Power Input Input I/O Power Output Output Output Power Output Output Output Output Input. Output Output Output Output Input Input Output Output Output Output Input E4 E7, E8 F8 Output HiSPi serial data, lane 0, differential N. HiSPi serial data, lane 0, differential P. HiSPi serial data, lane 1, differential N. HiSPi serial data, lane 1, differential P. Standby-mode enable pin (active HIGH). PLL power. HiSPi serial DDR clock differential N. HiSPi serial DDR clock differential P. HiSPi serial data, lane 2, differential N. HiSPi serial data, lane 2, differential P. Analog power. External input clock. HiSPi power. HiSPi serial data, lane 3, differential N. HiSPi serial data, lane 3, differential P. Digital ground. Digital power. Analog ground. Two-Wire Serial address select. Two-Wire Serial clock input. Two-Wire Serial data I/O. Pixel power. Asserted when DOUT line data is valid. Asserted when DOUT frame data is valid. Pixel clock out. DOUT is valid on rising edge of this clock. I/O supply power. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output (MSB) Manufacturing test enable pin (connect to DGND). Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Exposure synchronization input. Output enable (active LOW). Parallel pixel data output (LSB) Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Asynchronous reset (active LOW). All settings are restored to factory default. Flash control output. No connection. No connection. Must be left floating for normal operation. 7 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Functional Overview Figure 4: 9 x 9 mm 63-Ball IBGA Package 1 A 2 3 4 SLVS0N SLVS0P SLVS1N 5 6 7 8 SLVS1P VDD VDD STANDBY B VDD_PLL SLVSCN SLVSCP SLVS2N SLVS2P VDD VAA VAA C EXTCLK VDD_ SLVS SLVS3N SLVS3P DGND VDD AGND AGND D SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX E LINE_ VALID FRAME_ VALID PIXCLK FLASH DGND VDD_IO NC F DOUT8 DOUT9 DOUT10 DOUT11 DGND VDD_IO TEST G DOUT4 DOUT5 DOUT6 DOUT7 DGND VDD_IO TRIGGER OE_BAR H DOUT0 DOUT1 DOUT2 DOUT3 DGND VDD_IO VDD_IO RESET_ BAR NC Reserved Top View (Ball Down) Note: AR0132AT/D Rev. 9, 2/16 EN No ball on A1 pin, 63 balls in total in actual iBGA package. 8 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure The AR0132AT pixel array is configured as 1412 columns by 1028 rows, (see Figure 5). The dark pixels are optically black and are used internally to monitor black level. Of the right 96 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. There are 1288 columns by 972 rows of optically active pixels that can be readable. While the sensor's format is 1280 x 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. Figure 5: Pixel Array Description 1412 1028 2 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r + 1 0 0 d a rk + 4 b a rrie r 4 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r + 2 4 d a rk + 1 0 b a rrie r 1 2 8 8 x9 7 2 (re a d a b le a ctive p ixe l) 4.8 3 x3 .6 4 5 m m ^2 2 lig h t d u m m y + 1 0 b a rrie r 6 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r D a rk p ixe l AR0132AT/D Rev. 9, 2/16 EN B a rrie r p ixe l L ig h t dummy p ixe l 9 E xtra a ctive p ixe l R e a d a b le A ctive p ixe l ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Pixel Data Format Figure 6: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction Row Readout Direction Readable Active Pixel (0,0) Physical Pixel (112, 44) R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right 2corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first readable pixel location of the sensor in default condition is that of physical pixel address(112, 44). This first readable pixel location corresponds to the register x_addr_start(R0x3004)=0x0000 and the register y_addr_start(R0x3002)=0x0000. The optical center of the readable pixel array is the location of the register x_addr_end(R0x3008)=643 and the register y_addr_end(R0x3006)=485. When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 7. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 7 on page 10. Figure 7: Imaging a Scene Lens Scene Sensor (rear view) Row Readout Order Column Readout Order AR0132AT/D Rev. 9, 2/16 EN Pixel (0,0) 10 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Pixel Data Format Digital Gain Control AR0132AT supports four digital gains for the color channels: Red, Green1 (green pixels on the red rows), Green2 (green pixels on the blue rows), and Blue. Digital gain control of the AR0132AT is dependent on the configuration of the x_addr_start register. Table 4 illustrates how the digital gains are applied when x_addr_start is even or odd number. Table 4: Digital Gain Control for odd and even x_addr_start (R0x3004) Pixels Red Green1 (on Red rows) Green2 (on Blue rows) Blue AR0132AT/D Rev. 9, 2/16 EN x_addr_start Gain Register Even Odd Even Odd Even Odd Even Odd red_gain green1_gain green1_gain red_gain green2_gain blue_gain blue_gain green2_gain R0x305A R0x3056 R0x3056 R0x305A R0x305C R0x3058 R0x3058 R0x305C 11 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Output Data Format The AR0132AT image data is read out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking (see Figure 8). The amount of horizontal row time (in clocks) is programmable through R0x300C. The amount of vertical frame time (in rows) is programmable through R0x300A. LINE_VALID (LV) is HIGH during the shaded region of Figure 8. Optional Embedded Register setup information and Histogram statistics information are available in first two and last row of image data. Figure 8: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 HORIZONTAL BLANKING VALID IMAGE Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Readout Sequence Typically, the readout window is set to a region including only active pixels. The user has the option of reading out dark regions of the array, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. AR0132AT/D Rev. 9, 2/16 EN 12 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Parallel Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 968 rows of 1284 columns each. The FRAME_VALID (FV) and LINE_VALID (LV) signals indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12-bit pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is deasserted are called vertical blanking. PIXCLK cycles that occur when only LV is deasserted are called horizontal blanking. Figure 9: Default Pixel Output Timing PIXCLK FV LV DOUT[11:0] P0 Vertical Blanking Horizontal Blanking P1 P2 P3 P4 Valid Image Data P5 Pn Horizontal Blanking Vertical Blanking LV and FV The timing of the FV and LV outputs is closely related to the row time and the frame time. FV will be asserted for an integral number of row times, which will normally be equal to the height of the output image. LV will be asserted during the valid pixels of each row. The leading edge of LV will be offset from the leading edge of FV by six PIXCLKs. Normally, LV will only be asserted if FV is asserted; this is configurable as described below. LV Format Options The default situation is for LV to be de-asserted when FV is de-asserted. By configuring R0x306E[1:0], the LV signal can take two different output formats. The formats for reading out four lines and two vertical blanking lines are shown in Figure 10. AR0132AT/D Rev. 9, 2/16 EN 13 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Figure 10: LV Format Options FV Default LV FV Continuous LV LV The timing of an entire frame is shown in Figure 16: “Line Timing and FRAME_VALID/ LINE_VALID Signals,” on page 17. Serial Output Data Timing The AR0132AT also uses ON Semiconductor's High-Speed Serial Pixel Interface (“HiSPi”). The physical interface comprises differential serial data lines and a differential clock line. The protocol layer formats the data and synchronization signals separately, with Sync codes defined for active image boundaries. Figure 11 shows the configuration between the HiSPi transmitter and the receiver. There are two options for HiSPi output: SLVS or HiVCM mode selectable through register 0x306E bit 9. Setting this bit to 0 selects SLVS; setting the bit to 1 selects HiVCM. Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram A camera containing the HiSPi transmitter Tx PHY0 AR0132AT/D Rev. 9, 2/16 EN A host (DSP) containing the HiSPi receiver Dp0 Dp0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 14 Rx PHY0 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format HiSPi Physical Layer The HiSPi physical layer has four data lanes and an associated clock lane. Depending on the sensor operating mode and data rate, it can be configured to use either 2, 3, or 4 lanes. The PHY will serialize a 12- to 20-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the following falling edge of clock. Figure 12 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. Figure 12: Timing Diagram TxPost cp …. cn TxPre dp …. MSB dn LSB 1 UI DLL Timing Adjustment The AR0132AT includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. delay data _lane 0 AR0132AT/D Rev. 9, 2/16 EN delay delay DATA3_DEL[2:0] DATA2_DEL[2:0] DATA1_DEL[2:0] CLOCK_DEL[2:0] Block Diagram of DLL Timing Adjustment DATA0_DEL[2:0] Figure 13: delay delay data _lane 1 clock _lane 0 data _lane 2 data _lane 3 15 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Figure 14: Delaying the Clock with Respect to Data 1 UI dataN (DATAN_DEL = 000) cp (CLOCK_DEL = 000) cp (CLOCK_DEL = 001) cp (CLOCK_DEL = 010) cp (CLOCK_DEL = 011) cp (CLOCK_DEL = 100) cp (CLOCK_DEL = 101) c p (CLOCK_DEL = 110) cp (CLOCK_DEL =111) increasing CLOCK_DEL[2:0] increases clock delay Figure 15: Delaying Data with Respect to the Clock cp ( CLOCK_DEL = 000) dataN (DATAN_DEL = 000) dataN(DATAN_DEL = 001) dataN(DATAN_DEL = 010) dataN(DATAN_DEL = 011) dataN(DATAN_DEL = 100) dataN(DATAN_DEL = 101) dataN(DATAN_DEL = 110) dataN(DATAN_DEL = 111) increasing DATAN_DEL[2:0] increases data delay t DLLSTEP 1 UI HiSPi Protocol Layer The HiSPi protocol is described the HiSPi Protocol Specification document. Contact your local Field Applications Engineer or sales representative to get a copy. AR0132AT/D Rev. 9, 2/16 EN 16 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Frame Time The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array. The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time (tROW) is the period from the first pixel output in a row to the first pixel output in the next row. The row time and frame time are defined by equations in Table 5. Figure 16: Line Timing and FRAME_VALID/LINE_VALID Signals ... FRAME_VALID ... LINE_VALID ... P1 Table 5: A Q A Q A P2 Frame Time (Example Based on 1280 x 960, 45 Frames Per Second) Default Timing at 74.25 MHz Parameter Name Equation A Active data time P1 Frame start blanking Context A: R0x3008 - R0x3004 + 1 Context B: R0x308E - R0x308A + 1 6 (fixed) P2 Frame end blanking 6 (fixed) Q Horizontal blanking R0x300C - A A+Q (tROW) Line (Row) time R0x300C V Vertical blanking Nrows x (A + Q) Frame valid time F Total frame time Context A: (R0x300A-(R0x3006-R0x3002+1)) x (A + Q) Context B: ((R0x30AA-(R0x3090-R0x308C+1)) x (A + Q) Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2 Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2 V + (N rows x (A + Q)) 1280 pixel clocks = 17.23s 6 pixel clocks = 0.08s 6 pixel clocks = 0.08s 370 pixel clocks = 4.98s 1650 pixel clocks = 22.22s 49,500 pixel clocks = 666.66s 1,584,000 pixel clocks = 21.33ms 1,633,500 pixel clocks = 22.22ms Sensor timing is shown in terms of pixel clock cycles (see Figure 8 on page 12). The recommended pixel clock frequency is 74.25 MHz. The vertical blanking and the total frame time equations assume that the integration time (coarse integration time plus fine integration time) is less than the number of active lines plus the blanking lines: Window Height + Vertical Blanking (EQ 1) If this is not the case, the number of integration lines must be used instead to determine the frame time, (see Table 6). In this example, it is assumed that the coarse integration time control is programmed with 2000 rows and the fine integration time total is zero. For master mode, if the integration time registers exceed the total readout time, then the vertical blanking time is internally extended automatically to adjust for the additional integration time required. This extended value is not written back to the frame_length_lines register. The frame_length_lines register can be used to adjust frame-to-frame readout time. This register does not affect the exposure time but it may extend the readout time. AR0132AT/D Rev. 9, 2/16 EN 17 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Output Data Format Table 6: Parameter F’ Frame Time: Long Integration Time Name Equation (Number of Pixel Clock Cycles) Default Timing at 74.25 MHz Total frame time (long integration time) Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2 Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2 3,300,012 pixel clocks = 44.44ms Note: The AR0132AT uses column parallel analog-digital converters; thus short line timing is not possible. The minimum total line time is 1650 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 370. Exposure Total integration time is the result of Coarse_Integration_Time and Fine_Integration_Time registers in Linear mode and is the result of Coarse_Integration_Time in HDR mode, and it depends also on whether manual or automatic exposure is selected. The actual total integration time, tINT is defined as: tINT = tINTCoarse - 410 - tINTFine (EQ 2) = (number_of_lines_of_integration x line_time) - ((410 + number_of_pixels_of_integration) x pixel_time) where: – Number of Lines of Integration (Auto Exposure Control: Enabled) When automatic exposure control (AEC) is enabled, the number of lines of integration may vary from frame to frame, with the limits controlled by R0x311E (minimum auto exposure time) and R0x311C (maximum auto exposure time). – Number of Lines of Integration (Auto Exposure Control: Disabled) If AEC is disabled, the number of lines of integration equals the value in R0x3012 (context A) or R0x3016 (context B). – Number of Pixels of Integration The number of fine integration time pixels is independent of AEC mode (enabled or disabled): • Context A: the number of pixels of integration equals the value in R0x3014. • Context B: the number of pixels of integration equals the value in R0x3018. • where < Fine_Integration_Time < (Line_Length_Pck - 545) in linear mode. Typically, the value of the Coarse_Integration_Time register is limited to the number of lines per frame (which includes vertical blanking lines), such that the frame rate is not affected by the integration time. For more information on coarse and fine integration time settings limits, please refer to the Register Reference document. Note: AR0132AT/D Rev. 9, 2/16 EN In HDR mode, there are specific limitations on coarse_integration_time due to the number of line buffers available. Please refer to the section called “HDR Specific Exposure Settings” on page 21. 18 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode High Dynamic Range Mode By default, the sensor powers up in Linear Mode, however, the AR0132AT can be configured to run in HDR mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle 120dB of dynamic range. The sensor also features a linear mode. In HDR mode, the sensor sequentially captures three exposures by maintaining three separate read and reset pointers that are interleaved within the rolling shutter readout. The intermediate pixel values are stored in line buffers while waiting for the three exposure values to be present. As soon as a pixel's three exposure values are available, they are combined to create a linearized 20-bit value for each pixel’s response. This 20-bit value is then optionally compressed back to a 12- or 14-bit value for output. For 14-bit mode, the compressing is lossless. In 12-bit mode, there is minimal data loss. Figure 17 shows the HDR data compression: Figure 17: HDR Data Compression Digital output code Decompressed linear output ADC max code K2 = knee point 2 K1 = knee point 1 Piece-wise Compressed Signal Output From Sensor Pout = P Signal Response to Light Intensity The HDR mode is selected when Operation_Mode_Ctrl, R0x3082[1:0] = 0. Further controls on exposure time limits and compressing are controlled by R0x3082[5:2] and R0x31D0. More details can be found in the AR0132AT Register Reference. In HDR mode, when compression is used, there are two types of knee-points: (i) T1/T2 and T2/T3 capture knee-points and (ii) POUT and POUT2 compression knee-points (Figure 17). Aligning the capture knee-points on top of the compression knee-points, AR0132AT/D Rev. 9, 2/16 EN 19 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode can avoid code losses (SNR loss) in the compression. Table 7 and Table 8 below show the knee points for the different modes. Alternatively, the sensor automatically reports the knee points and can be read directly from registers R0x319A and R0x319C. Table 7: Knee Points for Compression to 14 Bits T1/T2 Exposure Ratio (R1) R0x3082[3:2] 4x P1 POUT1 = P1 P2 POUT2 = (P2 - P1)/ R1 + POUT1 212 4096 214 7168 8x 212 4096 215 7680 16x 212 4096 216 7936 Table 8: T2/T3 Exposure Ratio (R2) R0x3082[5:4] PMAX POUTMAX = (PMAX - P2)/ (R1*R2) + POUT2 4x 8x 16x 4x 8x 16x 4x 8x 16x 216 217 218 217 218 219 218 219 220 10240 10752 11008 10752 11264 11520 11008 11520 11776 Knee Points for Compression to 12 Bits T1/T2 Exposure Ratio (R1) R0x3082[3:2] POUT1 = P1 P2 POUT2 = (P2 - P1)/ (R1* 4)+ POUT1 4x 11 2 2048 214 2944 8x 211 2048 215 3008 16x 211 2048 216 3040 AR0132AT/D Rev. 9, 2/16 EN P1 20 T2/T3 Exposure Ratio (R2) R0x3082[5:4] PMAX POUTMAX = (PMAX - P2)/ (R1*R2*4) + POUT2 4x 8x 16x 4x 8x 16x 4x 8x 16x 216 217 218 217 218 219 218 219 220 3712 3840 3904 3776 3904 3968 3808 3936 4000 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode HDR Specific Exposure Settings In HDR mode, pixel values are stored in line buffers while waiting for all 3 exposures to be available for final pixel data combination. There are 42 line buffers used to store intermediate T1 data. Due to this limitation, the maximum coarse integration time possible is equal to 42*T1/T2 lines. For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the maximum number of integration lines is 42*16 = 672 lines. If coarse integration time is greater than this, the T2 integration time will stay at 42 lines. The sensor calculates the ratio internally, enabling the linearization to be performed. If companding is being used then relinearization would still follow the programmed ratio. For example, if the T1/T2 ratio was programmed to 16x but coarse integration was increased beyond 672 then one would still use the 16x relinearization formulas. An additional limitation is the maximum number of exposure lines in relation to the frame_length_lines register. In Linear mode, as described on page 20, maximum coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the coarse integration time register controls T1, the max coarse_integration time is frame_length_lines - 45. Putting the two criteria listed above together, it can be summarized as follows: maximum coarse_integration_time = minimum  42  T1  T2, frame_length_lines – 45  (EQ 3) In HDR mode, subline integration is not utilized. As such, fine integration time register changes will have no effect on the image. There is also a limitation of the minimum number of exposure lines that can be used. This is summarized in the following formula: minimum coarse_integration_time =  0.5 *  T1  T2   T2  T3  (EQ 4) Due to limitation on the internal floating point calculation, the exact ratio specified by the RATIO_T2_T3 (R0x3082[5:4]) may not be achievable. Motion Compensation In typical multi-exposure HDR systems, motion artifacts can be created when objects move during the T1, T2 or T3 integration time. When this happens, edge artifacts can potentially be visible and might look like a ghosting effect. To correct this feature, the AR0132AT has special 2D motion compensation circuitry that detects motion artifacts and corrects the image accordingly. There are two motion compensation options available. One using the default HDR motion compensation feature can be enabled by setting R0x318C[14] = 1. Additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. These can be set in R0x318C–R0x3190. The other is using the DLO method of HDR combination. When using DLO, R0x318C[14] is ignored. DLO is enabled by setting R0x3190[13] = 1. Noise filtering is enabled by setting R0x3190[14] = 1. For more information, please refer to the AR0132AT Register Reference document. AR0132AT/D Rev. 9, 2/16 EN 21 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Real-Time Context Switching Real-Time Context Switching In the AR0132AT, the user may switch between two full register sets (listed in Table 9) by writing to a context switch change bit in R0x30B0[13]. This context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time. Table 9: Real-Time Context-Switch Registers Register Number Register Description Y_Addr_Start X_Addr_Start Y_Addr_End X_Addr_End Coarse_Integration_Time Fine_Integration_Time Y_Odd_Inc Column Gain Green1_Gain (GreenR) Blue_Gain Red_Gain Green2_Gain (GreenB) Global_Gain Frame_Length_Lines Digital_Binning Operation_Mode_Ctrl Context A Context B R0x3002 R0x3004 R0x3006 R0x3008 R0x3012 R0x3014 R0x30A6 R0x30B0[5:4] R0x3056 R0x3058 R0x305A R0x305C R0x305E R0x300A R0x3032[1:0] 0x3082 R0x308C R0x308A R0x3090 R0x308E R0x3016 R0x3018 R0x30A8 R0x30B0[9:8] R0x30BC R0x30BE R0x30C0 R0x30C2 R0x30C4 R0x30AA R0x3032[5:4] 0x3084 Features See the AR0132AT Register Reference for additional details. Reset The AR0132AT may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset of Logic The RESET_BAR pin can be connected to an external RC circuit for simplicity. The recommended RC circuit uses a 10k resistor and a 0.1F capacitor. The rise time for the RC circuit is 1s maximum. Soft Reset of Logic Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. This bit is a self-resetting bit and also returns to “0” during two-wire serial interface reads. AR0132AT/D Rev. 9, 2/16 EN 22 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Clocks The AR0132AT requires one clock input (EXTCLK). PLL-Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and two divider stages to generate the output clock. The clocking structure is shown in Figure 18. PLL control registers can be programmed to generate desired master clock frequency. Note: Figure 18: The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined. PLL-Generated Master Clock PLL Setup PLL Input Clock EXTCLK Pre PLL Div (PFD) Pre_pll_clk_div PLL Output Clock SYSCLK PLL Multiplier (VCO) PLL Output Div 1 PLL Output Div 2 pll_multiplier vt_sys_clk_div vt_pix_clk_div PIXCLK The PLL is enabled by default on the AR0132AT. To configure and use the PLL: 1. Bring the AR0132AT up as normal; make sure that fEXTCLK is between 6 and 50MHz and ensure the sensor is in software standby (R0x301A-B[2]= 0). PLL control registers must be set in software standby. 2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_siv, and vt_pix_clk_div based on the desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, P1, and P2 values to achieve the desired fPIXCLK using this formula: fPIXCLK= (fEXTCLK × M) / (N × P1 x P2) where M = PLL_Multiplier N = Pre_PLL_Clk_Div P1 = Vt_Sys_Clk_Div P2 = Vt_PIX_Clk_Div 3. Wait 1ms to ensure that the VCO has locked. 4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-generated clock. Notes: 1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting R0x30B0[14]=1. However, only the parallel data interface is supported with the PLL bypassed. The PLL is always bypassed in software standby mode. To disable the PLL, the sensor must be in standby mode (R0x301A[2] = 0) 2. The following restrictions apply to the PLL tuning parameters: 32  M  255 AR0132AT/D Rev. 9, 2/16 EN 23 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features 1  N  63 P1 = 1 2 4 6 8 10 12 14 16 4  P2  16 3. The VCO frequency, defined as f VCO = f EXTCLK  M  N must be within 384-768 MHz. 4. When PLL_Multiplier is odd, 2 MHz  fEXTCLK / N  24 MHz. 5. If using HiSPi output mode, use the following settings for P2 (Vt_Pix_Clk_Div). 5a. If 20-bit mode (4 lanes): set P2 (R0x302A) = 5 5b. If 12-/14-bit mode (3 lanes): set P2 (R0x302A) = 5 5c. If 12-bit mode (2 lanes): set P2 (R0x302A) = 6 5d. If 14-bit mode (2 lanes): set P2 (R0x302A) = 7 The user can utilize the Register Wizard tool accompanying DevWare to generate PLL settings given a supplied input clock and desired output frequency. Spread-Spectrum Clocking To facilitate improved EMI performance, the external clock input allows for spread spectrum sources, with no impact on image quality. Limits of the spread spectrum input clock are: • 5% maximum clock modulation • 35 KHz maximum modulation frequency • Accepts triangle wave modulation, as well as sine or modified triangle modulations. Stream/Standby Control The sensor supports two standby modes: Hard Standby and Soft Standby. In both modes, external clock can be optionally disabled to further minimize power consumption. If this is done, then the “Power-Up Sequence” on page 51 must be followed. Soft Standby Soft Standby is a low power state that is controlled through register R0x301A[2]. Depending on the value of R0x301A[4], the sensor will go to standby after completion of the current frame readout (default behavior) or after the completion of the current row readout. When the sensor comes back from Soft Standby, previously written register settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high. A specific sequence needs to be followed to enter and exit from Soft Standby. Entering Soft Standby: 1. R0x301A[12] = 1 if serial mode was used 2. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW. 3. External clock can be turned off to further minimize power consumption (Optional) Exiting Soft Standby: 1. Enable external clock if it was turned off 2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH. 3. R0x301A[12] = 0 if serial mode is used AR0132AT/D Rev. 9, 2/16 EN 24 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Hard Standby Hard Standby puts the sensor in lower power state; previously written register settings are still maintained. A specific sequence needs to be followed to enter and exit from Hard Standby. Entering Hard Standby: 1. R0x301A[8] = 1 2. R0x301A[12] = 1 if serial mode was used 3. Assert STANDBY pin 4. External clock can be turned off to further minimize power consumption (Optional) Exiting Hard Standby: 1. Enable external clock if it was turned off 2. De-assert STANDBY pin 3. Set R0x301A[8] = 0 Window Control Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and starting coordinates of the image window. The exact window height and width out of the sensor is determined by the difference between the Y address start and end registers or the X address start and end registers, respectively. The AR0132AT allows different window sizes for context A and context B. Blanking Control Horizontal blank and vertical blank times are controlled by the line_length_pck and frame_length_lines registers, respectively. • Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting the X window size from the line_length_pck register. The minimum horizontal blanking is 370 pixel clocks. • Vertical blanking is specified in terms of numbers of lines. It is calculated by subtracting the Y window size from the frame_length_lines register. The minimum vertical blanking is 26 lines. The actual imager timing can be calculated using Table 5 on page 17 and Table 6 on page 18, which describe the Line Timing and FV/LV signals. When in HDR mode, the maximum size is 1280 x 960. AR0132AT/D Rev. 9, 2/16 EN 25 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Readout Modes Digital Binning By default, the resolution of the output image is the full width and height of the FOV as defined above. The output resolution can be reduced by digital binning. For RGB and monochrome mode, this is set by the register R0x3032. For Context A, use bits [1:0], for Context B, use bits [5:4]. Available settings are: 0b00 = No binning 0b01 = Horizontal binning 0b10 = Horizontal and vertical binning Binning gives the advantage of reducing noise at the cost of reduced resolution. When both [horizontal and vertical binning are used, a 2x improvement in SNR is achieved, therefore improving low light performance. Binning results in a smaller resolution image, but the FOVs between binned and unbinned images are the same. Bayer Space Resampling All of the pixels in the FOV contribute to the output image in digital binning mode. This can result in a more pleasing output image with reduced subsampling artifacts. It also improves low-light performance. For RGB mode, resampling can be enabled by setting of register 0x306E[4] = 1. Mirror Column Mirror Image By setting R0x3040[14] = 1, the readout order of the columns is reversed, as shown in Figure 19. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in the imaging array. When using horizontal mirror mode, the user must retrigger column correction. Please refer to the column correction section to see the procedure for column correction retriggering. Bayer resampling must be enabled, by setting R0x306E[4] = 1. Figure 19: Eight Pixels in Normal and Column Mirror Readout Modes LV Normal readout DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] G3[11:0] R3[11:0] Reverse readout DOUT[11:0] AR0132AT/D Rev. 9, 2/16 EN G3[11:0] R3[11:0] G2[11:0] R2[11:0] G1[11:0] R1[11:0] G0[11:0] R0[11:0] 26 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Row Mirror Image By setting R0x3040[15] = 1, the readout order of the rows is reversed as shown in Figure 20. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in the imaging array. When using horizontal mirror mode, the user must retrigger column correction. Please refer to the column correction section to see the procedure for column correction retriggering. Figure 20: Six Rows in Normal and Row Mirror Readout Modes FV Normal readout Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0] DOUT[11:0] Reverse readout DOUT[11:0] Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0] Row0 [11:0] Maintaining a Constant Frame Rate Maintaining a constant frame rate while continuing to have the ability to adjust certain parameters is the desired scenario. This is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. Therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. By default, the following register fields cause a “bubble” in the output rate (that is, the vertical blank increases for one frame) if they are written in video mode, even if the new value would not change the resulting frame rate. The following list shows only a few examples of such registers; a full listing can be seen in the AR0132AT Register Reference. • x_addr_start • x_addr_end • y_addr_start • y_addr_end • frame_length_lines • line_length_pclk • coarse_integration_time • fine_integration_time • read_mode The size of this bubble is (Integration_Time × tROW), calculating the row time according to the new settings. The Coarse_Integration_Time and Fine_Integration_Time fields may be written to without causing a bubble in the output rate under certain circumstances. Because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without special provisions in the hardware. Writes to these registers take effect two frames after the frame they are written, which allows the integration time to increase without interrupting the output or producing a corrupt frame (as long as the change in integration time does not affect the frame time). AR0132AT/D Rev. 9, 2/16 EN 27 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Synchronizing Register Writes to Frame Boundaries Changes to most register fields that affect the size or brightness of an image take effect on two frames after the one during which they are written. These fields are noted as “synchronized to frame boundaries” in the AR0132AT Register Reference. To ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of FV and before the trailing edge of FV. As a special case, in single frame mode, register writes that occur after FV but before the next trigger will take effect immediately on the next frame, as if there had been a Restart. However, if the trigger for the next frame occurs during FV, register writes take effect as with video mode. Fields not identified as being frame-synchronized are updated immediately after the register write is completed. The effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. Restart To restart the AR0132AT at any time during the operation of the sensor, write a “1” to the Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is interrupted immediately. Second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in video mode). The current row completes before the new frame is started, so the time between issuing the Restart and the beginning of the next frame can vary by about tROW. Image Acquisition Modes The AR0132AT supports two image acquisition modes: video (master) and single frame. Video The video mode takes pictures by scanning the rows of the sensor twice. On the first scan, each row is released from reset, starting the exposure. On the second scan, the row is sampled, processed, and returned to the reset state. The exposure for any row is therefore the time between the first and second scans. Each row is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects as is typical with electronic rolling shutter sensors. Single Frame The single-frame mode operates similar to the video mode. It also scans the rows of the sensor twice, first to reset the rows and second to read the rows. Unlike video mode where a continuous stream of images are output from the image sensor, the single-frame mode outputs a single frame in response to a high state placed on the TRIGGER input pin. As long as the TRIGGER pin is held in a high state, new images will be read out. After the TRIGGER pin is returned to a low state, the image sensor will not output any new images and will wait for the next high state on the TRIGGER pin. The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal is low). The pin is level sensitive rather than edge sensitive. As such, image integration will only begin when the sensor detects that the TRIGGER pin has been held high for 3 consecutive clock cycles. If the trigger signal is applied to multiple sensors at the same time, the single frame output of the sensors will be synchronized to within 1 PIXCLK if is PLL disabled or 2 PIXCLKs if PLL is enabled. AR0132AT/D Rev. 9, 2/16 EN 28 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features During integration time of single-frame mode and video mode, the FLASH output pin is at high. Continuous Trigger In certain applications, multiple sensors need to have their video streams synchronized (for example, surround view or panorama view applications). The TRIGGER pin can also be used to synchronize output of multiple image sensors together and still get a video stream. This is called continuous trigger mode. Continuous trigger is enabled by holding the TRIGGER pin high. Alternatively, the TRIGGER pin can be held high until the stream bit is enabled (R0x301A[2]=1) then can be released for continuous synchronized video streaming. If the TRIGGER pins for all connected AR0132AT sensors are connected to the same control signal, all sensors will receive the trigger pulse at the same time. If they are configured to have the same frame timing, then the usage of the TRIGGER pin guarantees that all sensors will be synchronized within 1 PIXCLK cycle if PLL is disabled, or 2 PIXCLK cycles if PLL is enabled. With continuous trigger mode, the application can now make use of the video streaming mode while guaranteeing that all sensor outputs are synchronized. As long as the initial trigger for the sensors takes place at the same time, all subsequent video streams will be synchronous. Temperature Sensor The AR0132AT sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1. After this, the temperature sensor output value can be read from R0x30B2[10:0]. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of listed in the equation below can be used to convert the ADC output value to the final temperature in degrees Celsius. Temperature = slope  R0x30B2  10:0  + T 0 (EQ 5) For this conversion, a minimum of 2 known points are needed to construct the line formula by identifying the slope and y-intercept "T0". These calibration values can be read from registers R0x30C6 and R0x30C8 which correspond to value read at 70°C and 55°C respectively. Once read, the slope and y-intercept values can be calculated and used in the above equation. For more information on the temperature sensor registers, refer to the AR0132AT Register Reference. AR0132AT/D Rev. 9, 2/16 EN 29 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Automatic Exposure Control The integrated automatic exposure control (AEC) is responsible for ensuring that optimal settings of exposure and gain are computed and updated every other frame. AEC can be enabled or disabled by R0x3100[0]. When AEC is disabled (R0x3100[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers and the manual gain value in the gain registers. When AEC is enabled (R0x3100[0]=1), the target luma value in linear mode is set by R0x3102. For the AR0132AT this target luma has a default value of 0x0800 or about half scale. For HDR mode, the luma target maximum auto exposure value is limited by R0x311C; the minimum auto exposure is limited by R0x311E. These values are in units of line-times. The exposure control measures current scene luminosity by accumulating a histogram of pixel values while reading out a frame. It then compares the current luminosity to the desired output luminosity. Finally, the appropriate adjustments are made to the exposure time and gain. All pixels are used, regardless of color or mono mode. In HDR mode, the coarse and fine integration time is the longest integration time of the three integration, the other two shorter integration are generated automatically base on the predefined exposure ratios. Embedded Data and Statistics The AR0132AT has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout: 1. Embedded Data: If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. 2. Embedded Statistics: If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. Note: Figure 21: One must have both embedded data and embedded statistics enabled or disabled together. Frame Format with Embedded Data Lines Enabled Register Data Image HBlank Status & Statistics Data VBlank AR0132AT/D Rev. 9, 2/16 EN 30 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Embedded Data The embedded data contains the configuration of the image being displayed. This includes all register settings used to capture the current frame. The registers embedded in these rows are as follows: Line 1: Registers R0x3000 to R0x312F Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF Note: All non-defined registers will have a value of 0. In parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8 MSB and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel word. For example, of a register value of 0x1234 is to be transmitted, it will be transmitted over 2, 12-bit pixels as follows: 0x120, 0x340. The first pixel of each line in the embedded data is a tag value of 0x0A0. This signifies that all subsequent data is 8 bit data aligned to the MSB of the 12-bit pixel. The figure below summarizes how the embedded data transmission looks like. It should be noted that data, as shown in Figure 22, is aligned to the MSB of each word: Figure 22: Format of Embedded Data Output within a Frame data_format_ code =8'h0A 8'hAA {register_ address_MSB} 8'hA5 {register_ address_LSB} 8'h5A {register_ value_MSB} 8'h5A Data line 1 data_format_ code =8'h0A Data line 2 8'hAA {register_ value_LSB} 8'h5A {register_ address_MSB} 8'hA5 {register_ value_LSB} {register_ address_LSB} 8'h5A {register_ value_MSB} 8'h5A 8'h5A The data embedded in these rows are as follows: • 0x0A0 - identifier • 0xAA0 • Register Address MSB of the first register • 0xA50 • Register Address LSB of the first register • 0x5A0 • Register Value MSB of the first register addressed • 0x5A0 • Register Value LSB of the first register addressed • 0x5A0 • Register Value MSB of the register at first address + 2 • 0x5A0 • Register Value LSB of the register at first address + 2 • 0x5A0 • etc. AR0132AT/D Rev. 9, 2/16 EN 31 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Embedded Statistics The embedded statistics contain frame identifiers and histogram information of the image in the frame. This can be used by downstream auto-exposure algorithm blocks to make decisions about exposure adjustment. This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 212, 120 evenly spaced bins for values 212 to 216, 60 evenly spaced bins for values 216 to 220. In HDR with a 16x exposure ratio, this approximately corresponds to the T1, T2, T3 exposures respectively. The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signifies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel. The figure below summarizes how the embedded statistics transmission looks like. It should be noted that data, as shown in Figure 23, is aligned to the msb of each word: Figure 23: Format of Embedded Statistics Output within a Frame data_format_ code =8'h0B #words = 10’h1EC {2’b00, frame _count MSB} {2’b00, frame _count LSB} {2’b00, frame _ID MSB} {2’b00, frame histogram bin0 [19:10] _ID LSB} histogram bin0 [9:0] stats line 1 histogram bin1 [19:10] data_format_ code =8'h0B stats line 2 #words = 10’h1C mean [ 19:10] histogram bin1 [9:0] mean [9:0] lowEndMean lowEndMean [9:0] [19:10] histogram bin243 [19:10] hist_begin [19:10] hist_begin [9:10] perc_lowEnd [19:10] perc_lowEnd [9:0] histogram bin243 [9:0] hist_end [19:10] 8'h07 8'h07 hist_end [9:10] norm_abs_dev lnorm_abs_dev [9:0] [19:10] 8'h07 The statistics embedded in these rows are as follows: Line 1: • 0x0B0 - identifier • Register 0x303A - frame_count • Register 0x31D2 - frame ID • Histogram data - histogram bins 0-243 Line 2: • 0x0B0 (identifier) • Mean • Histogram Begin • Histogram End • Low End Histogram Mean • Percentage of Pixels Below Low End Mean • Normal Absolute Deviation Gain Digital Gain Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B). There are also registers that allow individual control over each Bayer color (GreenR(Green1_gain) by R0x3056, Blue_gain by R0x3058, Red_gain by R0x305A, GreenB(Green2_gain) by R0x305C). AR0132AT/D Rev. 9, 2/16 EN 32 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125 while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital gain to 01000011. Analog Gain The AR0132AT has a column parallel architecture and therefore has an Analog gain stage per column. There are two stages of analog gain, the first stage can be set to 1x, 2x, 4x or 8x. This is can be set in R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B). The second stage is capable of setting an additional 0.5X, 0.75X, 1X or 1.25x gain which can be set in R0x3EE4[9:8]. 0.5X or 0.75X gain other than 1.0X or 1.25X gain will not affect device reliability but could parts to deviate from ON Semiconductor's official specification. This allows the maximum possible analog gain to be set to 10x. Black Level Correction Black level correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Setting R0x30EA[15] disables the automatic black level correction. Default setting is for automatic black level calibration to be enabled. The automatic black level correction measures the average value of pixels from a set of optically black lines in the image sensor. The pixels are averaged as if they were lightsensitive and passed through the appropriate gain. This line average is then digitally low-pass filtered over many frames to remove temporal noise and random instabilities associated with this measurement. The new filtered average is then compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction value is increased by a predetermined amount. If it is above the maximum level, the offset correction value is decreased by a predetermined amount. The high and low thresholds have been calculated to avoid oscillation of the black level from below to above the targeted black level. Row-wise Noise Correction Row (Line)-wise Noise Correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Clearing R0x3044[10] disables the row noise correction. Default setting is for row noise correction to be enabled. Row-wise noise correction is performed by calculating an average from a set of optically black pixels at the start of each line and then applying each average to all the active pixels of the line. Column Correction The AR0132AT uses column parallel readout architecture to achieve fast frame rate. Without any corrections, the consequence of this architecture is that different column signal paths have slightly different offsets that might show up on the final image as structured fixed pattern noise. AR0132AT/D Rev. 9, 2/16 EN 33 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features The AR0132AT has column correction circuitry that measures this offset and removes it from the image before output. This is done by sampling dark rows containing tied pixels and measuring an offset coefficient per column to be corrected later in the signal path. Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default this register is set to 0x7, which means that eight rows are used. This is the recommended value. Other control features regarding column correction can be viewed in the AR0132AT Register Reference. Any changes to column correction settings need to be done when the sensor streaming is disabled and the appropriate triggering sequence must be followed as described below. Column Correction Triggering Column correction requires a special procedure to trigger depending on which state the sensor is in. Column Correction Triggering on Startup When streaming the sensor for the first time after power up, a special sequence needs to be followed to make sure that the column correction coefficients are internally calculated properly. 1. Follow proper power up sequence for power supplies and clocks 2. Apply sequencer settings if needed (Linear or HDR mode) 3. Apply frame timing and PLL settings as required by application 4. Set analog gain to 1x and low conversion gain (R0x30B0=0x1300) 5. Enable column correction and settings (R0x30D4=0xE007) 6. Disable auto re-trigger for change in conversion gain or col_gain, and enable column correction always. (R0x30BA = 0x0008). 7. Enable streaming (R0x301A[2] = 1) or drive the TRIGGER pin HIGH. 8. Wait 9 frames to settle. (First frame after coming up from standby is internally column correction disabled.) 9. Disable streaming (R0x301A[2] = 0) After this, the sensor has calculated the proper column correction coefficients and the sensor is ready for streaming. Any other settings (including gain, integration time and conversion gain etc.) can be done afterwards without affecting column correction. Column Correction Retriggering due to Mode Change Since column offsets are sensitive to changes in the analog signal path, such changes require column correction circuitry to be retriggered for the new path. Examples of such mode changes include: horizontal mirror, vertical mirror, changes to column correction settings. When such changes take place, the following sequence needs to take place: 1. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW. 2. Enable streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH. 3. Wait 9 frames to settle. Note: AR0132AT/D Rev. 9, 2/16 EN The above steps are not needed if the sensor is being reset (soft or hard reset) upon the mode change. 34 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Features Defective Pixel Correction Defective Pixel Correction is intended to compensate for defective pixels by replacing their value with a value based on the surrounding pixels, making the defect less noticeable to the human eye. The defect pixel correction feature supports up to 200 defects. The locations of defective pixels are stored in a table on chip during the manufacturing process; this table is accessible through the two-wire serial interface. There is no provision for later augmenting the defect table entries. The DPC algorithm is one-dimensional, calculating the resulting averaged pixel value based on nearby pixels within a row. The algorithm distinguishes between color and monochrome parts; for color parts, the algorithm uses nearest neighbor in the same color plane. At high gain, long exposure, and high temperature conditions, the performance of this function can degrade. Test Patterns The AR0132AT has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 10. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. Note: Table 10: Turn off black level calibration (BLC) by setting R0x30EA[15] = 1 when Test Pattern is enabled. Test Pattern Modes Test_Pattern_Mode Test Pattern Output 0d0 0d1 0d2 0d3 0d256 No test pattern (normal operation) Solid color test pattern 100% color bar test pattern Fade-to-gray color bar test pattern Walking 1s test pattern (12-bit) Color Field When the color field mode is selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. Walking 1s When the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. AR0132AT/D Rev. 9, 2/16 EN 35 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status registers within the AR0132AT. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW—the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0132AT uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. AR0132AT/D Rev. 9, 2/16 EN 36 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0132AT are 0x20(write address) and0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. AR0132AT/D Rev. 9, 2/16 EN 37 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 24) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 24 shows how the internal register address maintained by the AR0132AT is loaded and incremented as the sequence proceeds. Figure 24: Single READ from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P slave to master master to slave Single READ from Current Location This sequence (Figure 25) performs a read using the current value of the AR0132AT internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 25: Single READ from Current Location Previous Reg Address, N S Slave Address 1 A Reg Address, N+1 Read Data A P S Slave Address N+2 1 A Read Data A P Sequential READ, Start from Random Location This sequence (Figure 26) starts in the same way as the single READ from random location (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 26: Sequential READ, Start from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data AR0132AT/D Rev. 9, 2/16 EN M+2 A A Reg Address, M Reg Address[7:0] A Sr M+3 Read Data A 38 Slave Address M+L-2 Read Data 1 A M+L-1 A Read Data M+1 Read Data A M+L A P ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Current Location This sequence (Figure 27) starts in the same way as the single READ from current location (Figure 25). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 27: Sequential READ, Start from Current Location Previous Reg Address, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A N+L-1 Read Data A Read Data N+L A P Single WRITE to Random Location This sequence (Figure 28) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 28: Single WRITE to Random Location Previous Reg Address, N S 0 A Reg Address[15:8] Slave Address A Reg Address, M Reg Address[7:0] Write Data A M+1 A P A Sequential WRITE, Start at Random Location This sequence (Figure 29) starts in the same way as the single WRITE to random location (Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 29: Sequential WRITE, Start at Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Write Data AR0132AT/D Rev. 9, 2/16 EN M+2 A A Reg Address, M Reg Address[7:0] M+3 Write Data 39 A A Write Data M+L-2 Write Data M+1 A M+L-1 A Write Data M+L A P A ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 30: Quantum Efficiency – Color Sensor 70 Quantum Efficiency (%) 60 red green blue 50 40 30 20 10 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 Wavelength (nm) AR0132AT/D Rev. 9, 2/16 EN 40 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Spectral Characteristics Figure 31: Quantum Efficiency – Monochrome Sensor AR0132AT/D Rev. 9, 2/16 EN 41 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Electrical Specifications Unless otherwise stated, the following specifications apply to the following conditions: VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V; VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +70°C; output load = 10pF; frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 32 and Table 11. Figure 32: Two-Wire Serial Bus Timing Parameters SDATA tLOW tf tSU;DAT tr tf tHD;STA tr tBUF SCLK S tHD;STA tHD;DAT Note: AR0132AT/D Rev. 9, 2/16 EN tHIGH tSU;STA Sr tSU;STO P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. 42 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 11: Two-Wire Serial Bus Characteristics fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; TA = 25°C Standard-Mode Parameter SCLK Clock Frequency SCLK High Symbol Min Max Min Max Unit fSCL 0 8*EXTCLK+ SCLK rise time 6*EXTCLK+ SCLK rise time 100 0 8*EXTCLK+ EXTCLK rise time 6*EXTCLK+ SCLK rise time 400 KHz s 4.0 - 0.6 - s 4.7 4.0 4.7 - 1.3 0.6 0.6 - s s s 04 250 - 3.455 1000 06 1006 20 + 0.1Cb7 0.95 300 s ns ns - 300 20 + 0.1Cb7 300 ns 4.0 4.7 - 0.6 1.3 - s s 1.5 400 3.3 30 4.7 1.5 400 3.3 30 4.7 pF pF pF K SCLK Low Hold time (repeated) START condition t HD;STA After this period, the first clock pulse is generated t LOW LOW period of the SCLK clock tHIGH HIGH period of the SCLK clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time: tSU;DAT Data set-up time tr Rise time of both SDATA and SCLK signals tf Fall time of both SDATA and SCLK signals tSU;STO Set-up time for STOP condition tBUF Bus free time between a STOP and START condition Capacitive load for each bus line Cb Serial interface input pin capacitance CIN_SI CLOAD_SD SDATA max load capacitance RSD SDATA pull-up resistor Notes: AR0132AT/D Rev. 9, 2/16 EN Fast-Mode s This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tR max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. 1. 2. 3. 4. 43 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications I/O Timing By default, the AR0132AT launches pixel data, FV, and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of PIXCLK. This can be changed using register R0x3028. See Figure 33 and Table 12 for I/O timing (AC) characteristics. Figure 33: I/O Timing Diagram tR t RP tF t FP 90% 90% 10% 10% t EXTCLK EXTCLK PIXCLK t PD Data[11:0] Pxl _0 LINE_VALID/ FRAME_VALID Table 12: Pxl _1 Pxl _2 Pxl _n t PLH t PFL t PFH t PLL FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. I/O Timing Characteristics (2.8V VDD_IO)1 Conditions: fPIXCLK = 74.25 MHz (720P 60fps) VDD_IO = 2.8V; Slew rate setting = 6 for PIXCLK; Slew rate setting = 7 for parallel ports Symbol Definition fEXTCLK tEXTCLK tR tF tJITTER tCP Input clock frequency Input clock period Input clock rise time Input clock fall time Input clock jitter EXTCLK to PIXCLK propagation delay tRP tFP fPIXCLK tPD Pixclk rise time Pixclk fall time Pixclk duty cycle PIXCLK frequency2 PIXCLK to data valid tPFH PIXCLK to FV HIGH tPLH PIXCLK to LV HIGH tPFL PIXCLK to FV LOW tPLL PIXCLK to LV LOW AR0132AT/D Rev. 9, 2/16 EN Condition Nominal voltages, PLL Disabled, PCLK slew rate=4 PCLK slew rate = 6 PCLK slew rate = 6 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 44 Min Typ Max Unit 6 20 – – – 5.5 – – 3 3 – – 50 166 – – 600 13.7 MHz ns ns ns ps ns 1.2 1.2 45 6 –2 – – 50 – – 2.9 2.9 55 74.25 2.5 ns ns % MHz ns –2 – 2.5 ns –2 – 2.5 ns –2 – 2.5 ns –2 – 2.5 ns ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Notes: Table 13: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C at 2.5V, and -40°C at 3.1V. All values are taken at the 50% transition point. The loading used is 10pF. 2. Jitter from PIXCLK is already taken into account as the data of all the output parameters. 3. Input clock pad delay is not included in the total delay numbers for tCP. I/O Timing Characteristics (1.8V VDD_IO)1 Conditions: fPIXCLK = 74.25 MHz (720P 60fps) VDD_IO = 1.8V; Slew rate setting = 6 for PIXCLK; Slew rate setting = 7 for parallel ports Symbol Definition fEXTCLK tEXTCLK tR tF tJITTER tCP Input clock frequency Input clock period Input clock rise time Input clock fall time Input clock jitter EXTCLK to PIXCLK propagation delay Pixel rise time Pixel fall time Pixel duty cycle PIXCLK frequency2 PIXCLK to data valid tRP tFP fPIXCLK tPD Condition tPFH PIXCLK to FV HIGH tPLH PIXCLK to LV HIGH tPFL PIXCLK to FV LOW tPLL PIXCLK to LV LOW Notes: PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 PCLK slew rate = 6, Parallel slew rate = 7 Typ Max Unit 6 20 – 6.2 3 3 – – 50 166 600 15.3 MHz ns ns ns ps ns 1.8 1.7 45 6 –2.5 50 – 4.8 4.5 55 74.25 2 ns ns % MHz ns –2.5 – 2 ns –2.5 – 2 ns –2.5 – 2 ns –2.5 – 2 ns 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C TA at 1.7V, and -40°C TA at 1.95V. All values are taken at the 50% transition point. The loading used is 10pF. 2. Jitter from PIXCLK is already taken into account as the data of all the output parameters. 3. Input clock pad delay is not included in the total delay numbers for tCP. I/O Rise Slew Rate (2.8V VDD_IO)1 Table 14: AR0132AT/D Rev. 9, 2/16 EN Nominal voltages, PLL Disabled, PCLK slew rate=4 PCLK slew rate = 6 PCLK slew rate = 6 Min Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.08 0.77 0.58 0.44 0.32 0.23 0.16 0.10 1.77 1.26 0.95 0.70 0.51 0.37 0.25 0.15 2.72 1.94 1.46 1.08 0.78 0.56 0.38 0.22 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns 45 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C TA at 2.5V, and -40°C TA at 3.1V. The loading used is 20pF. I/O Fall Slew Rate (2.8V VDD_IO)1 Table 15: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.00 0.76 0.60 0.46 0.35 0.25 0.17 0.11 1.62 1.24 0.98 0.75 0.56 0.40 0.27 0.16 2.41 1.88 1.50 1.16 0.86 0.61 0.41 0.24 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C TA at 2.5V, and -40°C TA at 3.1V. The loading used is 20pF. I/O Rise Slew Rate (1.8V VDD_IO)1 Table 16: Parallel Slew Rate (R0x306E[15:13]) Conditions 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default Notes: Typ Max Units 0.41 0.30 0.24 0.19 0.14 0.10 0.07 0.04 0.65 0.47 0.37 0.28 0.21 0.15 0.10 0.06 1.10 0.79 0.61 0.46 0.34 0.24 0.16 0.10 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C TA at 1.7V, and -40°C TA at 1.95V. The loading used is 20pF. I/O Fall Slew Rate (1.8V VDD_IO)1 Table 17: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 0.42 0.32 0.26 0.20 0.16 0.12 0.08 0.05 0.68 0.51 0.41 0.32 0.24 0.18 0.12 0.07 1.11 0.84 0.67 0.52 0.39 0.28 0.19 0.11 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Notes: AR0132AT/D Rev. 9, 2/16 EN Min 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 105°C TA at 1.7V, and -40°C TA at 1.95V. The loading used is 20pF. 46 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in the tables below. Table 18: DC Electrical Characteristics Symbol Definition VDD VDD_IO VAA VAA_PIX VDD_PLL VDD_SLVS VDD_SLVS Core digital voltage I/O digital voltage Analog voltage Pixel supply voltage PLL supply voltage HiSPi supply voltage for SLVS mode HiSPi supply voltage for HiVCM mode Input HIGH voltage Input LOW voltage Input leakage current No pull-up resistor; VIN = VDD_IO or DGND Output HIGH voltage Output LOW voltage Output HIGH current At specified VOH Output LOW current At specified VOL VIH VIL IIN VOH VOL IOH IOL Condition Note: Caution Table 19: Min Typ Max Unit 1.7 1.7/2.5 2.5 2.5 2.5 0.3 1.7 1.8 1.8/2.8 2.8 2.8 2.8 0.4 1.8 1.95 1.9/3.1 3.1 3.1 3.1 0.6 1.95 V V V V V V V VDD_IO*0.7 – – – – – – VDD_IO*0.3 20 V V A VDD_IO-0.3 – -22 – – – – – – 0.4 – 22 V V mA mA TA = -40 °C to 105 °C Stresses greater than those listed in Table 19 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Parameter VSUPPLY ISUPPLY IGND VIN VOUT TSTG1 Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature Notes: AR0132AT/D Rev. 9, 2/16 EN Minimum Maximum Unit Symbol –0.3 – – –0.3 –0.3 –40 4.3 200 200 VDD_IO + 0.3 VDD_IO + 0.3 +150 V mA mA V V °C VSUPPLY ISUPPLY IGND VIN VOUT TSTG1 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. To keep dark current and shot noise artifacts from impacting image quality, keep operating temperature at a minimum. 3. TA = -40 °C to 105 °C 47 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 20: Operating Current Consumption in Parallel Output and Linear Mode Definition Condition Symbol Min Typ Max Unit Digital operating current Streaming, 1280x960 45fps IDD1 – 63 90 mA I/O digital operating current Streaming, 1280x960 45fps IDD_IO – 35 40 mA Analog operating current Streaming, 1280x960 45fps IAA – 30 45 mA Pixel supply current Streaming, 1280x960 45fps IAA_PIX – 10 15 mA PLL supply current Streaming, 1280x960 45fps IDD_PLL – 7 15 mA Digital operating current Streaming, 720p 60 fps IDD1 – 63 90 mA I/O digital operating current Streaming, 720p 60 fps IDD_IO – 35 40 mA Analog operating current Streaming, 720p 60 fps IAA – 30 45 mA Pixel supply current Streaming, 720p 60 fps IAA_PIX – 10 15 mA PLL supply current Streaming, 720p 60f ps IDD_PLL – 7 15 mA Notes: Table 21: 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD =1.8V PLL Enabled and PIXCLK = 74.25 MHz TA = 25°C CLOAD = 10pF Measured in dark Operating Current Consumption in Parallel Output and HDR Mode Definition Condition Symbol Min Typ Max Unit Digital operating current Streaming, 1280x960 45fps IDD – 95 115 mA I/O digital operating current Streaming, 1280x960 45fps IDD_IO – 35 40 mA Analog operating current Streaming, 1280x960 45fps IAA – 65 75 mA Pixel supply current Streaming, 1280x960 45fps IAA_PIX – 15 20 mA PLL supply current Streaming, 1280x960 45fps IDD_PLL – 7 15 mA Digital operating current Streaming, 720p 60 fps IDD – 95 115 mA I/O digital operating current Streaming, 720p 60 fps IDD_IO – 35 40 mA Analog operating current Streaming, 720p 60 fps IAA – 61 75 mA Pixel supply current Streaming, 720p 60 fps IAA_PIX – 15 20 mA PLL supply current Streaming, 720p 60 fps IDD_PLL – 7 15 mA Notes: AR0132AT/D Rev. 9, 2/16 EN 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD = 1.8V PLL Enabled and PIXCLK = 74.25 MHz TA= 25°C CLOAD = 10pF Measured in dark 48 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 22: Operating Currents in HiSPi Output and Linear Mode Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming 1280x960 45fps IDD – 95 115 mA I/O digital operating current Streaming 1280x960 45fps IDD_IO – 100 150 A Analog operating current Streaming 1280x960 45fps IAA – 30 45 mA Pixel Supply Current Streaming 1280x960 45fps IAA_PIX – 10 15 mA PLL Supply Current Streaming 1280x960 45fps IDD_PLL – 7 15 mA SLVS Supply Current IDD_SLVS – 8 15 mA – 16 25 mA Digital Operating Current Current LoVCM Mode Streaming 1280x960 45fps Current HiVCM Mode Streaming 1280x960 45fps Streaming 720p 60 fps IDD – 95 115 mA I/O digital operating current Streaming 720p 60 fps IDD_IO – 100 150 A Analog operating current Streaming 720p 60 fps IAA – 30 45 mA Pixel Supply Current Streaming 720p 60 fps IAA_PIX – 10 15 mA PLL Supply Current Streaming 720p 60 fps IDD_PLL – 7 15 mA SLVS Supply Current Current LoVCM Mode Streaming 720p 60 fps Current HiVCM Mode Streaming 1280x960 60fps IDD_SLVS – 8 15 mA – 16 25 mA Notes: AR0132AT/D Rev. 9, 2/16 EN 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD = 1.8V VDD_SLVS = 0.4V (LoVCM) VDD_SLVS = 1.8V (HiVCM) PLL Enabled and PIXCLK = 74.25 MHz TA = 25°C CLOAD = 10pF Measured in dark 49 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 23: Operating Current in HiSPi Output and HDR Mode Definition Condition Digital Operating Current I/O digital operating current Analog operating current Pixel Supply Current PLL Supply Current SLVS Supply Current Streaming 1280x960 45 fps Streaming 1280x960 45 fps Streaming 1280x960 45 fps Streaming 1280x960 45 fps Streaming 1280x960 45 fps Current LoVCM Mode Streaming 1280x960 45 fps Current HiVCM Mode Streaming 1280x960 45 fps Streaming 720p 60 fps Streaming 720p 60 fps Streaming 720p 60 fps Streaming 720p 60 fps Streaming 720p 60 fps Current LoVCM Mode Streaming 720p 60 fps Current HiVCM Mode Streaming 1280x960 60fps Digital Operating Current I/O digital operating current Analog operating current Pixel Supply Current PLL Supply Current SLVS Supply Current Notes: Table 24: Symbol Min Typ Max Unit IDD IDD_IO IAA IAA_PIX IDD_PLL IDD_SLVS – – – – – – 115 100 65 15 7 8 130 150 75 20 15 15 mA A mA mA mA mA – 16 25 mA – – – – – – 115 100 65 15 7 8 130 150 75 20 15 15 mA A mA mA mA mA – 16 25 mA IDD IDD_IO IAA IAA_PIX IDD_PLL IDD_SLVS 1. Operating currents are measured at the following conditions: VAA=VAA_PIX=VDD_IO=VDD_PLL=2.8V VDD=1.8V VDD_SLVS = 0.4V (LoVCM) VDD_SLVS = 1.8V (HiVCM) PLL Enabled and PIXCLK=74.25MHz TA = 25°C CLOAD = 10pF Measured in dark Standby Current Consumption Definition Condition Hard standby (clock off) Hard standby (clock on) Soft standby (clock off) Soft standby (clock on) Notes: AR0132AT/D Rev. 9, 2/16 EN Symbol Min Typ Max Unit Analog, 2.8V – – 30 100 ìA Digital, 1.8V – – 85 2500 ìA Analog, 2.8V – – 30 100 ìA Digital, 1.8V – – 1.55 4 mA Analog, 2.8V – – 85 100 ìA Digital, 1.8V – – 85 2500 ìA Analog, 2.8V – – 30 100 ìA Digital, 1.8V – – 1.55 4 mA 1. Analog – VAA + VAA_PIX + VDD_PLL 2. Digital – VDD + VDD_IO + VDD_SLVS 50 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Figure 34: Power Supply Rejection Ratio 70 60 PSRR (dB) 50 40 30 20 10 0 1000 10000 100000 1000000 Frequency (Hz) HiSPi Electrical Specifications The ON Semiconductor AR0132AT sensor supports both SLVS and HiVCM HiSPi modes. Please refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the AR0132AT is shown in Figure 35. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 0–10s, turn on VAA and VAA_PIX power supply. 3. After 0–10s, turn on VDD_IO power supply. 4. After the last power supply is stable, enable EXTCLK. 5. Assert RESET_BAR for at least 1ms. 6. Wait 850000 EXTCLKs (for internal initialization into software standby). 7. Configure PLL, output, and image settings to desired values. 8. Wait 1ms for the PLL to lock. 9. Set streaming mode (R0x301A[2] = 1). AR0132AT/D Rev. 9, 2/16 EN 51 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Figure 35: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) t0 t1 VDD_IO (1.8/2.8) t2 VDD (1.8) t3 VDD_SLVS (0.4) EXTCLK t4 RESET_BAR Table 25: tx t5 t6 Hard Reset Internal Initialization Software Standby Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX3 VAA/VAA_PIX to VDD_IO VDD_IO to VDD VDD to VDD_SLVS Xtal settle time Hard Reset Internal Initialization PLL Lock Time t0 t1 t2 t3 tx t4 t5 t6 0 0 0 0 – 12 850000 1 10 10 10 10 301 – – – – – – – – – – – s s s s ms ms EXTCLKs ms PLL Lock Streaming Power-Up Sequence Notes: AR0132AT/D Rev. 9, 2/16 EN 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then the sensor may have functionality issues and will experience high current draw on this supply. 4. TA = -40 °C to 105 °C 52 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Power-Down Sequence The recommended power-down sequence for the AR0132AT is shown in Figure 36. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. Power may be removed from all supplies simultaneously, and a sudden loss of power on all rails does not cause damage or affect the lifetime of the device. 1. Disable streaming if output is active by setting standby R0x301A[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 36: Power Down VDD_SLVS (0.4) t0 VDD (1.8) t1 V DD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Table 26: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD VDD to VDD_IO VDD_IO to VAA/VAA_PIX VAA/VAA_PIX to VDD_PLL PwrDn until Next PwrUp Time t0 t1 t2 t3 t4 0 0 0 0 100 – – – – – – – – – – s s s s ms Notes: AR0132AT/D Rev. 9, 2/16 EN 1. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. 2. TA = -40 °C to 105 °C 53 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Package Dimensions (Case 503AF) Package Dimensions (Case 503AF) IBGA63 9x9 CASE 503AF ISSUE O DATE 30 DEC 2014 AR0132AT/D Rev. 9, 2/16 EN 54 ©Semiconductor Components Industries, LLC, 2016. AR0132AT: 1/3-Inch CMOS Digital Image Sensor Package Dimensions (Case 503AF) ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. AR0132AT/D Rev. 9, 2/16 EN 55 ©Semiconductor Components Industries, LLC, 2016 .