AX8052F100-2-TW30

AX8052F100 Ultra-Low Power Microcontroller OVERVIEW The AX8052F100 is a single chip ultra−lowpower microcontroller primarily for use in radio applications. The AX8052F100 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal SRAM. The AX8052F100 features 3 16−bit general purpose timers with SD capability, 2 output compare units for generating PWM signals, 2 input compare units to record timings of external signals, 2 16−bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a 10−bit 500 kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware debug interface controller that connects using a 3−wire protocol (1 dedicated wire, 2 shared with GPIO) to the PC hosting the debug software. Features ORDERING INFORMATION Device AX8052F100−2−TA05 AX8052F100−3−TA05 AX8052F100−3−TW30 Package Shipping† QFN28 (Pb−Free) 500 / Tape & Reel QFN28 3,000 / (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. • DebugLink Interface allows “printf” Style Debugging without utilizing a UART or GPIO Pins Memory • 64 kByte FLASH AX8052 Core • Industry Standard 8052 Instruction Set • High Performance Core, most Instructions Require only 1 Clock per Instruction Byte • 20 MIPS • Dual DPTR for High Speed Memory Chips • 22 Interrupt Vectors • • 100,000 Erase Cycles 10 Year Data Retention 8.25 kByte RAM High Performance Memory Crossbar Clocking • Four Clock Sources ♦ On−chip 20 MHz RC−oscillator 10 kHz/640 Hz Ultra−low−power RC−oscillator ♦ Fast Crystal Oscillator ♦ Low Power Tuning Fork Crystal Oscillator Fully Automatic Calibration of On−chip RC Oscillators to a Reference Clock Clock Monitor can Detect Failures of the Main Clock and Switch to the On−chip Fast RC Oscillator Watchdog ♦ Debugger • Three−wire (1 dedicated, 2 shared with GPIO Pins) Debugger Interface • True Hardware Debugger with Breakpoints and Single Stepping Support • User Programmable 64−bit Key to restrict Debugging to Authorized Personnel May, 2018 − Rev. 5 1 28 QFN28 5x5, 0.5P CASE 485EH AX8052F100−2−TW30 Ultra−low Power Microcontroller • QFN28 Package • Supply Range 1.8 V − 3.6 V • −40°C to 85°C • Ultra−low Power Consumption: ♦ CPU Active Mode 150 mA/MHz ♦ Sleep Mode with 256 Byte RAM Retention and Wake−up Timer running 850 nA ♦ Sleep Mode 4 kByte RAM Retention and Wake−up Timer running 1.5 mA ♦ Sleep Mode 8 kByte RAM Retention and Wake−up Timer running 2.2 mA © Semiconductor Components Industries, LLC, 2016 www.onsemi.com • • • 1 Publication Order Number: AX8052F100/D AX8052F100 ADC • 10−bit 500 kSamples/s ADC • Up to 8 Channels • Single Ended and Differential Sampling • x0.1, x1 and x10 Gain Amplifier • Internal 1 V Reference • Flexibly Programmable Conversion Schedule • Built−in Temperature Sensor Power Modes • Standby, Sleep and Deep Sleep Power Modes for Very Low Idle Power Consumption • On−chip Power−on−Reset and Brown−out Detection • Unrestricted Operation from 1.8 V − 3.6 V VDD_IO 16−bit Wakeup Timer • Two Counting Registers • Four Event Registers Allow Flexible Wakeup and Software Schedules Analog Comparators • Internal and External Reference • Output Signal may be Routed to GPIO, Read by Software, or Used as Input Capture Trigger GPIO • 24 GPIO Pins • PB0−PB7, PC0−PC3 and PR0−PR5 5 V Tolerant Inputs • All GPIO Pins Support Individually Programmable • DMA Controller • 2 Independent DMA Channels • Moves Data between X−RAM and most On−chip Pull−ups and Interrupt on Change Flexible Allocation of GPIO Pins to Peripherals Peripherals • Cycle−steal and Round−robin Memory Arbitration 16−bit General Purpose Timer (3x) • Saw Tooth and Triangle Modes • Sigma−Delta Mode Converts Timer into a DAC • Optional Double Buffering of the PERIOD Register • • • ensure Minimal Impact on AX8052 Core • Chained Buffer Descriptors allow Arbitrarily Elaborate Buffering Schemes and Flexible Interrupt Generation allows Controlled Frequency Changes Optional High−byte Buffering allows Atomic 16−bit Accesses Flexible Clocking Options, can use any Internal or an External Clock Source Pre−scaler Included AES • Dedicated AES Crypto Controller • Dedicated DMA Engine to fetch Input Data and Key • • 16−bit Output Compare Unit (2x) • Used together with a General Purpose Timer to create • • PWM Waveforms Optional Double Buffering • 16−bit Input Capture Unit (2x) • Used together with a General Purpose Timer to time Events on an External or Internal Signal Stream from X−RAM and Strobe Output Data into X−RAM Multi Megabit/s Data Rates Supports AES−128, AES−192 and AES−256 International Standards Programmable Round Number and Software Key Schedule Generation allow Longer Key Lengths for Higher Security Applications ECB, CFB and OFB Chaining Modes NOTE: The AES engine requires software enabling and support. True Random Number Generator (RNG) • Cryptographic Random Numbers UART (2x) • 5−9 bit Word Length, 1−2 Stop Bits • Uses One of the General Purpose Timers as Baud Rate Generator NOTE: The random number generator requires software enabling and support. Applications • Ultra−low Power Microcontroller Applications, Dedicated Radio Master SPI Interface • Compatible to AX RF and other Peripherals • Efficient CPU Access • Easy Access to Transceiver Registers by Mapping • • • • • • • Transceiver Registers into X Address Space Transceiver Crystal may clock MCU Master/Slave SPI • Supports 3 and 4 Wire Variants especially in Conjunction with AXRadio IC Sensor Applications Home Automation Automatic Meter Reading Remote Keyless Entry Active RFID Wireless Audio www.onsemi.com 2 AX8052F100 BLOCK DIAGRAM DMA Controller Timer Counter 0 8k Timer Counter 2 AX8052 Debug Interface Output Comp 0 System Controller Output Comp 1 Reset, Clocks, Power Input Capt 0 AES Crypto Engine Input Capt 1 ADC Comparators Temp Sensor UART 0 SFR-Bus SPI M/S POR PA0 PA1 PA2 PA3 PA4 PA5 Timer Counter 1 I-Bus 256 X-Bus RESET_N GND VDD_IO GPIO P-Bus DBG_EN FLASH 64k RAM IRQ Req PR0 PR1 PR2 PR3 PR4 PR5 DMA Req AX8052F100 UART 1 I/O Multiplexer Figure 1. Functional Block Diagram of the AX8052F100 www.onsemi.com 3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 AX8052F100 Table 1. PIN FUNCTION DESCRIPTIONS Pin(s) Type PR5 Symbol 1 I/O/PU Description VDD_CORE 2 P PR4 3 I/O/PU General Purpose I/O PR3 4 I/O/PU General Purpose I/O PR2 5 I/O/PU General Purpose I/O PR0 6 I/O/PU General Purpose I/O PR1 7 I/O/PU General Purpose I/O PC3 8 I/O/PU General Purpose I/O PC2 9 I/O/PU General Purpose I/O PC1 10 I/O/PU General Purpose I/O PC0 11 I/O/PU General Purpose I/O PB0 12 I/O/PU General Purpose I/O PB1 13 I/O/PU General Purpose I/O PB2 14 I/O/PU General Purpose I/O PB3 15 I/O/PU General Purpose I/O PB4 16 I/O/PU General Purpose I/O PB5 17 I/O/PU General Purpose I/O PB6, DBG_DATA 18 I/O/PU General Purpose I/O, debugger data line PB7, DBG_CLK 19 I/O/PU General Purpose I/O, debugger clock line DBG_EN 20 I/PD In−Circuit Debugger Enable RESET_N 21 I/PU Optional reset pin. If this pin is not used it must be connected to VDD_IO VDD_IO 22 P PA0 23 I/O/PU General Purpose I/O PA1 24 I/O/PU General Purpose I/O PA2 25 I/O/PU General Purpose I/O PA3 26 I/O/PU General Purpose I/O PA4 27 I/O/PU General Purpose I/O PA5 28 I/O/PU General Purpose I/O GND Center pad P General Purpose I/O Regulated output voltage Unregulated power supply Ground on center pad of QFN, must be connected All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible. Port A Pins (PA0 − PA7) must not be driven above VDD_IO, all other digital inputs are 5 V tolerant. Pull−ups are programmable for all GPIO pins. A = analog input I = digital input signal O = digital output signal PU = pull−up I/O = digital input/output signal N = not to be connected P = power or ground PD = pull−down www.onsemi.com 4 AX8052F100 Alternate Pin Functions GPIO Pins are shared with dedicated Input/Output signals of on−chip peripherals. The following table lists the available functions on each GPIO pin. Table 2. ALTERNATE PIN FUNCTIONS GPIO Alternate Functions PA0 T0OUT IC1 ADC0 XTALP PA1 T0CLK OC1 ADC1 XTALN PA2 OC0 U1RX ADC2 COMPI00 PA3 T1OUT ADC3 LPXTALP PA4 T1CLK COMPO0 ADC4 LPXTALN PA5 IC0 U1TX ADC5 COMPI10 EXTIRQ0 PB0 U1TX IC1 PB1 U1RX OC1 PB2 IC0 T2OUT PB3 OC0 T2CLK PB4 U0TX T1CLK PB5 U0RX T1OUT PB6 DBG_DATA PB7 DBG_CLK PC0 SSEL T0OUT EXTIRQ0 PC1 SSCK T0CLK COMPO1 PC2 SMOSI U0TX PC3 SMISO U0RX PR0 RSEL PR1 RSYSCLK PR2 RCLK PR3 RMISO PR4 RMOSI PR5 RIRQ www.onsemi.com 5 EXTIRQ1 COMPO0 DSWAKE AX8052F100 28 VDD_IO PA0/ADC0/T0OUT/IC1/XTALN PA1/ADC1/T0CLK/OC1/XTALP PA2/ADC2/OC0/U1RX/COMPI00 PA3/ADC3/T1OUT/LPXTALP PA4/ADC4/T1CLK/COMPO0/LPXTALN PA5/ADC5/IC0/U1TX/COMPI10 Pinout Drawing 27 26 25 24 23 22 21 RESET_N RIRQ/PR5 1 VDD_CORE 2 20 DBG_EN RMOSI/PR4 3 19 PB7/DBG_CLK AX8052F100 RMISO/PR3 4 18 PB6/DBG_DATA RCLK/PR2 5 17 PB5/U0RX/T1OUT RSEL/PR0 6 16 PB4/U0TX/T1CLK RSYSCLK/PR1 7 9 10 11 12 13 14 U0TX/SMOSI/PC2 COMPO1/T0CLK/SSCK/PC1 EXTIRQ0/T0OUT/SSEL/PC0 EXTIRQ0/IC1/U1TX/PB0 T2OUT/IC0/PB2 OC1/U1RX/PB1 8 COMPO0/U0RX/SMISO/PC3 15 PB3/OC0/T2CLK/EXTIRQ1/DSWAKE Figure 2. Pinout Drawing (Top View) www.onsemi.com 6 AX8052F100 SPECIFICATIONS Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Description Condition Min Max Units −0.5 5.5 V 100 mA 800 mW 10 mA −100 100 mA 40 mA −0.5 5.5 V −2000 2000 V −40 85 °C −65 150 °C 150 °C VDD_IO Supply voltage IDD Supply current Ptot Total power consumption II1 DC current into any pin −10 II2 DC current into pins IO Output Current Via Input voltage digital pins Ves Electrostatic handling Tamb Operating temperature Tstg Storage temperature Tj Junction Temperature HBM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Table 4. SUPPLIES Symbol Description Condition Min Typ Max Units TAMB Operational ambient temperature −40 27 85 °C VDD_IO I/O and voltage regulator supply voltage 1.8 3.0 3.6 V VDDIO_R1 I/O voltage ramp for reset activation; Note 1, starting with AX8052F100−3 this limitation to the VDD_IO ramp for reset activation is no longer necessary. Ramp starts at VDD_IO ≤ 0.1 V 0.1 V/ms VDDIO_R2 I/O voltage ramp for reset activation; Note 1, starting with AX8052F100−3 this limitation to the VDD_IO ramp for reset activation is no longer necessary. Ramp starts at 0.1V < VDD_IO < 0.7 V 3.3 V/ms VBOUT Brown−out Threshold Note 2 1.3 V IDEEPSLEEP Deep Sleep current 50 nA ISLEEP256PIN Sleep current, 256 Bytes RAM retained Wakeup from dedicated pin 450 nA ISLEEP256 Sleep current, 256 Bytes RAM retained Wakeup Timer running at 640 Hz 850 nA ISLEEP4K Sleep current, 4.25 kBytes RAM retained Wakeup Timer running at 640 Hz 1.5 mA ISLEEP8K Sleep current, 8.25 kBytes RAM retained Wakeup Timer running at 640 Hz 2.2 mA IMCU Micro−controller Running Power consumption All peripherals disabled 150 mA/ MHz IVSUP Voltage Supervisor Run and Standby mode 85 mA IXTALOSC Crystal oscillator current 20 MHz 160 mA ILFXTALOSC Low Frequency Crystal Oscillator current 32 kHz 700 nA IRCOSC Internal Oscillator current 20 MHz 210 mA ILPOSC Internal Low Power Oscillator current 10 kHz 650 nA 640 Hz 210 nA 311 kSample/s, DMA 5 MHz 1.1 mA IADC ADC current 1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended for AX8052F100−1 and AX8052F100−2, see the AX8052 Application Note: Power On Reset 2. Digital circuitry is functional down to typically 1 V. www.onsemi.com 7 AX8052F100 Table 5. LOGIC Symbol Description Condition Min Typ Max Units Digital Inputs VDD_IO = 3.3 V VT+ Schmitt trigger low to high threshold point 1.55 V VT− Schmitt trigger high to low threshold point 1.25 V VIL Input voltage, low VIH Input voltage, high 2.0 VIPA Input voltage range, Port A −0.5 VDD_IO V VIPBC Input voltage range, Ports B, C −0.5 5.5 V IL Input leakage current −10 10 mA RPU Programmable Pull−Up Resistance 0.8 V V 65 kW Digital Outputs IOH P[ABC]x Output Current, high VOH = 2.4 V 8 mA IOL IPROH P[ABC]x Output Current, low VOL = 0.4 V 8 mA PRx Output Current, high VOH = 2.4 V 2 mA IPROL PRx Output Current, low VOL = 0.4 V 2 mA IOZ Tri−state output leakage current −10 10 mA AC Characteristics Table 6. CRYSTAL OSCILLATOR Symbol Description fXTAL Crystal frequency gmxosc Transconductance oscillator Note 1 RINxosc Condition Min Typ 8 XTALOSCGM = 0001 0.5 XTALOSCGM = 0010 1.0 XTALOSCGM = 1110 4.5 XTALOSCGM = 1111 11.0 Input DC impedance Max Units 20 MHz mS 10 kW 1. During normal operation the oscillator transconductance is automatically adjusted for lowest power consumption Table 7. LOW FREQUENCY CRYSTAL OSCILLATOR Symbol Description fLPXTAL Crystal frequency gmlpxosc Transconductance oscillator Condition Min Max Units 32 150 kHz LPXOSCGM = 00110 3.5 LPXOSCGM = 01000 4.6 LPXOSCGM = 01100 6.9 LPXOSCGM = 10000 RINlpxosc Typ Input DC impedance 9.1 10 www.onsemi.com 8 ms MW AX8052F100 Table 8. INTERNAL LOW POWER OSCILLATOR Symbol fLPOSC Description Condition Oscillation Frequency Min Typ Max Units LPOSCFAST = 0 Factory calibration applied. Over the full temperature and voltage range 630 640 650 Hz LPOSCFAST = 1 Factory calibration applied. Over the full temperature and voltage range 10.08 10.24 10.39 kHz Min Typ Max Units 19.8 20 20.2 MHz Table 9. INTERNAL RC OSCILLATOR Symbol Description fLFRPCOSC Oscillation Frequency Condition Factory calibration applied. Over the full temperature and voltage range Table 10. MICROCONTROLLER Symbol Description Condition Min Typ Max Units TSYSCLKL SYSCLK Low 27 ns TSYSCLKH SYSCLK High 21 ns TSYSCLKP SYSCLK Period 47 ns TFLWR FLASH Write Time 2 Bytes 20 ms TFLPE FLASH Page Erase 1 kBytes 2 ms TFLE FLASH Secure Erase 64 kBytes 10 ms TFLEND FLASH Endurance: Erase Cycles 100 000 Cycles TFLRETroom FLASH Data Retention TFLREThot 10 000 25°C See Figure 3 for the lower limit set by the memory qualification 100 85°C See Figure 3 for the lower limit set by the memory qualification 10 Years Data retention time [years] 100000 10000 1000 100 10 15 25 35 45 55 Temperature [5C] 65 75 85 Figure 3. FLASH Memory Qualification Limit for Data Retention after 10k Erase Cycles www.onsemi.com 9 AX8052F100 Table 11. ADC / COMPARATOR / TEMPERATURE SENSOR Symbol Description Condition Min ADCSR ADC sampling rate GPADC mode 30 ADCSR_T ADC sampling rate temperature sensor mode 10 ADCRES ADC resolution VADCREF ADC reference voltage & comparator internal reference voltage ZADC00 Input capacitance DNL Differential nonlinearity INL Integral nonlinearity OFF Offset GAIN_ERR Gain error Typ 15.6 Max Units 500 kHz 30 kHz 10 0.95 1 Bits 1.05 V 2.5 pF ±1 LSB ±1 LSB 3 LSB 0.8 % ADC in Differential Mode VABS_DIFF Absolute voltages & common mode voltage in differential mode at each input VFS_DIFF01 Full swing input for differential signals VFS_DIFF10 0 VDD_IO V Gain x1 −500 500 mV Gain x10 −50 50 mV ADC in Single Ended Mode VMID_SE Mid code input voltage in single ended mode VIN_SE00 Input voltage in single ended mode VFS_SE01 Full swing input for single ended signals VFS_SE10 0.5 V 0 VDD_IO V Gain x1 0 1 V Gain x10 0.45 0.55 V Comparators VCOMP_ABS Comparator absolute input voltage 0 VDD_IO V VCOMP_COM Comparator input common mode 0 VDD_IO − 0.8 V VCOMPOFF Comparator input offset voltage 20 mV 85 °C Temperature Sensor TRNG Temperature range TRES Temperature resolution TERR_CAL Temperature error −40 °C/LSB 0.1607 Factory calibration applied www.onsemi.com 10 −2 2 °C AX8052F100 CIRCUIT DESCRIPTION Memory Architecture The AX8052F100 Microcontroller features the highest bandwidth memory architecture of its class. Figure 4 shows the memory architecture. Three bus masters may initiate bus cycles: • The AX8052 Microcontroller Core • The Direct Memory Access (DMA) Engine • The Advanced Encryption Standard (AES) Engine The AX8052F100 is a single chip ultra−lowpower microcontroller primarily for use in radio applications. The AX8052F100 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal SRAM. The AX8052F100 features 3 16−bit general purpose timers with SD capability, 2 output compare units for generating PWM signals, 2 input compare units to record timings of external signals, 2 16−bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a 10−bit 500 kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware debug interface controller that connects using a 3−wire protocol (1 dedicated wire, 2 shared with GPIO) to the PC hosting the debug software. The system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from one of the following clock sources: the crystal oscillator, an internal high speed 20 MHz oscillator, an internal low speed 640 Hz/10 kHz oscillator, or the low frequency crystal oscillator. Pre−scalers offer additional flexibility with their programmable divide by a power of two capability. To improve the accuracy of the internal oscillators, both oscillators may be slaved to the crystal oscillator. AX8052F100 can be operated from a 1.8 V to 3.6 V power supply over a temperature range of −40°C to 85°C. The AX8052F100 features make it an ideal interface for integration into various battery powered SRD solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. Bus targets include: • Two individual 4 kBytes RAM blocks located in X • • • • address space, which can be simultaneously accessed and individually shut down or retained during sleep mode A 256 Byte RAM located in internal address space, which is always retained during sleep mode A 64 kBytes FLASH memory located in code space. Special Function Registers (SFR) located in internal address space accessible using direct address mode instructions Additional Registers located in X address space (X Registers) The upper half of the FLASH memory may also be accessed through the X address space. This simplifies and makes the software more efficient by reducing the need for generic pointers. NOTE: Generic pointers include, in addition to the address, an address space tag. SFR Registers are also accessible through X address space, enabling indirect access to SFR registers. This allows driver code for multiple identical peripherals (such as UARTs or Timers) to be shared. The 4 word × 16 bit fully associative cache and a pre−fetch controller hide the latency of the FLASH. Microcontroller The AX8052F100 microcontroller core executes the industry standard 8052 instruction set. Unlike the original 8052, many instructions are executed in a single cycle. The system clock and thus the instruction rate can be programmed freely from DC to 20 MHz. www.onsemi.com 11 AX8052F100 Cache AX8052 AES Prefetch DMA X Bus SFR Bus Arbiter Arbiter Arbiter XRAM XRAM X Registers 0000−0FFF 1000−1FFF 4000−7FFF IRAM Bus Arbiter Code Bus Arbiter Arbiter SFR Registers IRAM FLASH 80−FF 00−FF 0000−FFFF Figure 4. AX8052 Memory Architecture The AES engine accesses memory 16 bits at a time. It is therefore slightly faster to align its buffers on even addresses. The AX8052 Memory Architecture is fully parallel. All bus masters may simultaneously access different bus targets during each system clock cycle. Each bus target includes an arbiter that resolves access conflicts. Each arbiter ensures that no bus master can be starved. Both 4 kBytes RAM blocks may be individually retained or switched off during sleep mode. The 256 Byte RAM is always retained during sleep mode. Memory Map The AX8052, like the other industry standard 8052 compatible microcontrollers, uses a Harvard architecture. Multiple address spaces are used to access code and data. Figure 5 shows the AX8052 memory map. I (internal) Space Address P (Code) Space X Space direct access 0000−007F indirect access IRAM IRAM XRAM 0080−00FF SFR 0100−1FFF IRAM 2000−207F 2080−3F7F FLASH 3F80−3FFF SFR 4000−4FFF RREG 5000−5FFF RREG (nb) 6000−7FFF XREG 8000−FBFF FLASH FC00−FFFF Calibration Data Calibration Data Figure 5. AX8052 Memory Map www.onsemi.com 12 AX8052F100 given in the Radio chip’s Programming Manual are relative to the beginning of RREG, i.e. 0x4000 must be added to these addresses. If an AXRadio chip is connected, the appropriate provided ax8052f1xx.h header file should be used. Normally, accessing Radio Registers through the RREG address range is adequate. Since Radio Register accesses have a higher latency than other AX8052 registers, the AX8052 provides a method for non−blocking access to the Radio Registers. Accessing the RREG (nb) address range initiates a Radio Register access, but does not wait for its completion. The details of mechanism is documented in the Radio Interface section of the AX8052 Programming Manual. The FLASH memory is organized as 64 pages of 1 kBytes each. Each page can be individually erased. The write word size is 16 Bits. The last 1 kByte page is dedicated to factory calibration data and should not be overwritten. The AX8052 uses P or Code Space to access its program. Code space may also be read using the MOVC instruction. Smaller amounts of data can be placed in the Internal (see Note) or Data Space. A distinction is made in the upper half of the Data Space between direct accesses (MOV reg,addr; MOV addr,reg) and indirect accesses (MOV reg,@Ri; MOV @Ri,reg; PUSH; POP); Direct accesses are routed to the Special Function Registers, while indirect accesses are routed to the internal RAM. NOTE: The origin of Internal versus External (X) Space is historical. External Space used to be outside of the chip on the original 8052 Microcontrollers. Large amounts of data can be placed in the External or X Space. It can be accessed using the MOVX instructions. Special Function Registers, as well as additional Microcontroller Registers (XREG) and the Radio Registers (RREG) are also mapped into the X Space. Detailed documentation of the Special Function Registers (SFR) and additional Microcontroller Registers can be found in the AX8052 Programming Manual. The Radio Registers are documented in the Programming Manual of the connected Radio chip. Register Addresses Power Management The microcontroller supports the following power modes: Table 12. POWER MANAGEMENT PCON register Name Description 00 RUNNING The microcontroller and all peripherals are running. Current consumption depends on the system clock frequency and the enabled peripherals and their clock frequency. 01 STANDBY The microcontroller is stopped. All register and memory contents are retained. All peripherals continue to function normally. Current consumption is determined by the enabled peripherals. STANDBY is exited when any of the enabled interrupts become active. 10 SLEEP The microcontroller and its peripherals, except GPIO and the system controller, are shut down. Their register settings are lost. The internal RAM is retained. The external RAM is split into two 4 kByte blocks. Software can determine individually for both blocks whether contents of that block are to be retained or lost. SLEEP can be exited by any of the enabled GPIO or system controller interrupts. For most applications this will be a GPIO or wakeup timer interrupt. 11 DEEPSLEEP The microcontroller, all peripherals and the transceiver are shut down. Only 4 bytes of scratch RAM are retained. DEEPSLEEP can only be exited by tying the PB3 pin low. www.onsemi.com 13 AX8052F100 Clocking WDT Wakeup Timer FRCOSC Calib Interrupt LPOSC FRCOSC Glitch Free Clock Switch LPOSC Calib Internal Reset XOSC Prescaler ÷1,2,4,... System Clock Clock Monitor LPXOSC RSYSCLK Figure 6. Clock System Diagram The system clock can be derived from any of the following clock sources: • The crystal oscillator • The low speed crystal oscillator • The internal high speed RC (20 MHz) oscillator • The internal low power (640 Hz/10 kHz) oscillator Both internal oscillators can be slaved to one of the crystal oscillators to increase the accuracy of the oscillation frequency. While the reference oscillator runs, the internal oscillator is slaved to the reference frequency by a digital frequency locked loop. When the reference oscillator is switched off, the internal oscillator continues to run unslaved with the last frequency setting. An additional pre−scaler allows the selected oscillator to be divided by a power of two. After reset, the microcontroller starts with the internal high speed RC oscillator selected and divided by two. I.e. at start−up, the microcontroller runs with 10 MHz ± 10%. Clocks may be switched any time by writing to the CLKCON register. In order to prevent clock glitches, the switching takes approximately 2·(T1+T2), where T1 and T2 are the periods of the old and the new clock. Switching may take longer if the new oscillator first has to start up. Internal oscillators start up instantaneously, but crystal oscillators may take a considerable amount of time to start the oscillation. CLKSTAT can be read to determine the clock switching status. A programmable clock monitor resets the CLKCON register when no system clock transitions are found during a programmable time interval, thus reverts to the internal RC oscillator. Reset and Interrupts After reset, the microcontroller starts executing at address 0x0000. All registers except SCRATCH0...SCRATCH3 are set to default values. RAM is either retained (SLEEP mode) or undefined. Several events can lead to resetting the microcontroller core: • POR or hardware RESET_N pin activated and released • Leaving SLEEP or DEEPSLEEP mode • Watchdog Reset • Software Reset The reset cause can be determined by reading the PCON register. After POR or reset all registers are set to their default values. AX8052F100 has an integrated power−on−reset block which is edge sensitive to VDD_IO. For many common www.onsemi.com 14 AX8052F100 modes, as well as a SD mode that can be used to output an analog value on a dedicated digital pin only employing a simple RC lowpass filter. Two output compare units work in conjunction with one of the timers to generate PWM signals. Two input capture units work in conjunction with one of the timers to measure transitions on an input signal. For software timekeeping, two additional 16−bit wakeup timers with 4 16−bit event registers are provided, generating an interrupt on match events. application cases no external reset circuitry is required. However, if VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended. For detailed recommendations and requirements see the AX8052 Application Note: Power On Reset. The RESET_N pin contains a weak pull−up. However, it is strongly recommended to connect the RESET_N pin to VDD_IO if not used, for additional robustness. The microcontroller supports 22 interrupt sources. Each interrupt can be individually enabled and can be programmed to have one of two possible priorities. The interrupt vectors are located at 0x0003, 0x000B,…, 0x00AB. UART The AX8052F100 features two universal asynchronous receiver transmitters. They use one of the timers as baud rate generator. Word length can be programmed from 5 to 9 bits. Debugging A hardware debug unit considerably eases debugging compared to other 8052 microcontrollers. It allows to reliably stop the micro−controller at breakpoints even if the stack is smashed. The debug unit communicates with the host PC running the debugger using a 3 wire interface. One wire is dedicated (DBG_EN), while two wires are shared with GPIO pins (PB6, PB7). When DBG_EN is driven high, PB6 and PB7 convert to debug interface pins and the GPIO functionality is no longer available. A pin emulation feature however allows bits PINB[7:6] to be set and PORTB[7:6] and DIRB[7:6] to be read by the debugger software. This allows for example switches or LEDs connected to the PB6, PB7 pins to be emulated in the debugger software whenever the debugger is active. In order to protect the intellectual property of the firmware developer, the debug interface can be locked using a developer−selectable 64−bit key. The debug interface is then disabled and can only be enabled with the knowledge of this 64−bit key. Therefore, unauthorized persons cannot read the firmware through the debug interface, but debugging is still possible for authorized persons. Secure erase can be initiated without key knowledge; secure erase ensures that the main FLASH array is completely erased before erasing the key, reverting the chip into factory state. The DebugLink peripheral looks like an UART to the microcontroller, and allows exchange of data between the microcontroller and the host PC without disrupting program execution. Dedicated Radio SPI Master Controller The AX8052F100 features a dedicated Radio master SPI controller. It is compatible with AX RF chips as well as some third party SPI slave devices. It features efficient access by the CPU. RF IC registers are mapped into the CPU X address space. SPI Master/Slave Controller The AX8052F100 features a master/slave SPI controller. Both 3 and 4 wire SPI variants are supported. In master mode, any of the on−chip oscillators or the system clock may be selected as clock source. An additional pre−scaler with divide by two capability provides additional clocking flexibility. Shift direction, as well as clock phase and inversion, are programmable. ADC, Analog Comparators and Temperature Sensor The AX8052F100 features a 10−bit, 500 kSample/s Analog to Digital converter. Figure 7 shows the block diagram of the ADC. The ADC supports both single ended and differential measurements. It uses an internal reference of 1 V. ×1, ×10 and ×0.1 gain modes are provided. The ADC may digitize signals on PA0…PA7, as well as VDD_IO and an internal temperature sensor. The user can define four channels which are then converted sequentially and stored in four separate result registers. Each channel configuration consists of the multiplexer and the gain setting. The AX8052F100 contains an on−chip temperature sensor. Built−in calibration logic allows the temperature sensor to be calibrated in °C, °F or any other user defined temperature scale. The AX8052F100 also features two analog comparators. Each comparator can either compare two voltages on dedicated PA pins, or one voltage against the internal 1 V reference. The comparator output can be routed to a dedicated digital output pin or can be read by software. The comparators are clocked with the system clock. Timer, Output Compare and Input Capture The AX8052F100 features three general purpose 16−bit timers. Each timer can be clocked by the system clock, any of the available oscillators, or a dedicated input pin. The timers also feature a programmable clock inversion, a programmable prescaler that can divide by powers of two, and an optional clock synchronization logic that synchronizes the clock to the system clock. All three counters are identical and feature four different counting www.onsemi.com 15 System Clock SYSCLK LPXOSC XOSC VDDIO LPOSC Temperature Sensor FRCOSC ADCCLKSRC AX8052F100 Free Running One Shot PA6 Timer 0 PA5 Timer 1 Prescaler ÷1,2,4,8,... PA7 PA4 PA3 Timer 2 PC4 PA2 PA1 ADCCONV Clock PA0 Trigger ADC Core PPP Ref x 0.1, x 1, x 10 Gain ADC Result VREF 1V 0.5 V Single Ended NNN ACOMP0IN ACOMP0ST/PA4/PC3 ACOMP0INV ACOMP0REF System Clock ACOMP1IN ACOMP1ST/PA7/PC1 ACOMP1INV ACOMP1REF Figure 7. ADC Block Diagram DMA Controller microcontroller. Additional logic prevents starvation of the DMA controller. The AX8052F100 features a dual channel DMA engine. Each DMA channel can either transfer data from XRAM to almost any peripheral on chip, or from almost any peripheral to XRAM. Both channels may also be cross−linked for memory−memory transfers. The DMA channels use buffer descriptors to find the buffers where data is to be retrieved or placed, thus enabling very flexible buffering strategies. The DMA channels access XRAM in a cycle steal fashion. They access XRAM whenever XRAM is not used by the microcontroller. Their priority is lower than the microcontroller, thus interfering very little with the AES Engine The AX8052F100 contains a dedicated engine for the government mandated Advanced Encryption Standard (AES). It features a dedicated DMA engine and reads input data as well as key stream data from the XRAM, and writes output data into a programmable buffer in the XRAM. The round number is programmable; the chip therefore supports AES−128, AES−192, and AES−256, as well as higher security proprietary variants. Key stream (key expansion) is www.onsemi.com 16 AX8052F100 Ports performed in software, adding to the flexibility of the AES engine. ECB (electronic codebook), CFB (cipher feedback) and OFB (output feedback) modes are directly supported without software intervention. In conjunction with the true random number generator a high degree of security can be achieved. VDDIO PORTx.y DIRx.y Crystal Oscillator 65 kW Special Function The on−chip crystal oscillator allows the use of an inexpensive quartz crystal as timing reference. Normally, the oscillator operates fully automatically. It is powered on whenever the system clock or any peripheral clock is programmed to be derived from the crystal clock. To hide crystal startup latencies, the oscillator may also be forced on using the OSCFORCERUN register. The transconductance of the oscillator is automatically controlled to ensure fast startup and low steady state current consumption. For lowest phase noise applications, transconductance may be programmed manually using the XTALOSC register. PALTx.y INTCHGx.y Interrupt PINx.y PINx read clock ANALOGx.y Figure 8. Port Pin Schematic Figure 8 shows the GPIO logic. The DIR register bit determines whether the port pin acts as an output (1) or an input (0). If configured as an output, the PALT register bit determines whether the port pin is connected to a peripheral output (1), or used as a GPIO pin (0). In the latter case, the PORT register bit determines the port pin drive value. If configured as an input, the PORT register bit determines whether a pull−up resistor is enabled (1) or disabled (0). Inputs have chmitt−trigger characteristic. Port A inputs may be disabled by setting the ANALOGA register bit; this prevents additional current consumption if the voltage level of the port pin is mid−way between logic low and logic high, when the pin is used as an analog input. Port A, B and C pins may interrupt the microcontroller if their level changes. The INTCHG register bit enables the interrupt. The PIN register bit reflects the value of the port pin. Reading the PIN register also resets the interrupt if interrupt on change is enabled. www.onsemi.com 17 AX8052F100 APPLICATION INFORMATION Typical Application Diagrams Figure 9. Typical Application Diagram PB3 is driven by the debugger only to bring the AX8052F100 out of Deep Sleep. It is high impedance otherwise. Port Pins PR0−PR5 may be used to connect an AXRadio Chip, or as General Purpose I/O. Crystals are optional. Crystal Load Capacitances should be chosen according to the Crystal Datasheet. Figure 9 shows a typical application schematic. Short Jumper JP1−1 if it is desired to supply the target board from the Debug Adapter (50 mA max). Connect the bottom exposed pad of the AX8052F100 to ground. If the debugger is not running, PB6 and PB7 are not driven by the Debug Adapter. If the debugger is running, the PB6 and PB7 values that the software reads may be set using the Pin Emulation feature of the debugger. www.onsemi.com 18 AX8052F100 QFN28 Soldering Profile Preheat Reflow Cooling tP TP Temperature TL tL TsMAX TsMIN ts 25°C T25°C to Peak Time Figure 10. QFN28 Soldering Profile Table 13. Profile Feature Pb−Free Process Average Ramp−Up Rate 3°C/s max. Preheat Preheat Temperature Min TsMIN 150°C Temperature Max TsMAX 200°C Time (TsMIN to TsMAX) ts 60 – 180 sec Time 25°C to Peak Temperature T25°C to Peak 8 min max. Liquidus Temperature TL 217°C Time over Liquidus Temperature tL 60 – 150 s Peak Temperature tp 260°C Time within 5°C of actual Peak Temperature Tp 20 – 40 s Reflow Phase Cooling Phase Ramp−down rate 6°C/s max. 1. All temperatures refer to the top side of the package, measured on the package body surface. www.onsemi.com 19 AX8052F100 QFN28 Recommended Pad Layout 1. PCB land and solder masking recommendations are shown in Figure 11. A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads. D = PCB land length = QFN solder pad length + 0.1 mm E = PCB land width = QFN solder pad width + 0.1 mm Figure 11. PCB Land and Solder Mask Recommendations 3. For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil with an array of smaller openings that sum to 50% of the QFN exposed pad area. Solder paste should be applied through an array of squares (or circles) as shown in Figure 12. 4. The aperture opening for the signal pads should be between 50−80% of the QFN pad area as shown in Figure 13. 5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 6. The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 7. No−clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water−soluble flux is used. 2. Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the IC will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. Assembly Process Stencil Design & Solder Paste Application 1. Stainless steel stencils are recommended for solder paste application. 2. A stencil thickness of 0.125 – 0.150 mm (5 – 6 mils) is recommended for screening. Figure 12. Solder Paste Application on Exposed Pad www.onsemi.com 20 AX8052F100 Minimum 50% coverage 62% coverage Maximum 80% coverage Figure 13. Solder Paste Application on Pins REFERENCES [1] ON Semiconductor AX8052 Programming Manual, see http://www.onsemi.com [2] ON Semiconductor AX8052 Silicon Errata, see http://www.onsemi.com DEVICE VERSIONS The revision of the AX8052 silicon can be determined by the device marking or by reading the SILICONREV register. [2] documents the differences between silicon revisions. Table 14. DEVICE VERSIONS Device Marking AX8052 Version SILICONREV AX8052F100−1 1 0x8E (10001110) AX8052F100−2 1C 0x8F (10001111) AX8052F100−3 2 0x90 (10010000) www.onsemi.com 21 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN28 5x5, 0.5P CASE 485EH ISSUE A 1 28 SCALE 2:1 A B D PIN ONE REFERENCE ÉÉ ÉÉ L DATE 25 NOV 2015 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e L L1 0.05 C 0.05 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C C SIDE VIEW NOTE 4 DETAIL A 8 28X ÉÉ ÇÇ TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION SEATING PLANE GENERIC MARKING DIAGRAM* D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 15 L E2 1 28 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 5.00 BSC 3.40 3.50 5.00 BSC 3.40 3.50 0.50 BSC 0.44 0.54 −−− 0.15 22 e 28X BOTTOM VIEW b 0.10 M C A B 0.05 M C XXXXX A WL YY WW G NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 28X 0.69 3.60 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 1 3.60 5.30 0.50 PITCH 28X 0.32 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON04198G QFN28 5X5, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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