CAT1023ZI25

CAT1021, CAT1022, CAT1023 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer DESCRIPTION FEATURES The CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontrollerbased systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus. Precision Power Supply Voltage Monitor — 5V, 3.3V and 3V systems — Five threshold voltage options Watchdog Timer Active High or Low Reset — Valid reset guaranteed at VCC = 1V The CAT1021 and CAT1023 provide a precision VCC sense circuit and two open drain outputs: one (RESET) ¯¯¯¯¯¯) drives low whenever drives high and the other (RESET VCC falls below the reset threshold voltage. The ¯¯¯¯¯¯ output and does not have CAT1022 has only a RESET a Write Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high. 400kHz I2C Bus 2.7V to 5.5V Operation Low power CMOS technology 16-Byte Page Write Buffer Built-in inadvertent write protection — WP pin (CAT1021) All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI. 1,000,000 Program/Erase cycles Manual Reset Input 100 year data retention Industrial and extended temperature ranges 8-pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot-print) packages The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and ¯¯¯¯¯¯ pin or a other ICs is simple. In addition, the RESET separate input, ¯¯¯ MR , can be used as an input for pushbutton manual reset capability. — TDFN max height is 0.8mm For Ordering Information details, see page 19. The on-chip, 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include an 8-pin DIP and surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP packages. The TDFN package thickness is 0.8mm maximum. TDFN footprint options are 3x3mm. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 BLOCK DIAGRAM THRESHOLD VOLTAGE OPTION EXTERNALLOAD SENSEAMPS SHIFT REGISTERS DOUT ACK VCC WORDADDRESS BUFFERS VSS COLUMN DECODERS START/STOP LOGIC SDA Minimum Threshold Maximum Threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 2kbit EEPROM XDEC WP (CAT1021) Part Dash Number CONTROL LOGIC DATA IN STORAGE HIGHVOLTAGE/ TIMING CONTROL RESET Controller STATE COUNTERS Precision MR SLAVE ADDRESS COMPARATORS Vcc Monitor RESET (CAT1021/23) RESET SCL WDI (CAT1023) PIN CONFIGURATION DIP Package (L) SOIC Package (W) TSSOP Package (Y) MSOP Package (Z) (Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (ZD4) 1 ¯¯¯ MR VCC 8 Doc. No. 3009 Rev. L ¯¯¯ MR 1 8 VCC ¯¯¯¯¯¯ RESET 2 7 RESET WP 3 6 SCL VSS 4 5 SDA ¯¯¯ MR 1 8 VCC ¯¯¯¯¯¯ RESET 2 7 NC NC 3 6 SCL VSS 4 5 SDA ¯¯¯ MR 1 8 VCC ¯¯¯¯¯¯ RESET 2 7 WDI RESET 3 6 SCL VSS 4 5 SDA CAT1021 CAT1022 CAT1023 RESET 7 CAT1021 SCL 6 3 WP SDA 5 4 VSS VCC 8 1 ¯¯¯ MR NC 7 CAT1022 ¯¯¯¯¯¯ 2 RESET SCL 6 3 NC SDA 5 4 VSS VCC 8 1 ¯¯¯ MR WDI 7 CAT1023 2 ¯¯¯¯¯¯ 2 RESET ¯¯¯¯¯¯ 2 RESET SCL 6 3 RESET SDA 5 4 VSS © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 PIN FUNCTION PIN DESCRIPTION ¯¯¯¯¯¯: RESET OUTPUT RESET/RESET (RESET CAT1021/23 Only) ¯¯¯¯¯¯ can be used These are open drain pins and RESET as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the ¯¯¯¯¯¯ pin must be connected through a pull-up RESET resistor. Pin Name NC ¯¯¯¯¯¯ RESET VSS SCL: SERIAL CLOCK Serial clock input. No Connect Active Low Reset Input/Output Ground SDA Serial Data/Address SCL Clock Input RESET SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. Function Active High Reset Output (CAT1021/23) VCC Power Supply WP Write Protect (CAT1021 only) ¯¯¯ MR Manual Reset Input WDI Watchdog Timer Interrupt (CAT1023) OPERATING TEMPERATURE RANGE ¯¯¯ MR : MANUAL RESET INPUT Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor. Industrial -40ºC to 85ºC Extended -40ºC to 125ºC WP (CAT1021 Only): WRITE PROTECT INPUT When WP input is tied to VSS or left unconnected write operations to the entire array are allowed. When tied to VCC, the entire array is protected. This input has an internal pull down resistor. WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active. CAT102X FAMILY OVERVIEW CAT1021 Watchdog Monitor Pin SDA CAT1022 SDA 2k CAT1023 WDI 2k Device Manual Reset Input Pin Watchdog Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM 2k CAT1024 2k CAT1025 2k CAT1026 2k CAT1027 WDI 2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 ABSOLUTE MAXIMUM RATINGS(1) Parameters Ratings Units –55 to +125 ºC –65 to +150 ºC –2.0 to VCC + 2.0 V –2.0 to 7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 ºC 100 mA Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (2) VCC with Respect to Ground Output Short Circuit Current (3) D.C. OPERATING CHARACTERISTICS VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min ILI Input Leakage Current VIN = GND to Vcc ILO Output Leakage Current VIN = GND to Vcc ICC1 Power Supply Current (Write) ICC2 ISB VIL(4) VIH (4) Typ Max Units -2 10 µA -10 10 µA fSCL = 400kHz VCC = 5.5V 3 mA Power Supply Current (Read) fSCL = 400kHz VCC = 5.5V 1 mA Standby Current Vcc = 5.5V, VIN = GND or Vcc 60 µA Input Low Voltage -0.5 0.3 x Vcc V Input High Voltage 0.7 x Vcc Vcc + 0.5 V 0.4 V VOL Output Low Voltage ¯¯¯¯¯¯) (SDA, RESET IOL = 3mA VCC = 2.7V VOH Output High Voltage (RESET) IOH = -0.4mA VCC = 2.7V Vcc - 0.75 CAT102x-45 (VCC = 5.0V) 4.50 4.75 CAT102x-42 (VCC = 5.0V) 4.25 4.50 CAT102x-30 (VCC = 3.3V) 3.00 3.15 CAT102x-28 (VCC = 3.3V) 2.85 3.00 CAT102x-25 (VCC = 3.0V) 2.55 2.70 VTH VRVALID VRT (5) Reset Threshold Reset Output Valid VCC Voltage Reset Threshold Hysteresis V V 1.00 V 15 mV Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) VIL min and VIH max are reference values only and are not tested. (5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 4 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 CAPACITANCE TA = 25ºC, f = 1.0MHz, VCC = 5V Symbol COUT CIN (1) (1) Test Output Capacitance Input Capacitance Test Conditions Max Units VOUT = 0V 8 pF VIN = 0V 6 pF AC CHARACTERISTICS VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle(2) Symbol Parameter Min Max Units fSCL Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs (1) SDA and SCL Rise Time 300 ns (1) SDA and SCL Fall Time 300 ns tR tF tHD; STA Start Condition Hold Time 0.6 µs tSU; STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD; DAT Data Input Hold Time 0 ns tSU; DAT Data Input Setup Time 100 ns tSU; STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid tDH 900 ns Data Out Hold Time 50 ns (1) Time the Bus must be Free Before a New Transmission Can Start 1.3 µs (3) Write Cycle Time (Byte or Page) tBUF tWC 5 ms Notes: (1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (2) Test Conditions according to “AC Test Conditions” table. (3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 RESET CIRCUIT AC CHARACTERISTICS Symbol Parameter tPURST tRDP Test Conditions Min Typ Max Units Power-Up Reset Timeout Note 2 130 200 270 ms VTH to RESET output Delay Note 3 5 µs tGLITCH VCC Glitch Reject Pulse Width Note 4, 5 30 ns MR Glitch Manual Reset Glitch Immunity Note 1 100 ns tMRW MR Pulse Width Note 1 tMRD MR Input to RESET Output Delay Note 1 tWD Watchdog Timeout Note 1 1.0 Test Conditions Min 5 µs 1 µs 1.6 2.1 sec Typ Max Units POWER-UP TIMING (5), (6) Symbol Parameter tPUR Power-Up to Read Operation 270 ms tPUW Power-Up to Write Operation 270 ms AC TEST CONDITIONS Parameter Test Conditions Input Pulse Voltages 0.2VCC to 0.8VCC Input Rise and Fall times 10ns Input Reference Voltages 0.3VCC , 0.7VCC Output Reference Voltages Output Load 0.5VCC Current Source: IOL = 3mA; CL = 100pF RELIABILITY CHARACTERISTICS Symbol NEND TDR (5) (5) VZAP(5) ILTH(5)(7) Parameter Reference Test Method Min Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte Data Retention MIL-STD-883, Test Method 1008 100 Years ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts JEDEC Standard 17 100 mA Latch-Up Max Units Notes: (1) Test Conditions according to “AC Test Conditions” table. (2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data (5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. (7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V. Doc. No. 3009 Rev. L 6 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 DEVICE OPERATION Hardware Data Protection The CAT1021/22/23 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Reset Controller Description The CAT1021/22/23 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. During power-down, the RESET outputs will be active ¯¯¯¯¯¯ output will be when VCC falls below VTH. The RESET valid so long as VCC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). In addition, the CAT1021 includes a Write Protection Input which when tied to VCC will disable any write operations to the device. Reset output timing is shown in Figure 1. Manual Reset Operation ¯¯¯¯¯¯ pin can operate as reset output and The RESET manual reset input. The input is edge triggered; that ¯¯¯¯¯¯ input will initiate a reset timeout after is, the RESET detecting a high to low transition. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, CAT1021/22/23 devices will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. The CAT1023 is designed with the Watchdog timer feature on the WDI pin. The CAT1021 and CAT1022 monitor the SDA line. If WDI or SDA does not toggle within a 1.6 second interval, the reset condition will be generated on the reset outputs. The watchdog timer is cleared by any transition on a monitored line. ¯¯¯¯¯¯ I/O is driven to the active state, the 200 When RESET msec timer will begin to time the reset interval. If external reset is shorter than 200ms, Reset outputs will remain active at least 200ms. The CAT1021/22/23 also have a separate manual reset input. Driving the ¯¯¯ MR input low by connecting a pushbutton (normally open) from ¯¯¯ MR pin to GND will generate a reset condition. The input has an internal pull up resistor. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. Reset remains asserted while ¯¯¯ MR is low and for the Reset Timeout period after ¯¯¯ MR input has gone high. Glitches shorter than 100ns on ¯¯¯ MR input will not generate a reset pulse. No external debouncing circuits are required. Manual reset operation using ¯¯¯ MR input is shown in Figure 2. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 Figure 1. RESET Output Timing t GLITCH VTH VRVALID t PURST VCC t RPD t PURST t RPD RESE T RESE T Figure 2: ¯¯¯ MR Operation and Timing t MRW MR t MRD t PURST RESET RESET Doc. No. 3009 Rev. L 8 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 SDA when SCL is HIGH. The CAT1021/22/23 monitor the SDA and SCL lines and will not respond until this condition is met. EMBEDDED EEPROM OPERATION The CAT1021/22/23 feature a 2-kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP CONDITION A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. 2 I C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT1021/22/23 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1021/22/23 then perform a Read or ¯¯ bit. Write operation depending on the R/W START CONDITION The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of Figure 3. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 4. Write Cycle Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 START CONDITION ADDRESS Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 ACKNOWLEDGE WRITE OPERATIONS After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information ¯¯ bit set to zero) to the Slave device. After (with the R/W the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The device acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. All devices respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When a device begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the device will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 5. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 6. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 7: Slave Address Bits Default Configuration Doc. No. 3009 Rev. L 1 0 1 10 0 0 0 0 R/W © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 Page Write The CAT1021/22/23 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1021/22/23 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1021/22/23 in a single write cycle. Figure 8. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 9: Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n S T DATA n+15 O P DATA n+1 S P A C K © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice A C K 11 A C K A C K A C K Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1021/22/23 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. READ OPERATIONS The READ operation for the CAT1021/22/23 is initiated in the same manner as the write operation with one ¯¯ bit is set to one. Three different READ exception, the R/W operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. WRITE PROTECTION PIN (WP) The Write Protection feature (CAT1021 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1021 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. Figure 10. Immediate Address Read Timing BUS ACTIVIT Y: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K SCL SDA 8 N O A C K 9 8TH BI T DATA OUT Doc. No. 3009 Rev. L DATA NO ACK 12 STOP © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 Immediate/Current Address Read The CAT1021/22/23 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1021/22/23 receives its slave address infor¯¯ bit set to one), it issues an mation (with the R/W acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1021/22/23 acknowledges, the Master device sends the START condition and the slave address ¯¯ bit set to one. The again, this time with the R/W CAT1021/22/23 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1021/22/23 sends the inital 8bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1021/22/23 will continue to output an 8bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1021/22/23 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1021/22/23 address bits so that the entire memory array can be read during one operation. Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S S T O P SLAVE ADDRESS P S A C K A C K A C K DATA n N O A C K Figure 12. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice A C K A C K 13 A C K N O A C K Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A c A1 L e eB b2 b SYMBOL A A1 A2 b b2 c D E E1 e eB L MIN NOM MAX 4.57 0.38 3.05 0.36 1.14 0.21 9.02 7.62 6.09 7.87 2.92 0.46 0.26 7.87 6.35 2.54 BSC 3.81 0.56 1.77 0.35 10.16 8.25 7.11 9.65 3.81 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. Doc. No. 3009 Rev. L 14 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 8-LEAD 150 MIL SOIC (W) E1 E h x 45 D C A q1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L q1 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.50 1.27 8° 0.25 0.40 0° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MS-012 dimensions. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 8-LEAD TSSOP (V) D 5 8 SEE DETAIL A c E E1 E/2 GAGE PLANE 4 1 PIN #1 IDENT. 0.25 q1 L A2 SEATING PLANE SEE DETAIL A A e A1 b SYMBOL A A1 A2 b c D E E1 e L q1 NOM MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 0.90 3.00 6.4 4.40 0.65 BSC 0.60 MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MO-153 Doc. No. 3009 Rev. L 16 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 8-LEAD MSOP (Z) E1 e e E e D GAUGE PLANE A2 A c L2 θ b L A1 L1 SYMBOL MIN NOM MAX 0.05 0.10 0.15 A A1 1.1 A2 0.75 0.85 0.95 b 0.28 0.33 0.38 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 c e L 0.65 BSC 0.35 0.45 0.55 L1 L2 Ө 0º 6º For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. This part is compliant with JEDEC Specification MO-187 Variations AA. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 17 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 TDFN 3 x 3 PACKAGE (ZD4) 3 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) (3) (4) (5) All dimentions in mm. Angels in degrees. Complies to JEDEC MO-229 / WEEC. Coplanarity shall not exceed 0.10mm. Warpage shall not exceed 0.10mm. Package lenght / package width are considered as special characteristic(s). Doc. No. 3009 Rev. L 18 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1021, CAT1022, CAT1023 EXAMPLE OF ORDERING INFORMATION Prefix Device # Suffix CAT 1021 W I -30 – Temperature Range I = Industrial (-40ºC to 85ºC) Company ID Product Number 1021: 2K 1022: 2K 1023: 2K Package L: PDIP W: SOIC Y: TSSOP Z: MSOP ZD4: TDFN 3x3mm (5) Reset Threshold Voltage -45: 4.50V – 4.75V -42: 4.25V – 4.50V -30: 3.00V – 3.15V -28: 2.85V – 3.00V -25: 2.55V – 2.70V G T3 Tape & Reel T: Tape & Reel 2: 2000/Reel (only TDFN) 3: 3000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu Notes: (1) (2) (3) (4) (5) All packages are RoHS-compliant (Lead-free, Halogen-free). The standard lead finish is Matte-Tin. The device used in the above example is a CAT1021WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel). For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. TDFN not available in NiPdAu (–G) version. Ordering Part Number – CAT1021xx CAT1021LI-45 CAT1021ZI-45 CAT1021LI-42 CAT1021ZI-42 CAT1021LI-30 CAT1021ZI-30 CAT1021LI-28 CAT1021ZI-28 CAT1021LI-25 CAT1021ZI-25 CAT1021WI-45 CAT1021ZD4I-45 CAT1021WI-42 CAT1021ZD4I-42 CAT1021WI-30 CAT1021ZD4I-30 CAT1021WI-28 CAT1021ZD4I-28 CAT1021WI-25 CAT1021ZD4I-25 CAT1021YI-45 CAT1021YI-42 CAT1021YI-30 CAT1021YI-28 CAT1021YI-25 CAT1022xx and Cat1023xx Ordering Part Numbers are located on page 20. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 19 Doc. No. 3009 Rev. L CAT1021, CAT1022, CAT1023 Ordering Part Number – CAT1022xx CAT1022LI-45 CAT1022ZI-45 CAT1022LI-42 CAT1022ZI-42 CAT1022LI-30 CAT1022ZI-30 CAT1022LI-28 CAT1022ZI-28 CAT1022LI-25 CAT1022ZI-25 CAT1022WI-45 CAT1022ZD4I-45 CAT1022WI-42 CAT1022ZD4I-42 CAT1022WI-30 CAT1022ZD4I-30 CAT1022WI-28 CAT1022ZD4I-28 CAT1022WI-25 CAT1022ZD4I-25 CAT1022YI-45 CAT1022YI-42 CAT1022YI-30 CAT1022YI-28 CAT1022YI-25 Ordering Part Number – CAT1023xx CAT1023LI-45 CAT1023ZI-45 CAT1023LI-42 CAT1023ZI-42 CAT1023LI-30 CAT1023ZI-30 CAT1023LI-28 CAT1023ZI-28 CAT1023LI-25 CAT1023ZI-25 CAT1023WI-45 CAT1023ZD4I-45 CAT1023WI-42 CAT1023ZD4I-42 CAT1023WI-30 CAT1023ZD4I-30 CAT1023WI-28 CAT1023ZD4I-28 CAT1023WI-25 CAT1023ZD4I-25 CAT1023YI-45 CAT1023YI-42 CAT1023YI-30 CAT1023YI-28 CAT1023YI-25 Doc. No. 3009 Rev. L 20 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date Rev. Reason 9/25/2003 F Added Green Package logo Updated DC Operating Characteristic notes Updated Reliability Characteristics notes 11/7/2003 G Eliminated Automotive temperature range Updated Ordering Information with “Green” package codes Updated Reset Circuit AC Characteristics 4/12/2004 H Eliminated data sheet designation Updated Reel Ordering Information 11/1/2004 I Eliminated 8-pad TDFN package (3x4.9mm) Changed SOIC package designators Added package outlines 11/04/2004 J Update Pin Configuration 11/11/2004 K Update Feature Update Description Update DC Operating Characteristic Update AC Characteristics 02/02/2007 L Update Example of Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include ech of the following: Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: 3009 Revision: L Issue date: 02/02/07