CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2k-bit
CMOS EEPROM and Manual Reset
FEATURES
DESCRIPTION
Precision Power Supply Voltage Monitor
The CAT1024 and CAT1025 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
— 5V, 3.3V and 3V systems
— Five threshold voltage options
Active High or Low Reset
— Valid reset guaranteed at VCC = 1V
400kHz I2C Bus
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
¯¯¯¯¯¯) drives low whenever VCC falls
and the other (RESET
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
2.7V to 5.5V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1025)
The CAT1024 also provides a precision VCC sense
¯¯¯¯¯¯ output and does not
circuit, but has only a RESET
have a Write Protect input.
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
¯¯¯¯¯¯ pin or a separate input, ¯¯¯
the RESET
MR , can be used
as an input for push-button manual reset capability.
Industrial and extended temperature ranges
Green packages available with NiPdAu Lead
finished
For Ordering Information details, see page 19.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until
VCC reaches the reset threshold during power up.
Available packages include an 8-pin PDIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thickness is 0.8mm maximum. TDFN footprint is 3x3mm.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
BLOCK DIAGRAM
THRESHOLD VOLTAGE OPTION
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WORDADDRESS
BUFFERS
VSS
SDA
COLUMN
DECODERS
START/STOP
LOGIC
Minimum
Threshold
Maximum
Threshold
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
2kbit
EEPROM
XDEC
WP*
Part Dash
Number
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
Precision
MR
SLAVE
ADDRESS
COMPARATORS
Vcc Monitor
RESET*
SCL
RESET
* CAT1025 Only
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
¯¯¯
MR
1
¯¯¯¯¯¯
RESET
2
CAT1024
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (ZD4)
8
VCC
VCC 8
7
NC
NC 7
1 ¯¯¯
MR
CAT1024
¯¯¯¯¯¯
2 RESET
NC
3
6
SCL
SCL 6
3 NC
VSS
4
5
SDA
SDA 5
4 VSS
1 ¯¯¯
MR
¯¯¯
MR
1
8
VCC
VCC 8
¯¯¯¯¯¯
RESET
2
7
WP
WDI 7
CAT1025
CAT1025
¯¯¯¯¯¯
2 RESET
RESET
3
6
SCL
SCL 6
3 RESET
VSS
4
5
SDA
SDA 5
4 VSS
Doc. No. MD-3008 Rev. P
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
PIN FUNCTION
PIN DESCRIPTION
Pin
Name
NC
¯¯¯¯¯¯: RESET OUTPUTs
RESET/RESET
(RESET CAT1025 Only)
¯¯¯¯¯¯ can be used
These are open drain pins and RESET
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
¯¯¯¯¯¯ pin must be connected through a pull-up
RESET
resistor.
¯¯¯¯¯¯
RESET
SCL: SERIAL CLOCK
Serial clock input.
No Connect
Active Low Reset Input/Output
VSS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Function
Active High Reset Output
(CAT1025 only)
VCC
Power Supply
WP
Write Protect (CAT1025 only)
¯¯¯
MR
Manual Reset Input
OPERATING TEMPERATURE RANGE
¯¯¯
MR : MANUAL RESET INPUT
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset
condition. Reset outputs are active while ¯¯¯
MR input is
low and for the reset timeout period after ¯¯¯
MR returns
to high. The input has an internal pull up resistor.
Industrial
-40ºC to 85ºC
Extended
-40ºC to 125ºC
WP (CAT1025 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write
operations to the entire array are allowed. When tied
to VCC, the entire array is protected. This input has an
internal pull down resistor.
CAT10XX FAMILY OVERVIEW
CAT1021
Watchdog
Monitor
Pin
SDA
CAT1022
SDA
2k
CAT1023
WDI
2k
Device
Manual
Reset
Input Pin
Watchdog
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
EEPROM
2k
CAT1024
2k
CAT1025
2k
CAT1026
2k
CAT1027
WDI
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
–55 to +125
ºC
–65 to +150
ºC
–2.0 to VCC + 2.0
V
–2.0 to 7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 secs)
300
ºC
100
mA
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
VCC with Respect to Ground
Output Short Circuit Current
(3)
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
ILI
Input Leakage Current
VIN = GND to VCC
ILO
Output Leakage Current
VIN = GND to VCC
ICC1
Power Supply Current (Write)
ICC2
ISB
VIL(4)
VIH
(4)
Typ
Max
Units
-2
10
µA
-10
10
µA
fSCL = 400kHz
VCC = 5.5V
3
mA
Power Supply Current (Read)
fSCL = 400kHz
VCC = 5.5V
1
mA
Standby Current
Vcc = 5.5V,
VIN = GND or VCC
40
µA
Input Low Voltage
-0.5
0.3 x VCC
V
Input High Voltage
0.7 x Vcc
VCC + 0.5
V
0.4
V
VOL
Output Low Voltage
¯¯¯¯¯¯)
(SDA, RESET
IOL = 3mA
VCC = 2.7V
VOH
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 2.7V
VCC - 0.75
CAT102x-45
(VCC = 5.0V)
4.50
4.75
CAT102x-42
(VCC = 5.0V)
4.25
4.50
CAT102x-30
(VCC = 3.3V)
3.00
3.15
CAT102x-28
(VCC = 3.3V)
2.85
3.00
CAT102x-25
(VCC = 3.0V)
2.55
2.70
VTH
VRVALID
VRT
(5)
Reset Threshold
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
V
V
1.00
V
15
mV
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) VIL min and VIH max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. MD-3008 Rev. P
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
COUT
CIN
(1)
(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
Max
Units
VOUT = 0V
8
pF
VIN = 0V
6
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
(1)
SDA and SCL Rise Time
300
ns
(1)
SDA and SCL Fall Time
300
ns
tR
tF
tHD; STA
Start Condition Hold Time
0.6
µs
tSU; STA
Start Condition Setup Time (for a Repeated Start)
0.6
µs
tHD; DAT
Data Input Hold Time
0
ns
tSU; DAT
Data Input Setup Time
100
ns
tSU; STO
Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
50
Time the Bus must be Free Before a New Transmission Can Start
1.3
tBUF
(1)
tWC(3)
900
Write Cycle Time (Byte or Page)
ns
ns
µs
5
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
tPURST
tRDP
tGLITCH
MR Glitch
Test Conditions
Min
Typ
Max
Units
Power-Up Reset Timeout
Note 2
130
200
270
ms
VTH to RESET Output Delay
Note 3
5
µs
VCC Glitch Reject Pulse Width
Note 4, 5
30
ns
Manual Reset Glitch Immunity
Note 1
tMRW
MR Pulse Width
Note 1
tMRD
MR Input to RESET Output Delay
Note 1
100
ns
5
µs
1
µs
Max
Units
POWER-UP TIMING (5), (6)
Symbol
Parameter
Test Conditions
Min
Typ
tPUR
Power-Up to Read Operation
270
ms
tPUW
Power-Up to Write Operation
270
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2VCC to 0.8VCC
Input Rise and Fall Times
10ns
Input Reference Voltages
0.3VCC, 0.7VCC
Output Reference Voltages
Output Load
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol
NEND
(5)
TDR(5)
VZAP(5)
ILTH(5)(7)
Parameter
Reference Test Method
Min
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
JEDEC Standard 17
100
mA
Latch-Up
Max
Units
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. MD-3008 Rev. P
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
DEVICE OPERATION
pushbutton (normally open) from ¯¯¯
MR pin to GND will
generate a reset condition. The input has an internal
pull up resistor.
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
Reset remains asserted while ¯¯¯
MR is low and for the
Reset Timeout period after ¯¯¯
MR input has gone high.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
Glitches shorter than 100ns on ¯¯¯
MR input will not generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using ¯¯¯
MR input
is shown in Figure 2.
Hardware Data Protection
The CAT1024/25 supervisors have been designed to
solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory
location which is assumed to hold correct data.
During power-down, the RESET outputs will be active
¯¯¯¯¯¯ output will be
when VCC falls below VTH. The RESET
valid so long as VCC is >1.0V (VRVALID). The device is
designed to ignore the fast negative going VCC transient pulses (glitches).
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5ms) before VCC reaches the minimum value of 2V.
Reset output timing is shown in Figure 1.
Manual Reset Operation
¯¯¯¯¯¯ pin can operate as reset output and
The RESET
manual reset input. The input is edge triggered; that
¯¯¯¯¯¯ input will initiate a reset timeout after
is, the RESET
detecting a high to low transition.
¯¯¯¯¯¯ I/O is driven to the active state, the
When RESET
200ms timer will begin to time the reset interval. If
external reset is shorter than 200ms, Reset outputs
will remain active at least 200ms.
In addition, the CAT1025 includes a Write Protection
Input which when tied to VCC will disable any write
operations to the device.
The CAT1024/25 also have a separate manual reset
input. Driving the ¯¯¯
MR input low by connecting a
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
Figure 1. RESET Output Timing
t
GLITCH
VTH
VRVALID
t PURST
VCC
t RPD
t PURST
t RPD
RESE T
RESE T
Figure 2: ¯¯¯
MR Operation and Timing
t MRW
MR
t MRD
t PURST
RESET
RESET
Doc. No. MD-3008 Rev. P
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
EMBEDDED EEPROM OPERATION
The CAT1024 and CAT1025 feature a 2-kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter
or receiver, but the Master device controls which mode
is activated.
SDA when SCL is HIGH. The CAT1024/25 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
2
I C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT1024/25 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address. The CAT1024/25 then perform a Read or
¯¯ bit.
Write operation depending on the R/W
START CONDITION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
START
CONDITION
ADDRESS
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
¯¯ bit set to zero) to the Slave device. After
(with the R/W
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1024/25 acknowledges once more and the
Master generates the STOP condition. At this time, the
device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
The CAT1024/25 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with
a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1024/25 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1024/25 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data transmis–
sion and waits for a STOP condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 7: Slave Address Bits
Default Configuration
Doc. No. MD-3008 Rev. P
1
0
1
10
0
0
0
0
R/W
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
Page Write
The CAT1024/25 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of
terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the CAT1024/25
will respond with an acknowledge and internally
increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
A
C
K
A
C
K
Figure 9: Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
S
T
DATA n+15 O
P
DATA n+1
S
P
A
C
K
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
A
C
K
11
A
C
K
A
C
K
A
C
K
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
READ OPERATIONS
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
¯¯ bit is set to one. Three different READ operations
the R/W
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addresses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 10. Immediate Address Read Timing
BUS ACTIVIT Y:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8TH BI T
DATA OUT
Doc. No. MD-3008 Rev. P
NO ACK
12
STOP
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
Immediate/Current Address Read
The CAT1024 and CAT1025 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1024/1025 receives its slave
¯¯ bit set to one), it
address information (with the R/W
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1024 and CAT1025 acknowledges, the Master
device sends the START condition and the slave
¯¯ bit set to one.
address again, this time with the R/W
The CAT1024 and CAT1025 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1024 and CAT1025 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
The data being transmitted from the CAT1024 and
CAT1025 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1024 and CAT1025 address bits so that the entire
memory array can be read during one operation.
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
T
O
P
SLAVE
ADDRESS
S
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L) (1)(2)
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
E1
6.10
eB
7.87
L
2.92
6.35
7.11
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
Doc. No. MD-3008 Rev. P
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
SOIC 8-Lead 150mils (W)
(1)(2)
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
e
PIN # 1
IDENTIFICATION
NOM
MAX
4.00
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
TSSOP 8-Lead (V)
(1)(2)
b
SYMBOL
MIN
NOM
A
A1
E1
E
MAX
1.20
0.05
0.15
A2
0.80
b
0.19
0.90
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
e
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
1.05
0.75
8°
e
TOP VIEW
D
A2
A
A1
c
θ1
L1
SIDE VIEW
L
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153
Doc. No. MD-3008 Rev. P
16
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
MSOP 8-Lead (Z)
(1)(2)
SYMBOL
MIN
NOM
MAX
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
A
E
E1
1.10
b
0.22
0.38
c
0.13
0.23
D
2.90
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
e
L
0.65 BSC
0.40
0.60
0.80
L1
0.95 REF
L2
0.25 BSC
θ
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
17
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
SIDE VIEW
TOP VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
A3
A1
0.23
0.30
0.37
D
2.90
3.00
3.10
D2
2.20
2.30
2.40
E
2.90
3.00
3.10
E2
1.40
1.50
1.60
e
BOTTOM VIEW
A
0.20 REF
b
L
D2
FRONT VIEW
0.65 TYP
0.20
0.30
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-229.
Doc. No. MD-3008 Rev. P
18
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
EXAMPLE OF ORDERING INFORMATION (1)
Prefix
Device # Suffix
CAT
1024
W
I
-30
–
Temperature Range
I = Industrial (-40ºC to 85ºC)
Company ID
Product
Number
1024: 2K
1025: 2K
Package
L: PDIP
W: SOIC
Y: TSSOP
Z: MSOP
ZD4: TDFN 3 x 3mm (5)
Ordering Part Number – CAT1024xx
CAT1024LI-45-G
CAT1024ZI-45-GT3
CAT1024LI-42-G
CAT1024ZI-42-GT3
CAT1024LI-30-G
CAT1024ZI-30-GT3
CAT1024LI-28-G
CAT1024ZI-28-GT3
CAT1024LI-25-G
CAT1024ZI-25-GT3
CAT1024WI-45-GT3
CAT1024ZD4I-45-T2
CAT1024WI-42-GT3
CAT1024ZD4I-42-T2
CAT1024WI-30-GT3
CAT1024ZD4I-30-T2
CAT1024WI-28-GT3
CAT1024ZD4I-28-T2
CAT1024WI-25-GT3
CAT1024ZD4I-25-T2
CAT1024YI-45-GT3
CAT1024YI-42-GT3
CAT1024YI-30-GT3
CAT1024YI-28-GT3
CAT1024YI-25-GT3
Reset Threshold Voltage
-45: 4.50V – 4.75V
-42: 4.25V – 4.50V
-30: 3.00V – 3.15V
-28: 2.85V – 3.00V
-25: 2.55V – 2.70V
G
T3
Tape & Reel
T: Tape & Reel
2: 2000/Reel (only TDFN)
3: 3000/Reel
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Ordering Part Number – CAT1025xx
CAT1025LI-45-G
CAT1025ZI-45-GT3
CAT1025LI-42-G
CAT1025ZI-42-GT3
CAT1025LI-30-G
CAT1025ZI-30-GT3
CAT1025LI-28-G
CAT1025ZI-28-GT3
CAT1025LI-25-G
CAT1025ZI-25-GT3
CAT1025WI-45-GT3
CAT1025ZD4I-45-T2
CAT1025WI-42-GT3
CAT1025ZD4I-42-T2
CAT1025WI-30-GT3
CAT1025ZD4I-30-T2
CAT1025WI-28-GT3
CAT1025ZD4I-28-T2
CAT1025WI-25-GT3
CAT1025ZD4I-25-T2
CAT1025YI-45-GT3
CAT1025YI-42-GT3
CAT1025YI-30-GT3
CAT1025YI-28-GT3
CAT1025YI-25-GT3
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT1024WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
(5) TDFN not available in NiPdAu (–G) version.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
19
Doc. No. MD-3008 Rev. P
CAT1024, CAT1025
REVISION HISTORY
Date
7-Nov-03
Rev.
I
Description
Eliminated Automotive temperature range
12-Apr-04
J
Eliminated data sheet designation
Updated Reel Ordering Information
1-Nov-04
K
Changed SOIC package designators
Eliminated 8-pad TDFN (3 x 4.9mm) package
Added package outlines
4-Nov-04
L
11-Nov-04
M
2-Feb-07
N
28-Nov-07
O
07-Nov-08
P
Update Pin Configuration
Update Feature
Update Description
Update DC Operating Characteristic
Update AC Characteristics
Update Example of Ordering Information
Update Package Outline Drawings
Update Example of Ordering Information
Add “MD-“ to document number
Change logo and fine print to ON Semiconductor
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Doc. No. MD-3008, Rev. P
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Characteristics subject to change without notice
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