CAT1027ZD4I-30T3

CAT1026, CAT1027 Dual Voltage Supervisory Circuits with I²C Serial 2k-bit CMOS EEPROM FEATURES Precision VCC Power Supply Voltage Monitor — 5 V, 3.3 V and 3 V systems — Five threshold voltage options Additional voltage monitoring — Externally adjustable down to 1.25 V Watchdog timer (CAT1027 only) Active High or Low Reset — Valid reset guaranteed at VCC = 1 V 400 kHz I2C Bus 2.7 V to 5.5 V Operation Low power CMOS technology 16-Byte Page Write Buffer Built-in inadvertent write protection 1,000,000 Program/Erase cycles Manual Reset capability 100 year data retention Industrial and extended temperature ranges 8-pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot-print) packages — TDFN max height is 0.8 mm For Ordering Information details, see page 19. The CAT1027 is designed with a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. The CAT1027 features a watchdog timer interrupt input, WDI. The on-chip 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include 8-pin DIP and surface mount, 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm. supply monitor and reset circuit protects memory and systems controllers during power up/down and against brownout conditions. If power supply voltages are out of tolerance reset signals become active preventing the system microcontroller, ASIC, or peripherals from operating. The CAT1026 features two open drain reset outputs: ¯¯¯¯¯¯ one (RESET) drives high and the other (RESET) drives low whenever VCC falls below the threshold. Reset outputs become inactive typically 200ms after the supply voltage exceeds the reset threshold value. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. CAT1027 ¯¯¯¯¯¯ ¯¯¯¯¯¯ has only a RESET output. In addition, the RESET pin can be used as an input for push-button manual reset capability. The CAT1026 and CAT1027 provide an auxiliary voltage sensor input, VSENSE, which is used to monitor a second system supply. The auxiliary high impedance comparator drives the open drain output, VLOW, whenever the sense voltage is below 1.25 V threshold. DESCRIPTION The CAT1026 and CAT1027 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS techno– logy. Memory interface is via a 400 kHz I2C bus. The CAT1026 and CAT1027 provide a precision VCC sense circuit with five reset threshold voltage options that support 5 V, 3.3 V and 3 V systems. The power © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 1 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 BLOCK DIAGRAM EXTERNA LOAD L DOUT ACK VCC VSS WORDADDRESS BUFFERS START/STOP LOGIC 2kbit EEPROM COLUMN DECODERS SENSEAMPS SHIFT REGISTERS RESET THRESHOLD OPTION Part Dash Number -45 -42 -30 -28 XDEC CONTR OL LOGIC Minimum Threshold 4.50 4.25 3.00 2.85 2.55 Maximum Threshold 4.75 4.50 3.15 3.00 2.70 SDA -25 DATA IN STORAGE VCC Monitor VCC HIGHVOLTAGE/ TIMING CONTR OL STATE COUNTERS SCL + VREF - RESET Controller WDI (CAT1027) SLAVE ADDRESS COMPARATORS AuxiliaryVoltage Monitor VSENSE VREF + - RESET RESET (CAT1026) VLOW PIN CONFIGURATION DIP Package (L) SOIC Package (W) TSSOP Package (Y) MSOP Package (Z) VLOW ¯¯¯¯¯¯ RESET VSENSE VSS VLOW ¯¯¯¯¯¯ RESET VSENSE VSS 1 2 CAT1026 3 4 1 2 CAT1027 3 4 6 5 SCL SDA 6 5 8 7 SCL SDA VCC WDI SCL 6 SDA 5 VCC 8 WDI 7 CAT1027 SCL 6 SDA 5 8 7 VCC RESET (Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (ZD4) VCC 8 RESET 7 CAT1026 1 VLOW ¯¯¯¯¯¯ 2 RESET 3 VSENSE 4 VSS 1 VLOW ¯¯¯¯¯¯ 2 RESET 3 VSENSE 4 VSS Doc. No. MD-3010 Rev. P 2 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 PIN DESCRIPTION ¯¯¯¯¯¯ RESET/RESET: RESET OUTPUTs (RESET CAT1026 Only) ¯¯¯¯¯¯ These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the ¯¯¯¯¯¯ RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. VSENSE: AUXILIARY VOLTAGE MONITOR INPUT The VSENSE input is a second voltage monitor which is compared against CAT1026 and CAT1027 internal reference voltage of 1.25 V typically. Whenever the input voltage is lower than 1.25 V, the open drain VLOW output will be driven low. An external resistor divider is used to set the voltage level to be sensed. Connect VSENSE to VCC if unused. VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT This open drain output goes low when VSENSE is less than 1.25 V and goes high when VSENSE exceeds the reference voltage. WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active. PIN FUNCTION Pin Name ¯¯¯¯¯¯ RESET VSS SDA SCL RESET VCC VSENSE VLOW WDI Function Active Low Reset Input/Output Ground Serial Data/Address Clock Input Active High Reset Output (CAT1026 only) Power Supply Auxiliary Voltage Monitor Input Auxiliary Voltage Monitor Output Watchdog Timer Interrupt (CAT1027 only) OPERATING TEMPERATURE RANGE Industrial Extended -40ºC to 85ºC -40ºC to 125ºC CAT10XX FAMILY OVERVIEW Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin SDA SDA WDI Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM 2k CAT1021 CAT1022 2k 2k CAT1023 CAT1024 2k 2k CAT1025 2k CAT1026 WDI CAT1027 2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 3 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 ABSOLUTE MAXIMUM RATINGS (1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground VCC with Respect to Ground Package Power Dissipation Capability (TA = 25°C) Lead Soldering Temperature (10 s) Output Short Circuit Current (3) (2) Ratings –55 to +125 –65 to +150 –2.0 to VCC + 2.0 –2.0 to 7.0 1.0 300 100 Units ºC ºC V V W ºC mA D.C. OPERATING CHARACTERISTICS VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. Symbol ILI ILO ICC1 ICC2 ISB VIL(4) VIH (4) Parameter Input Leakage Current Output Leakage Current Power Supply Current (Write) Power Supply Current (Read) Standby Current Input Low Voltage Input High Voltage Output Low Voltage ¯¯¯¯¯¯ (SDA, RESET) Output High Voltage (RESET) Test Conditions VIN = GND to VCC VIN = GND to VCC fSCL = 400 kHz VCC = 5.5 V fSCL = 400 kHz VCC = 5.5 V CAT1026 Vcc = 5.5 V, VIN = GND or VCC CAT1027 Min -2 -10 Typ Max 10 10 3 1 50 60 0.3 x VCC VCC + 0.5 0.4 Units µA µA mA mA µA V V V V -0.5 0.7 x VCC IOL = 3 mA VCC = 2.7 V IOH = -0.4 mA VCC = 2.7 V CAT102x-45 (VCC = 5.0 V) CAT102x-42 (VCC = 5.0 V) VCC - 0.75 4.50 4.25 3.00 2.85 2.55 1.00 15 1.2 1.25 VOL VOH 4.75 4.50 3.15 3.00 2.70 V VTH Reset Threshold CAT102x-30 (VCC = 3.3 V) CAT102x-28 (VCC = 3.3 V) CAT102x-25 (VCC = 3.0 V) VRVALID VRT(5) VREF Reset Output Valid VCC Voltage Reset Threshold Hysteresis Auxiliary Voltage Monitor Threshold V mV 1.3 VS Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) VIL min and VIH max are reference values only and are not tested. (5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. MD-3010 Rev. P 4 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 CAPACITANCE TA = 25ºC, f = 1.0 MHz, VCC = 5 V Symbol COUT CIN (1) (1) Test Output Capacitance Input Capacitance Test Conditions VOUT = 0 V VIN = 0 V Max 8 6 Units pF pF AC CHARACTERISTICS VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle(2) Symbol fSCL tSP tLOW tHIGH tR tF (1) (1) Parameter Clock Frequency Input Filter Spike Suppression (SDA, SCL) Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time (for a Repeated Start) Data Input Hold Time Data Input Setup Time Stop Condition Setup Time SCL Low to Data Out Valid Data Out Hold Time Time the Bus must be Free Before a New Transmission Can Start Write Cycle Time (Byte or Page) Min Max 400 100 Units kHz ns µs µs 1.3 0.6 300 300 0.6 0.6 0 100 0.6 900 50 1.3 5 ns ns µs µs ns ns µs ns ns µs ms tHD; STA tSU; STA tHD; DAT tSU; DAT tSU; STO tAA tDH tBUF (1) tWC(3) Notes: (1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (2) Test Conditions according to “AC Test Conditions” table. (3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 5 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS Symbol tPURST tRDP tGLITCH tWD tRPD2 Parameter Reset Timeout VTH to RESET Output Delay VCC Glitch Reject Pulse Width Watchdod Timeout VSENSE to VLOW Delay Test Conditions Note 2 Note 3 Note 4, 5 Note 1 1 Min 130 Typ 200 Max 270 5 30 Units ms µs ns s µs 1.0 1.6 2.1 5 Note 5 POWER-UP TIMING (6), (7) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Test Conditions Min Typ Max 270 270 Units ms ms AC TEST CONDITIONS Parameter Input Pulse Voltages Input Rise and Fall Times Input Reference Voltages Output Reference Voltages Output Load RELIABILITY CHARACTERISTICS Symbol NEND (6) Test Conditions 0.2 x VCC to 0.8 x VCC 10 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA; CL = 100 pF Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Max Units Cycles/Byte Years Volts mA TDR(6) VZAP(6) ILTH(6)(8) Notes: (1) Test Conditions according to “AC Test Conditions” table. (2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data 5) 0 < VSENSE - VCC, VLOW Output Reference Voltage and Load according to “AC Test Conditions” Table. (6) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (7) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. (8) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V. Doc. No. MD-3010 Rev. P 6 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 DEVICE OPERATION Reset Controller Description The CAT1026 and CAT1027 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET outputs will be active ¯¯¯¯¯¯ when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0 V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Capability ¯¯¯¯¯¯ The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that ¯¯¯¯¯¯ is, the RESET input will initiate a reset timeout after detecting a high to low transition. ¯¯¯¯¯¯ When RESET I/O is driven to the active state, the 200 ms timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. Monitoring Two Voltages The CAT1026 and CAT1027 feature a second voltage sensor, VSENSE, which drives the open drain VLOW output low whenever the input voltage is below 1.25 V. The auxiliary voltage monitor timing is shown in Figure 2. By using an external resistor divider the sense circuitry can be set to monitor a second supply in the system. The circuit shown in Figure 3 provides an externally adjustable threshold voltage, VTH_ADJ to monitor the auxiliary voltage. The low leakage current at VSENSE allows the use of large value resistors, to reduce the system power consumption. The VLOW output can be externally connected to the RESET output to generate a reset condition when either of the supplies is invalid. In other applications, VLOW signal can be used to interrupt the system controller for an impending power failure notification. Data Protection The CAT1026 and CAT1027 devices have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5 ms) before VCC reaches the minimum value of 2 V. In addition, to avoid data corruption due to the loss of power supply voltage during the memory internal write operation, the system controller should monitor the unregulated DC power. Using the second voltage sensor, VSENSE, to monitor an unregulated power supply, the CAT1026 and CAT1027 signals an impending power failure by setting VLOW low. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1027 device will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. CAT1027 is designed with the Watchdog timer feature on the WDI pin. If WDI does not toggle within 1.6 second intervals, the reset condition will be generated on reset output. The watchdog timer is cleared by any transition on monitored line. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 7 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 Figure 1. RESET Output Timing t GLITCH VTH V RVALID VCC t PURST t RPD t PURST t RPD RESE T RESE T Figure 2: Auxiliary Voltage Monitor Timing VREF VSENSE tRPD2 tRPD2 tRPD2 tRPD2 VLOW Figure 3: Auxiliary Voltage Monitor VCC VAUX CAT1026/27 Externally adjustable threshold R1 VTH-ADJ VSENSE R2 VLOW Power Fail Interrupt VTH-ADJ = VREF × R + R2 R1 + R2 = 1.25V × 1 R2 R2 Doc. No. MD-3010 Rev. P 8 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 EMBEDDED EEPROM OPERATION The CAT1026 and CAT1027 feature a 2-kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START CONDITION The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1026 and CAT1027 Figure 3. Bus Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR monitor the SDA and SCL lines and will not respond until this condition is met. STOP CONDITION A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT1026 and CAT1027 monitor the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1026 and CAT1027 then perform a Read or Write operation ¯¯ depending on the R/W bit. 2 Figure 4. Write Cycle Timing SC L SD A 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS Doc. No. MD-3010 Rev. P © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 9 CAT1026, CAT1027 ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1026 and CAT1027 respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT1026 and CAT1027 begin a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1026 and CAT1027 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 5. Start/Stop Timing WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information ¯¯ (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1026 and CAT1027 acknowledge once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. SDA SCL START BIT STOP BIT Figure 6. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 7: Slave Address Bits Default Configuration 1 0 1 0 0 0 0 R/W Doc. No. MD-3010 Rev. P 10 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 Page Write The CAT1026 and CAT1027 write up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1026 and CAT1027 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1026 and CAT1027 in a single write cycle. Figure 8. Byte Write Timing S T A R T S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS DATA S T O P P Figure 9: Page Write Timing S T A R T S A C K A C K A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS (n) DATA n DATA n+1 S T DATA n+15 O P P © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 11 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1026 and CAT1027 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. Figure 10. Immediate Address Read Timing S T A R T S A C K DATA N O A C K READ OPERATIONS The READ operation for the CAT1026 and CAT1027 is initiated in the same manner as the write operation with ¯¯ one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. BUS ACTIVIT Y: MASTER SDA LINE SLAVE ADDRESS S T O P P SCL 8 9 SDA 8TH BI T DATA OUT NO ACK STOP Doc. No. MD-3010 Rev. P 12 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 Immediate/Current Address Read The CAT1026 and CAT1027 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1026and CAT1027 receive its ¯¯ slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1026 and CAT1027 acknowledges, the Master device sends the START condition and the slave ¯¯ address again, this time with the R/W bit set to one. The CAT1026 and CAT1027 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1026 and CAT1027 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1026 and CAT1027 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1026 and CAT1027 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1026 and CAT1027 address bits so that the entire memory array can be read during one operation. Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K A C K SLAVE ADDRESS BYTE ADDRESS (n) S T A R T S A C K DATA n N O A C K SLAVE ADDRESS S T O P P Figure 12. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K Doc. No. MD-3010 Rev. P SLAVE ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x S T O P P © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 13 CAT1026, CAT1027 PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300 mils (L) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 b2 c D E e E1 eB PIN # 1 IDENTIFICATION D L TOP VIEW E A A2 A1 b2 L c e b eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. Doc. No. MD-3010 Rev. P 14 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 SOIC 8-Lead 150 mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0º 1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN # 1 IDENTIFICATION TOP VIEW D h A1 A θ c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 15 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 TSSOP 8-Lead (V) (1)(2) b SYMBOL MIN NOM MAX A A1 A2 b c E1 E 1.20 0.05 0.80 0.19 0.09 2.90 6.30 4.30 3.00 6.40 4.40 0.65 BSC 1.00 REF 0.50 0° 0.60 0.75 8° 0.90 0.15 1.05 0.30 0.20 3.10 6.50 4.50 D E E1 e L L1 θ1 e TOP VIEW D c A2 A θ1 A1 SIDE VIEW L1 END VIEW L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153 Doc. No. MD-3010 Rev. P 16 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 MSOP 8-Lead (Z) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b c D E E1 1.10 0.05 0.75 0.22 0.13 2.90 4.80 2.90 0.40 3.00 4.90 3.00 0.65 BSC 0.60 0.95 REF 0.25 BSC 0º 6º 0.80 0.10 0.85 0.15 0.95 0.38 0.23 3.10 5.00 3.10 E E1 e L L1 L2 θ TOP VIEW D A A2 DETAIL A A1 e SIDE VIEW b c END VIEW θ L2 L L1 DETAIL A Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 17 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 TDFN 8-Pad 3 x 3 mm (ZD4) (1)(2) D A e b L E E2 PIN#1 ID PIN#1 INDEX AREA A1 D2 TOP VIEW SIDE VIEW BOTTOM VIEW SYMBOL MIN NOM MAX A A1 A3 b D D2 E E2 e L 0.70 0.00 0.23 2.90 2.20 2.90 1.40 0.20 0.75 0.02 0.20 REF 0.30 3.00 — 3.00 — 0.65 TYP 0.30 0.80 0.05 A A3 A1 0.37 3.10 2.50 3.10 1.80 0.40 FRONT VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-229. Doc. No. MD-3010 Rev. P 18 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT1026, CAT1027 EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Company ID Device # Suffix 1026 W I Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 1026: 2k 1027: 2k Package L: PDIP W: SOIC Y: TSSOP Z: MSOP ZD4: TDFN 3 x 3 mm (5) Reset Threshold Voltage -45: 4.50 V – 4.75 V -42: 4.25 V – 4.50 V -30: 3.00 V – 3.15 V -28: 2.85 V – 3.00 V -25: 2.55 V – 2.70 V -30 – G T3 Tape & Reel T: Tape & Reel 3: 3,000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu ORDERING INFORMATION Orderable Part Number – CAT1026xx CAT1026LI-45-G CAT1026ZI-45-GT3 CAT1026LI-42-G CAT1026ZI-42-GT3 CAT1026LI-30-G CAT1026ZI-30-GT3 CAT1026LI-28-G CAT1026ZI-28-GT3 CAT1026LI-25-G CAT1026ZI-25-GT3 CAT1026WI-45-GT3 CAT1026ZD4I-45T3* CAT1026WI-42-GT3 CAT1026ZD4I-42T3* CAT1026WI-30-GT3 CAT1026ZD4I-30T3* CAT1026WI-28-GT3 CAT1026ZD4I-28T3* CAT1026WI-25-GT3 CAT1026ZD4I-25T3* CAT1026YI-45-GT3 CAT1026YI-42-GT3 CAT1026YI-30-GT3 CAT1026YI-28-GT3 CAT1026YI-25-GT3 Orderable Part Number – CAT1027xx CAT1027LI-45-G CAT1027ZI-45-GT3 CAT1027LI-42-G CAT1027ZI-42-GT3 CAT1027LI-30-G CAT1027ZI-30-GT3 CAT1027LI-28-G CAT1027ZI-28-GT3 CAT1027LI-25-G CAT1027ZI-25-GT3 CAT1027WI-45-GT3 CAT1027ZD4I-45T3* CAT1027WI-42-GT3 CAT1027ZD4I-42T3* CAT1027WI-30-GT3 CAT1027ZD4I-30T3* CAT1027WI-28-GT3 CAT1027ZD4I-28T3* CAT1027WI-25-GT3 CAT1027ZD4I-25T3* CAT1027YI-45-GT3 CAT1027YI-42-GT3 CAT1027YI-30-GT3 CAT1027YI-28-GT3 CAT1027YI-25-GT3 * there is only * Part number is not exactly the same as the “Example of Ordering Information” shown above. For part numbers marked with one hyphen in the orderable part number, which is placed before the “Reset Threshold Voltage”. Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT1026WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15 V, NiPdAu, Tape & Reel, 3,000/Reel). (4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. (5) TDFN not available in NiPdAu (–G) version. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 19 Doc. No. MD-3010 Rev. P CAT1026, CAT1027 REVISION HISTORY Date 9/25/2003 11/07/2003 4/12/2004 11/01/2004 11/04/2004 11/11/2004 02/02/2007 11/28/2007 7-Nov-08 05-Mar-09 14-Jul-09 Rev. F G H I J K L M N O P Reason Added Green Package logo. Updated DC Operating Characteristic notes. Updated Reliability Characteristics notes Eliminated Automotive temperature range. Updated Ordering Information with “Green” package marking codes Eliminated data sheet designation. Updated Reel Ordering Information Changed SOIC package designators. Eliminated 8-pad TDFN (3 x 4.9 mm) package. Added package outlines Update Pin Configuration Update Feature Update Description Update DC Operating Characteristic Update AC Characteristics Update Example of Ordering Information Update Package Outline Drawings Update Example of Ordering Information Add “MD-“ to document number Change logo and fine print to ON Semiconductor Update Ordering Information (Remove 2,000/Reel) Update Ordering Information table ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-3010, Rev. P 20 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice