CAT1163WI-30-GT3

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. CAT1163 Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) http://onsemi.com Description The CAT1163 is a complete memory and supervisory solution for microcontroller−based systems. A serial EEPROM memory (16K) with hardware memory write protection, a system power supervisor with brown out protection and a watchdog timer are integrated together in low power CMOS technology. Memory interface is via an I2C bus. The 1.6−second watchdog circuit returns a system to a known good state if a software or hardware glitch halts or “hangs” the system. The CAT1163 watchdog monitors the WDI input pin. The power supply monitor and reset circuit protects memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, a reset pin can be used as a debounced input for pushbutton manual reset capability. The CAT1163 memory features a 16−byte page. In addition, hardware data protection is provided by a write protect pin WP and by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include an 8−pin DIP and a surface mount, 8−pin SO package. Features • • • • • • • • • November, 2011 − Rev. 10 SOIC−8 CASE 751BD PIN CONFIGURATION PDIP 8 Lead SOIC 8 Lead WDI 1 RESET 2 WP 3 GND 4 CAT1163 8 VCC 7 RESET 6 SCL 5 SDA PIN FUNCTIONS Pin Name Function WDI Watchdog Timer Input RESET Active Low Reset I/O WP Write Protect GND Ground SDA Serial Data/Address SCL Clock Input RESET Watchdog Timer Input (WDI) 400 kHz I2C Bus Compatible 2.7 V to 6.0 V Operation Low Power CMOS Technology 16−Byte Page Write Buffer Built−in Inadvertent Write Protection ♦ VCC Lock Out ♦ Write Protection Pin, WP Active High or Low Reset ♦ Precision Power Supply Voltage Monitor ♦ 5 V, 3.3 V and 3 V Systems ♦ Five Threshold Voltage Options 1,000,000 Program/Erase Cycles Manual Reset © Semiconductor Components Industries, LLC, 2011 PDIP−8 CASE 646AA VCC Active High Reset I/O Power Supply ORDERING INFORMATION For Ordering Information details, see page 10. • • • • 1 100 Year Data Retention 8−Pin DIP or 8−Pin SOIC Commercial and Industrial Temperature Ranges These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Publication Order Number: CAT1163/D CAT1163 Table 1. RESET THRESHOLD OPTION Part Dash Number Minimum Threshold Maximum Threshold −45 4.50 4.75 −42 4.25 4.50 −30 3.00 3.15 −28 2.85 3.00 −25 2.55 2.70 BLOCK DIAGRAM EXTERNAL LOAD SENSEAMPS SHIFT REGISTERS D OUT ACK V CC GND SDA WORDADDRESS BUFFERS COLUMN DECODERS START/STOP LOGIC XDEC WP 16K EEPROM CONTROL LOGIC DATA IN STORAGE HIGHVOLTAGE/ TIMING CONTROL RESET Controller WATCHDOG Precision Vcc Monitor WDI RESET RESET http://onsemi.com 2 STATE COUNTERS SLAVE ADDRESS COMPARATORS SCL CAT1163 SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Ratings Units Temperature Under Bias Parameters –55 to +125 °C Storage Temperature –65 to +150 °C −2.0 to VCC + 2.0 V −2.0 to 7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 seconds) 300 °C Output Short Circuit Current (Note 2) 100 mA Voltage on any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 3. RELIABILITY CHARACTERISTICS Symbol Reference Test Method Min Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 3) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 3) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts JEDEC Standard 17 100 mA NEND (Note 3) ILTH (Notes 3 & 4) Parameter Latch−Up Max Units 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. Table 4. D.C. OPERATING CHARACTERISTICS VCC = 2.7 V to 6.0 V, unless otherwise specified. Parameter Symbol Test Conditions Min Typ Max Units ICC Power Supply Current fSCL = 100 kHz 3 mA ISB Standby Current VCC = 3.3 V 40 mA VCC = 5 V 50 mA ILI Input Leakage Current VIN = GND or VCC 2 mA ILO Output Leakage Current VIN = GND or VCC 10 mA VIL Input Low Voltage −1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V 0.4 V VOL1 Output Low Voltage (SDA) IOL = 3 mA, VCC = 3.0 V Table 5. CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5 V Max Units CI/O (Note 3) Input/Output Capacitance (SDA) Test VI/O = 0 V 8 pF CIN (Note 3) Input Capacitance (SCL) VIN = 0 V 6 pF Symbol Test Conditions http://onsemi.com 3 CAT1163 Table 6. AC CHARACTERISTICS VCC = 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF. VCC = 2.7 V − 6 V FSCL T1 (Note 1) tAA tBUF (Note 1) tHD; STA Min Parameter Symbol Max VCC = 4.5 V − 5.5 V Min Max Units Clock Frequency 100 400 kHz Noise Suppression Time Constant at SCL, SDA Inputs 200 200 ns SCL Low to SDA Data Out and ACK Out 3.5 1 ms Time the Bus must be Free Before a New Transmission Can Start Start Condition Hold Time 4.7 1.2 ms 4 0.6 ms tLOW Clock Low Period 4.7 1.2 ms tHIGH Clock High Period 4 0.6 ms 4.7 0.6 ms 0 ns tSU; STA Start Condition Setup Time (for a Repeated Start Condition) tHD; DAT Data in Hold Time 0 tSU; DAT Data in Setup Time 50 50 ns tR (Note 1) SDA and SCL Rise Time 1 0.3 ms tF (Note 1) SDA and SCL Fall Time 300 300 ns tSU; STO tDH Stop Condition Setup Time Data Out Hold Time 4 0.6 ms 100 100 ns 1. This parameter is tested initially and after a design or process change that affects the parameter. Table 7. POWER−UP TIMING (Notes 1 and 2) Symbol Parameter Min Typ Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms Max Units 10 ms 2. tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated. Table 8. WRITE CYCLE LIMITS Symbol tWR Parameter Min Typ Write Cycle Time The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Table 9. RESET CIRCUIT CHARACTERISTICS Symbol tGLITCH VRT Parameter Reset Threshold Hysteresis VOHRS Reset Output High Voltage Units 100 ns mV 0.4 VCC − 0.75 4.50 4.75 Reset Threshold (VCC = 5 V), (CAT1163−42) 4.25 4.50 Reset Threshold (VCC = 3.3 V), (CAT1163−30) 3.00 3.15 Reset Threshold (VCC = 3.3 V), (CAT1163−28) 2.85 3.00 Reset Threshold (VCC = 3 V), (CAT1163−25) 2.55 2.70 Power−Up Reset Timeout 130 270 Watchdog Period tRPD VTH to RESET Output Delay 1.6 1 http://onsemi.com 4 V ms s 5 RESET Output Valid V V Reset Threshold (VCC = 5 V), (CAT1163−45) tWP VRVALID Max 15 Reset Output Low Voltage (IOLRS = 1 mA) tPURST Typ Glitch Reject Pulse Width VOLRS VTH Min ms V CAT1163 PIN DESCRIPTION WDI: WATCHDOG INPUT If there is no transition on the WDI for more than 1.6 seconds, the watchdog timer times out. WP: WRITE PROTECT If the pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the pin is tied to GND or left floating normal read/write operations are allowed to the device. RESET/RESET: RESET I/O These are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition. The RESET pin must be connected through a pulldown resistor, and the RESET pin must be connected through a pull−up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs. SCL: Serial Clock Serial clock input. DEVICE OPERATION Reset Controller Description RESET input in the CAT1163 will initiate a reset timeout after detecting a low to high transition and the RESET input in the CAT1163 will initiate a reset timeout after detecting a high to low transition. The CAT1163 precision RESET controller ensures correct system operation during brownout and power up/down conditions. It is configured with open drain RESET outputs. During power−up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power−down, the RESET outputs will be active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is > 1.0 V (VRVALID). The RESET pins are I/Os; therefore, the CAT1163 can act as a signal conditioning circuit for an externally applied manual reset. The inputs are edge triggered; that is, the Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1163 will respond with a reset signal after a time−out interval of 1.6 seconds for a lack of activity. The CAT1163 is designed with the Watchdog Timer feature on the WDI input. If the microcontroller does not toggle the WDI input pin within 1.6 seconds, the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watchdog Timer is cleared by any transition on WDI. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. t GLITCH VTH VRVALID VCC t PURST t RPD t PURST RESET t RPD RESET Figure 1. RESET Output Timing http://onsemi.com 5 CAT1163 Hardware Data Protection down) VTH or until VCC reaches the reset threshold (power up) VTH. Any attempt to access the internal EEPROM is not recognized and an ACK will not be sent on the SDA line when RESET or RESET is active. The CAT1163 is designed with the following hardware data protection features to provide a high degree of data integrity. 1. The CAT1163 features a WP pin. When the WP pin is tied high the entire memory array becomes write protected (read only). 2. The VCC sense provides write protection when VCC falls below the reset threshold value (VTH). The VCC lock out inhibits writes to the serial EEPROM whenever VCC falls below (power Reset Threshold Voltage The CAT1163 is offered with five reset threshold voltage ranges. They are 4.50 ÷ 4.75 V, 4.25 ÷ 4.50 V, 3.00 ÷ 3.15 V, 2.85 ÷ 3.00 V and 2.55 ÷ 2.70 V. tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Bus Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION START CONDITION Figure 3. Write Cycle Timing SDA SCL START BIT STOP BIT Figure 4. Start/Stop Timing http://onsemi.com 6 ADDRESS CAT1163 FUCTIONAL DESCRIPTION The CAT1163 supports the I2C Bus data transmission protocol. This Inter−Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8−bit slave address are fixed as 1010. The next three bits (Figure 6) define memory addressing. For the CAT1163 the three bits define higher order bits. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT1163 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1163 then performs a Read or Write operation depending on the R/W bit. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1163 monitors the SDA and SCL lines and will not respond until this condition is met. SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 5. Acknowledge Timing CAT1163 1 0 1 0 a10 a9 a8 R/W Note: a8, a9 and a10 correspond to the address of the memory array address word. Figure 6. Slave Address Bits Acknowledge responds with an acknowledge after receiving each 8−bit byte. When the CAT1163 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1163 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1163 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it http://onsemi.com 7 CAT1163 WRITE OPERATIONS Byte Write Page Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8−bit address that is to be written into the address pointers of the CAT1163. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1163 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non−volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. The CAT1163 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1163 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1163 in a single write cycle. BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 7. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T BYTE ADDRESS (n) SLAVE ADDRESS DATA n S T O DATA n+15 P DATA n+1 S P A C K A C K A C K A C K A C K Figure 8. Page Write Timing Acknowledge Polling condition followed by the slave address for a write operation. If the CAT1163 is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT1163 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1163 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. http://onsemi.com 8 CAT1163 READ OPERATIONS The READ operation for the CAT1163 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N = E (where = 2047 for the CAT1163) then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT1163 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8−bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Immediate/Current Address Read The CAT1163’s address counter contains the address of the last byte accessed, incremented by one. In other words, BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS P S A C K DATA N O A C K SCL 8 9 SDA8TH BIT DATA OUT NO ACK STOP Figure 9. Immediate Address Read Timing Selective/Random Read memory array can be read during one operation. If more than E (where E=2047 for the CAT1163) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1163 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1163 then responds with its acknowledge and sends the 8−bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Manual Reset Operation The CAT116x RESET or RESET pin can also be used as a manual reset input. Only the “active” edge of the manual reset input is internally sensed. The positive edge is sensed if RESET is used as a manual reset input and the negative edge is sensed if RESET is used as a manual reset input. An internal counter starts a 200 ms count. During this time, the complementary reset output will be kept in the active state. If the manual reset input is forced active for more than 200 ms, the complementary reset output will switch back to the non active state after the 200 ms expired, regardless for how long the manual reset input is forced active. The embedded EEPROM is disabled as long as a reset condition is maintained on any RESET pin. If the external forced RESET/RESET is longer than internal controlled time−out period, tPURST, the memory will not respond with an acknowledge for any access as long as the manual reset input is active. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1163 sends the inital 8−bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1163 will continue to output an 8−bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1163 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1163 address bits so that the entire http://onsemi.com 9 CAT1163 BUS ACTIVITY: MASTER SDA LINE S T A R T S T A R T BYTE ADDRESS (n) SLAVE ADDRESS S T O P SLAVE ADDRESS S S P A C K A C K A C K DATA n A C K Figure 10. Selective Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 N O DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K A C K Figure 11. Sequential Read Timing ORDERING INFORMATION Orderable Part Numbers − CAT1163 Series (See Notes 1 − 4) Device Reset Threshold Voltage CAT1163LI−45−G 4.50 V − 4.75 V CAT1163LI−42−G 4.25 V − 4.50 V CAT1163LI−30−G 3.00 V − 3.15 V CAT1163LI−28−G 2.85 V − 3.00 V CAT1163LI−25−G 2.55 V − 2.70 V CAT1163WI−45−GT3 4.50 V − 4.75 V CAT1163WI−42−GT3 4.25 V − 4.50 V CAT1163WI−30−GT3 3.00 V − 3.15 V CAT1163WI−28−GT3 2.85 V − 3.00 V CAT1163WI−25−GT3 2.55 V − 2.70 V Package−Pins Shipping PDIP−8 3000 Tape & Reel SOIC−8 1. All packages are RoHS−compliant (Lead−free, Halogen−free). 2. The standard lead finish is NiPdAu. 3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 4. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com http://onsemi.com 10 N O CAT1163 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 11 CAT1163 SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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