CAT1232LP, CAT1832
5 V and 3.3 V Supply Monitor, Watchdog Timer,
Manual Reset, with Active High & Low Resets
FEATURES
DESCRIPTION
Selectable reset voltage tolerance
The CAT1232LP and CAT1832 microprocessor
supervisors can halt and restart a “hung-up” or
“stalled” microprocessor, restart a microprocessor
after a power failure, and debounce a manual/pushbutton microprocessor reset switch. The devices are
drop in replacements for the Maxim/Dallas
Semiconductor DS1232LP and DS1832 supervisors
— CAT1232LP for 5 V supply
— CAT1832 for 3.3 V supply
Selectable watchdog period:
150 ms, 600 ms or 1.2 s
Two reset outputs
— Active high, push-pull reset output
— Active low, open-drain reset output
(CAT1232LP)
— Active low, push-pull reset output (CAT1832)
Debounced manual push-button reset
Compact SOIC and MSOP packages
Precision reference and comparator circuits monitor
the 5 V or 3.3 V system power supply voltage, VCC.
During power-up or when the power supply falls
outside selectable tolerance limits, both the RESET
¯¯¯¯¯¯ become active. After the power supply
and RESET
voltage rises above the RESET threshold voltage, the
reset signals remain active for a minimum of 250ms,
allowing the power supply and system processor to
stabilize. The trip-point tolerance input, TOL, selects
the trip level tolerance to be either 5% or 10% for the
CAT1232LP 5 V supply and 10% or 20% for the
CAT1832 3.3 V supply.
For Ordering Information details, see page 11.
APPLICATIONS
Microprocessor Systems
Each device has a push-pull, active HIGH reset
output. The CAT1232LP also has an open drain,
active LOW reset output while the CAT1832 also has
a push-pull, active LOW reset output.
Portable Equipment
Controllers
Single Board Computers
Telecommunications
A debounced manual reset input activates the reset
outputs and holds them active for a minimum period of
250 ms after being released.
FUNCTIONAL DIAGRAM
Also included is a watchdog timer to reset a
microprocessor that has stopped due to a software or
hardware failure. Three watchdog time-out periods are
¯¯ input
selectable: 150 ms, 600 ms and 1.2 s. If the ST
is not strobed low before the watchdog time out period
expires, the reset signals become active for a
minimum of 250 ms.
Instrumentations
VCC
TOL
Tolerance Selection
+
Reference
–
RESET
(CAT1232LP)
VCC
40kΩ
PBRST
RESET
Push Button Debounce
TD
Watchdog Timebase Selection
ST
Watchdog Transition Detector
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
Reset &
Watchdog Timer
1
RESET
(CAT1832)
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
PIN CONFIGURATION
SOIC 16 Lead
SOIC 8 Lead
MSOP 8 Lead
PDIP 8 Lead
¯¯¯¯¯¯
PBRST
1
8
VCC
TD
2
7
¯¯
ST
TOL
3
6
¯¯¯¯¯¯
RESET
GND
4
5
RESET
CAT
NC
1
16
NC
¯¯¯¯¯¯
PBRST
2
15
VCC
NC
3
14
NC
TD
4
13
¯¯
ST
NC
5
12
NC
TOL
6
11
¯¯¯¯¯¯
RESET
NC
7
10
NC
GND
8
9
RESET
CAT
PIN DESCRIPTION
Pin Number
8-Lead
Package
Pin Number
16-Lead
Package
Name
1
2
¯¯¯¯¯¯
PBRST
Function
Debounced manual pushbutton reset input
Watchdog typical time delay selection:
a) tTD = 150 ms for TD = GND
b) tTD = 600 ms for TD = Open
c) tTD = 1200 ms for TD = VCC
2
4
TD
3
6
TOL
CAT1232LP TOL selects 5% (TOL = GND) or 10% (TOL = VCC) trip
point tolerance. CAT1832 TOL selects 10% (TOL = GND) or 20%
TOL = VCC) trip point tolerance.
4
8
GND
Ground
5
9
RESET
Active HIGH reset output. RESET is active
1. If VCC falls below the reset voltage trip point
¯¯¯¯¯¯ is low
2. If PBRST
¯¯ is not strobed low before the timeout period set by TD expires.
3. If ST
4. During power-up.
6
11
RESET
Active LOW reset output. (See RESET)
7
13
¯¯
ST
Strobe Input
8
15
1, 3. 5, 7, 10,
12, 14, 16
VCC
Power Supply
NC
No internal connection
ABSOLUTE MAXIMUM RATINGS (*)
Parameters
Voltage on VCC
¯¯ and TD
Voltage on ST
¯¯¯¯¯¯,
Voltage on PBRST
¯¯¯¯¯¯and RESET
RESET
Ratings
Units
Parameters
-0.5 to 7.0
V
Maximum Junction Temperature
-0.5 to VCC + 0.5
V
Storage Temperature Range
-0.5 to VCC + 0.5
V
Lead Soldering Temperature (10s)
Operating Temperature Range
Ratings
Units
125
ºC
-65 to +150
ºC
300
ºC
-40 to +85
ºC
Note:
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Doc. No. MD-3018 Rev. F
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1232LP, CAT1832
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, 1.0 V - VCC - 5.5 V and over the operating temperature range of -40ºC to +85ºC.
All voltages are referenced to ground.
Symbol Parameter
Conditions
Min
Typ
Units
5.5
V
VCC
Supply Voltage
ICC1
Supply Current
VIH
¯¯¯¯¯¯ Input High
ST and PBRST
Level
VIL
¯¯¯¯¯¯ Input Low
ST and PBRST
Level
VCC = 5.5 V, CAT1232LP
VCCTP
VCC Trip Point (TOL = GND)
CAT1232LP
4.50
4.62
4.74
V
VCCTP
VCC Trip Point (TOL = VCC)
CAT1232LP
4.25
4.37
4.49
V
VCCTP
VCC Trip Point (TOL = GND)
CAT1832
2.80
2.88
2.97
V
VCCTP
VCC Trip Point (TOL = VCC)
CAT1832
2.47
2.55
2.64
V
tTD
Watchdog Time-Out Period
TD = GND
62.5
150
250
ms
tTD
Watchdog Time-Out Period
TD = VCC
500
1200
2000
ms
tTD
Watchdog Time-Out Period
TD floating
250
600
1000
ms
VCC -0.5 V
VCC -0.1 V
V
-350
µA
VOH
Output Voltage
1.0
Max
VCC = 5.5 V, CAT1232LP
35
50
VCC = 3.6 V, CAT1832
20
35
(5)
2
(6)
VCC - 0.4 V
-0.3
I = -500 µA
(3)
0.5
(2)
Output Current
Output = 2.4 V
IOL
Output Current
Output = 0.4 V
IIL
Input Leakage
(1)
-1.0
RPU
Internal Pull-Up Resistor
(1)
32
CIN
tPB
tRST
tST
tRPD
tF
tPDLY
tRPU
tR
0.8
VCC = 3.6 V, CAT1832
IOH
COUT
VCC + 0.3 V
10
µA
V
V
mA
1.0
µA
55
kΩ
Input Capacitance
5
pF
Output Capacitance
¯¯¯¯¯¯ Manual Reset
PBRST
Minimum Low Time
Reset Active Time
7
pF
¯¯ Pulse Width
ST
VCC Fail Detect to RESET or
¯¯¯¯¯¯
RESET
¯¯¯¯¯¯ = VIL
PBRST
20
250
(4)
40
ms
600
1000
20
ns
5
VCC Slew Rate
¯¯¯¯¯¯ Stable LOW to RESET
PBRST
¯¯¯¯¯¯ Active
and RESET
VCC Detect to RESET or
tRISE = 5 µs
¯¯¯¯¯¯ Inactive
RESET
VCC Slew Rate
4.25 V to 4.75 V
8
20
250
0
ms
µs
µs
600
20
ms
1000
ms
ns
Notes:
¯¯¯¯¯¯ is internally pulled HIGH to VCC through a nominal 40 kΩ resistor (RPU).
(1) PBRST
¯¯¯¯¯¯ is an open drain output on the CAT1232LP.
(2) RESET
(3) RESET remains within 0.5 V of VCC on power-down until VCC falls below 2 V. RESET remains within 0.5 V of ground on power-down until
VCC falls below 2.0 V.
¯¯ must be
(4) Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST
strobed.
(5) Measured with VCC ≥ 2.7 V.
(6) Measured with VCC < 2.7 V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
TYPICAL CHARACTERISTICS
For the CAT1232LP, VCC = 5 V and TAMB = 25ºC unless otherwise stated.
Threshold Voltage vs. Temperature (5% TOL)
4.450
4.630
4.445
4.625
THRESHOLD VOLTAGE (V)
THRESHOLD VOLTAGE (V)
Threshold Voltage vs. Temperature (10% TOL)
TOL = Vcc (10%)
4.440
4.435
4.430
-50
0
50
TOL = GND (5%)
4.620
4.615
4.610
100
-50
TEMPERATURE (°C)
800
RESET ACTIVE TIME (ms)
Vcc = 5.5V
SUPPLY CURRENT (mA)
100
Reset Active Time vs. Temperature
40
30
Vcc = 4.5V
20
10
0
50
TD = open
700
Vcc = 5.5V
600
500
Vcc = 4.5V
400
300
-50
100
TEMPERATURE (°C)
0
50
100
TEMPERATURE (°C)
Reset Active Time Waveform
Doc. No. MD-3018 Rev. F
50
TEMPERATURE (ºC)
Supply Current vs. Temperature
0
-50
0
Transient Response
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1232LP, CAT1832
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
¯¯¯¯¯¯ is an active LOW signal. It is developed with
RESET
an open drain driver in the CAT1232LP. A pull-up
resistor is required, typical values are 10 kΩ to 50 kΩ.
The CAT1832 uses a CMOS push-pull output stage
¯¯¯¯¯¯.
for the RESET
Tolerance
Select
Voltage
RESET is an active High signal developed by a
CMOS push-pull output stage and is the logical
¯¯¯¯¯¯.
opposite to RESET
Trip Point Tolerance Selection
The TOL input is used to select the VCC trip point
threshold. This selection is made connecting the
TOL input to ground or VCC. Connecting TOL to
Ground makes the VCC trip threshold 4.62 V for the
CAT1232LP and 2.88 V for the CAT1832.
Min
Nominal
Max
CAT1232LP
TOL = VCC
10 %
4.25
4.37
4.49
CAT1232LP
TOL = GND
5%
4.50
4.62
4.74
CAT1832
TOL = VCC
20 %
2.47
2.55
2.64
CAT1832
TOL = GND
10 %
2.80
2.88
2.97
Manual Reset Operation
¯¯¯¯¯¯, allows the user to issue
Push-button input, PBRST
reset signals. The pushbutton input is debounced and
is pulled high through an internal 40 kΩ resistor.
Connecting TOL to VCC makes the VCC trip threshold
4.37 V for the CAT1232LP and 2.55 V for the
CAT1832.
¯¯¯¯¯¯ is held low for the minimum time of
When PBRST
20 ms, both resets become active and remain active
for a minimum time period of 250 ms after PBRST
returns high.
After VCC has risen above the trip point set by TOL,
¯¯¯¯¯¯remain active for a minimum time
RESET and RESET
period of 250 ms.
¯¯¯¯¯¯
No external pull-up resistor is required, since PBRST
is pulled high by an internal 40 kΩ resistor.
On power-down, once VCC falls below the reset
threshold the RESET outputs will remain active and
are guaranteed valid down to a VCC level of 1.0 V.
¯¯¯¯¯¯ can be driven from a TTL or CMOS logic line
PBRST
or short-ed to ground with a mechanical switch.
Figure 2. Timing Diagram: Power Down
Figure 1. Timing Diagram: Power Up
VCC
tR
VCCTP(MAX)
VCCTP(MIN)
VCC
VCCTP
tRPU
Trip Point Voltage (V)
Trip Point
Tolerance
RESET
tF
VCCTP(MAX)
VCCTP
VCCTP(MIN)
tRPD
RESET
VOH
VOL
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
RESET
RESET
5
VOH
VOL
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
¯¯ INPUT
WATCHDOG TIMER AND ST
A watchdog timer stops and restarts a microprocessor
that has stopped proper operation or become “hung”.
The watchdog performs this function by monitoring the
¯¯ input. After the reset outputs go inactive the ST
¯¯
ST
input must be strobed with a high-to-low signal
transition prior to the minimum watchdog timeout
¯¯ input is not strobed with a
period. However if the ST
high-to-low signal transition prior to a watchdog
timeout the reset outputs will become active for TRST
reseting and restarting the microprocessor. Once the
resets return to the inactive state the watchdog timer
restarts the process.
Watchdog Time-out Period (ms)
TD Voltage
Level
Min
Nominal
Max
GND
62.5
150
250
Floating
250
600
1000
VCC
500
1200
2000
3.3V
CAT1832
1
2
The TD input allows the user to select from three
predetermined watchdog timeout periods. Always use
the minimum timeout period to determine the required
¯¯ high-to-low transitions and the
frequency of ST
maximum to determine the time prior to the reset
¯¯ pulse widths must be
outputs becoming active. ST
20 ns or greater.
3
4
PBRST
TD
8
VCC
7
ST
TOL
RESET
GND
RESET
I/O
6
5
µP
RESET
Figure 4. CAT1832 Application Circuit:
Pushbutton Reset
The watchdog timer cannot be disabled. It must be
strobed with a high-to-low signal transition to avoid a
watchdog timeout and subsequent reset.
5V
CAT1232LP
1
2
3
4
PBRST
TD
TOL
GND
VCC
ST
RESET
RESET
8
MREQ
7
10k
µP
6
RESET
5
Decoder
Address Bus
Figure 5. CAT1232LP Application Circuit: Watchdog Timer
tPB
PBRST
tPDLY
Valid
Strobe
ST
VIH
VIL
RESET
tRST
RESET
tTD
(Min)
tTD
(Min)
RESET
VOH
VOL
Note: ST is ignored whenever a reset is active
Figure 7. Timing Diagram: Strobe Input
Figure 6. Timing Diagram: Pushbutton Reset
Doc. No. MD-3018 Rev. F
Invalid
Strobe
tST
tRST
RESET
Valid
Strobe
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1232LP, CAT1832
PACKAGE OUTLINE DRAWINGS
SOIC 16-Lead 300 mils (W)(1)(2)
D
SYMBOL
E1 E
MIN
NOM
2.49
MAX
A
2.36
A1
0.10
b
0.33
0.41
c
0.18
0.23
0.28
D
10.08
10.31
10.49
E
10.01
10.31
10.64
E1
7.39
7.49
7.59
e
2.64
0.30
0.51
1.27 BSC
h
0.25
L
0.38
θ
0º
0.75
0.81
1.27
8º
PIN #1 IDENTIFICATION
TOP VIEW
h
A
b
e
c
θ
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-013.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
PDIP 8-Lead 300mils (L)(1)(2)
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
4.95
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
E1
6.10
eB
7.87
L
2.92
6.35
7.11
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
Doc. No. MD-3018 Rev. F
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1232LP, CAT1832
MSOP 8-Lead (Z) (1)(2)
SYMBOL
MIN
NOM
MAX
A
E
E1
1.10
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
c
0.13
D
2.90
0.38
0.23
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
e
L
0.65 BSC
0.40
0.60
L1
L2
θ
0.80
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
SOIC 8-Lead 150mils (V) (1)(2)
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
e
PIN # 1
IDENTIFICATION
NOM
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Doc. No. MD-3018 Rev. F
10
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1232LP, CAT1832
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
1232LP
V
Company ID
Product Number
1232LP
1832
ORDERING PART NUMBER
– G
T3
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Package
L: PDIP
V: SOIC 8-Lead
W: SOIC 16-Lead (5)
Z: MSOP
Tape & Reel
T: Tape & Reel
2: 2,000/Reel
3: 3,000/Reel
Package
Parts per Tube
Parts Per Reel
Reel Size (inch)
CAT1232LPL-G
8-lead, PDIP
50
—
—
CAT1232LPV-GT3
8-lead, SOIC
—
3,000
13
CAT1232LPZ-GT3
8-lead, MSOP
—
3,000
13
CAT1232LPW-T2
16-lead, SOIC
—
2,000
13
CAT1832L-G
8-lead, PDIP
50
—
—
CAT1832V-GT3
8-lead, SOIC
—
3,000
13
CAT1832Z-GT3
8-lead, MSOP
—
3,000
13
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT1232LPV-GT3 (SOIC 8-Lead, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
(5) The SOIC 16-Lead package is only available in Matte-Tin finish.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-3018 Rev. F
CAT1232LP, CAT1832
REVISION HISTORY
Date
Rev.
Description
13-Jun-05
00
Initial Issue
26-Jul-05
0A
Update Electrical Characteristics
Add Typical Characteristics
37-Mar-06
0B
Update Document Title
Update Ordering Information
27-Nov-06
0C
13-Nov-07
D
06-Nov-08
E
09-Mar-09
F
Add Ordering Information detail to page 1
Update Sample of Ordering Information
Update Package Outline Drawings
Update Example of Ordering Information
Change document number from 25088, Rev. OC
Change logo and fine print to ON Semiconductor
Update Example of Ordering Information
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Doc. No. MD-3018 Rev. F
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center:
Phone: 81-3-5773-3850
12
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
工商网监
湘ICP备2023018690号
