CAT24AA01TDI-GT10

CAT24AA01, CAT24AA02 1-Kb and 2-Kb I2C CMOS Serial EEPROM Description The CAT24AA01/24AA02 are 1−Kb and 2−Kb CMOS Serial EEPROM devices internally organized as 128x8/256x8 bits. They feature a 16−byte page write buffer and support both the Standard (100 kHz) and the Fast (400 kHz) I2C protocols. In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02 have no external address pins, and are therefore suitable in applications that require a single CAT24AA01/02 on the I 2C bus. Features http://onsemi.com • • • • • • • • • • Supports Standard and Fast I2C Protocol 1.7 V to 5.5 V Supply Voltage Range 16−Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VCC SOIC−8 W SUFFIX CASE 751BD TSOT−23 TB SUFFIX CASE 419AE PIN CONFIGURATIONS SOIC NC NC NC VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA (Top View) TSOT−23 SCL 1 2 3 4 VCC 5 WP SCL CAT24AA01 CAT24AA02 WP SDA VSS SDA (Top View) PIN FUNCTION VSS Figure 1. Functional Symbol Pin Name SDA SCL WP VCC VSS NC Function Serial Data/Address Clock Input Write Protect Power Supply Ground No Connect ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 3 1 Publication Order Number: CAT24AA01/D CAT24AA01, CAT24AA02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Ratings −65 to +150 −0.5 to +6.5 Units °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. REABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program/Erase Cycles Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode @ 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.) Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read, fSCL = 400 kHz Write All I/O Pins at GND or VCC Pin at GND or VCC −0.5 VCC x 0.7 Min Max 0.5 1 1 1 VCC x 0.3 VCC + 0.5 0.4 0.2 Units mA mA mA mA V V V V Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.) Symbol CIN (Note 2) CIN (Note 2) IWP (Note 4) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current VIN = 0 V VIN = 0 V VIN < VIH VIN > VIH Conditions Max 8 6 100 1 Units pF pF mA 4. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. http://onsemi.com 2 CAT24AA01, CAT24AA02 Table 5. A.C. CHARACTERISTICS (Note 5) (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.) Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (Note 6) tSU:STO tBUF tAA tDH Ti (Note 6) tSU:WP tHD:WP tWR tPU (Notes 6, 7) 5. 6. 7. Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power−up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 4 4.7 3.5 100 100 4 4.7 4 4.7 0 250 1000 300 0.6 1.3 0.9 Parameter Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 Min Fast Max 400 Units kHz ms ms ms ms ns ns ns ns ms ms ms ns ns ms ms ms ms Test conditions according to “A.C. Test Conditions” table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC ≤ 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF http://onsemi.com 3 CAT24AA01, CAT24AA02 Power−On Reset (POR) Each CAT24AA01/02 incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR behavior protects the device against brown−out failure, following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of SCL. WP: When the Write Protect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LOW internally. Functional Description The CAT24AA01/02 supports the Inter−Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24AA01/02 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2−wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull−up resistors. The Master provides the clock to the SCL line, and the Master and Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by releasing it HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). A START is generated by a HIGH to LOW transition, while a STOP is generated by a LOW to HIGH transition. The START acts like a wake−up call. Absent a START, no Slave will respond to the Master. The STOP completes all commands. START/STOP Condition Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8−bit Slave address (Figure 3). The four most significant bits of the Slave address are 1010 (Ah). For the CAT24AA01/02 the next three bits must be 000. The last bit, R/W, instructs the Slave to either provide (1) or accept (0) data, i.e. it signals a Read (1) or a Write (0) request. Acknowledge During the 9th clock cycle following every byte sent onto the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 0 0 0 R/W Figure 3. Slave Address Bits http://onsemi.com 4 CAT24AA01, CAT24AA02 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9 BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4. Acknowledge Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHIGH tLOW tR tHD:DAT tSU:DAT tSU:STO tDH tBUF Figure 5. Bus Timing WRITE OPERATIONS Byte Write Acknowledge Polling To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends an address byte and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri−stated and the Slave does not acknowledge the Master (Figure 6). Page Write As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow−up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 16 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh. http://onsemi.com 5 CAT24AA01, CAT24AA02 BUS ACTIVITY: MASTER S T A R T S SLAVE A C K A C K A C K SLAVE ADDRESS ADDRESS BYTE a7 ÷ a 0 DATA BYTE d7 ÷ d0 S T O P P Figure 6. Byte Write Sequence SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: S T A MASTER R T S SLAVE n =1 x v15 SLAVE ADDRESS ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+x S T O P P A C K A C K A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP Figure 9. WP Timing http://onsemi.com 6 CAT24AA01, CAT24AA02 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode. Selective Read condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11). Sequential Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends an address byte to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START BUS ACTIVITY: MASTER S T A R T S SLAVE If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. For the CAT24AA01, the internal address counter will not wrap around at the end of the 128 byte memory space. N O SLAVE ADDRESS S AT CO KP P A C K 8 9 DATA BYT E SCL SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing S T A MASTER R T S SLAVE A C K A C K S T A R T S A C K DATA BYT E N O SLAVE ADDRESS BUS ACTIVITY: SLAVE ADDRESS ADDRESS BYTE S AT CO KP P Figure 11. Selective Read Sequence BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O S AT CO KP P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATE BYTA n+2 DATA BYTE n+x Figure 12. Sequential Read Sequence http://onsemi.com 7 CAT24AA01, CAT24AA02 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 8 CAT24AA01, CAT24AA02 PACKAGE DIMENSIONS TSOT−23, 5 LEAD CASE 419AE−01 ISSUE O SYMBOL A A1 A2 b c D E1 E E E1 e L L1 L2 0.30 0.01 0.80 0.30 0.12 0.15 2.90 BSC 2.80 BSC 1.60 BSC 0.95 TYP 0.40 0.60 REF 0.25 BSC 0.50 0.05 0.87 D e MIN NOM MAX 1.00 0.10 0.90 0.45 0.20 θ TOP VIEW 0º 8º A2 A q b A1 L1 L c L2 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-193. END VIEW http://onsemi.com 9 CAT24AA01, CAT24AA02 Example of Ordering Information Prefix CAT Device # 24AA02 Suffix TD I −G T3 Company ID Product Number 24AA01 24AA02 Temperature Range I = Industrial (−40°C to +85°C) Lead Finish G: NiPdAu Blank: Matte−Tin Tape & Reel (Note 12) T: Tape & Reel 3: 3,000 Units / Reel 10: 10,000 / Reel Package TD: TSOT−23 5−Lead W: SOIC 8−Lead 8. All packages are RoHS−compliant (Lead−free, Halogen−free). 9. The standard lead finish is NiPdAu. 10. The device used in the above example is a CAT24AA02TDI−GT3 (TSOT−23 5−Lead, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 11. For additional package and temperature options, please contact your nearest ON Semiconductor sales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 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