CAT24AA08WI-G

CAT24AA04, CAT24AA08 4-Kb and 8-Kb I2C CMOS Serial EEPROM DESCRIPTION FEATURES 2 „ Standard and Fast I C Protocol Compatible The CAT24AA04/24AA08 are 4-Kb and 8-Kb CMOS Serial EEPROM devices internally organized as 512x8/1024x8 bits. „ Supports 1MHz Clock Frequency „ 1.7 V to 5.5 V Supply Voltage Range They feature a 16-byte page write buffer and support 100kHz, 400kHz and 1MHz I2C protocols. „ 16-Byte Page Write Buffer „ Hardware Write Protection for entire memory In contrast to the CAT24C04/24C08, the CAT24AA04/24AA08 have no external address pins, and are therefore suitable in applications that require a single CAT24AA04/08 on the I2C bus. „ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) „ Low power CMOS technology „ 1,000,000 program/erase cycles „ 100 year data retention „ Industrial temperature range „ RoHS-compliant TSOT-23 5-lead and SOIC 8-lead packages For Ordering Information details, see page 12. FUNCTIONAL SYMBOL PIN CONFIGURATION SOIC (W) VCC TSOT-23 (TD) NC 1 8 VCC NC 2 7 WP NC 3 6 SCL VSS 4 5 SDA SCL 1 VSS 2 SDA 3 5 WP SCL 4 VCC CAT24AA04 CAT24AA08 * For the location of Pin 1, please consult the corresponding package drawing. SDA WP VSS PIN FUNCTIONS Pin Name Function SDA Serial Data Input/Output SCL Clock Input WP Write Protect VCC Power Supply VSS Ground NC No Connect © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 1 Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 ABSOLUTE MAXIMUM RATINGS (1) Parameters Storage Temperature Voltage on any Pin with Respect to Ground (2) Ratings Units –65 to +150 ºC –0.5 to +6.5 V REABILITY CHARACTERISTICS(3) Symbol NEND (4) TDR Parameter Min Units Endurance 1,000,000 Program/Erase Cycles 100 Years Data Retention D.C. OPERATING CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions ICCR Read Current ICCW Min Max Units Read, fSCL = 400 kHz 0.5 mA Write Current Write, fSCL = 400 kHz 1 mA ISB Standby Current All I/O Pins at GND or VCC 1 μA Pin at GND or VCC IL I/O Pin Leakage 1 μA VIL Input Low Voltage -0.5 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V Max Units PIN IMPEDANCE CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol CIN (3) Parameter Conditions SDA I/O Pin Capacitance VIN = 0V 8 pF CIN(3) Input Capacitance (other pins) VIN = 0V 6 pF IWP(5) WP Input Current VIN < 0.5xVCC, VCC = 5.5 V 200 VIN < 0.5xVCC, VCC = 3.3 V 150 VIN < 0.5xVCC, VCC = 1.8 V 100 VIN > 0.5xVCC μA 1 Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode @ 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. Doc. No. MD-1132 Rev. B 2 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 A.C. CHARACTERISTICS (1) VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Standard VCC = 1.7V – 5.5V Symbol Parameter FSCL tHD:STA Min Max Clock Frequency Fast 1 MHz VCC = 1.7V – 5.5V VCC = 2.5V – 5.5V Min Max 100 START Condition Hold Time Min 400 Units Max 1000 kHz 4 0.6 0.25 μs tLOW Low Period of SCL Clock 4.7 1.3 0.5 μs tHIGH High Period of SCL Clock 4 0.6 0.5 μs 4.7 0.6 0.25 μs 0 0 ns tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 tSU:DAT Data In Setup Time 250 tR(2) (2) tF tSU:STO ns 300 300 ns SDA and SCL Fall Time 300 300 100 ns STOP Condition Setup Time Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 4 0.6 0.25 μs 4.7 1.3 0.5 μs 3.5 100 0.9 50 100 tSU:WP WP Setup Time 0 tHD:WP WP Hold Time 2.5 tPU(2, 3) 100 1000 tBUF tWR 100 SDA and SCL Rise Time 0.4 50 100 0 ns 100 ns μs 0 2.5 μs μs 1 Write Cycle Time 5 5 5 ms Power-up to Ready Mode 1 1 1 ms A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = 1mA (VCC < 2.5V); CL = 100pF Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 POWER-ON RESET (POR) FUNCTIONAL DESCRIPTION Each CAT24AA04/08 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. The CAT24AA04/08 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24AA04/08 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. This bi-directional POR behavior protects the device against brown-out failure, following a temporary loss of power. I2C BUS PROTOCOL The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and the Master and Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by releasing it HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP CONDITION An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). A START is generated by a HIGH to LOW transition, while a STOP is generated by a LOW to HIGH transition. The START acts like a wake-up call. Absent a START, no Slave will respond to the Master. The STOP completes all commands. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address (Figure 2). The four most significant bits of the Slave address are 1010 (Ah). The next three bits from the Slave address byte are assigned as shown in Figure 2, where a9 and a8 are internal address ¯¯, instructs the Slave to either bits.The last bit, R/W provide (1) or accept (0) data, i.e. it specifies a Read (1) or a Write (0) operation. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of SCL. Acknowledge During the 9th clock cycle following every byte sent onto the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4. WP: When the Write Protect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LOW internally. Doc. No. MD-1132 Rev. B 4 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 Figure 1: Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2: Slave Address Bits 1 0 1 0 0 0 a8 ¯¯ R/W CAT24AA04 1 0 1 0 0 a9 a8 ¯¯ R/W CAT24AA08 Figure 3: Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP (≥ tSU:DAT) START ACK DELAY (≤ tAA) Figure 4: Bus Timing tF tR tHIGH tLOW tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave ¯¯ bit set to ‘0’. The Master then address with the R/W sends an address byte and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 6). Delivery State The CAT24AA04/08 is shipped erased, i.e., all bytes are FFh. Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 16 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24AA04/08 initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24AA04/08 is still busy with the write operation, NoACK will be returned. If the CAT24AA04/08 device has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the st 1 data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Doc. No. MD-1132 Rev. B 6 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 Figure 5: Byte Write Sequence S T A R T BUS ACTIVITY: MASTER SLAVE ADDRESS a9 a8 S ADDRESS BYTE DATA BYTE a7 ÷ a0 d7 ÷ d0 S T O P P * A C K A C K A C K SLAVE * a9 = 0 for CAT24AA04 Figure 6: Write Cycle Timing SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 7: Page Write Sequence S T A R T BUS ACTIVITY: MASTER SLAVE ADDRESS ADDRESS BYTE DATA BYTE n a7 ÷ a0 d7 ÷ d0 a9 a8 S DATA BYTE n+x S T O P P * A C K A C K A C K A C K SLAVE n=1 x ≤ 15 DATA BYTE n+1 A C K * a9 = 0 for CAT24AA04 Figure 8: WP Timing ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a ¯¯ bit set to ‘1’. The Slave Slave address with the R/W responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the ¯¯ bit set to ‘0’ and then sends an address byte to R/W the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address ¯¯ bit set to ‘1’. The Slave responds with with the R/W ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. Doc. No. MD-1132 Rev. B 8 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 Figure 9: Immediate Read Sequence and Timing BUS ACTIVITY: MASTER N O S T A R T S AT CO KP SLAVE ADDRESS S P A C K SLAVE 8 SCL DATA BYTE 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10: Selective Read Sequence BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS S N O S AT CO KP SLAVE ADDRESS S A C K A C K SLAVE P A C K DATA BYTE Figure 11: Sequential Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE © 2008 SCILLC. All rights reserved Characteristics subject to change without notice A C K DATA BYTE n DATA BYTE n+1 9 DATA BYTE n+2 DATA BYTE n+x Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 PACKAGE OUTLINE DRAWINGS SOIC 8-Lead 150mils (W) (1)(2) E1 E SYMBOL MIN A 1.35 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM MAX 1.75 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. Doc. No. MD-1132 Rev. B 10 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 TSOT 5-Lead (TD)(1)(2) SYMBOL D MIN NOM A e E1 E MAX 1.00 A1 0.01 0.05 0.10 A2 0.80 0.87 0.90 b 0.30 c 0.12 0.15 0.20 0.45 D 2.90 BSC E 2.80 BSC E1 1.60 BSC e 0.95 TYP L 0.30 0.40 L1 0.60 REF L2 0.25 BSC θ 0º 0.50 8º TOP VIEW A2 A b θ L A1 c L2 L1 SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-193. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc. No. MD-1132 Rev. B CAT24AA04, CAT24AA08 EXAMPLE OF ORDERING INFORMATION(1) Prefix CAT Device # Suffix 24AA04 TD I – Temperature Range I: Industrial (-40ºC to 85ºC) Company ID Product Number 24AA04 24AA08 G T3 Tape & Reel T: Tape & Reel 3: 3,000/Reel 10: 10,000/Reel(4) Lead Finish G: NiPdAu Blank: Matte-Tin Package TD: TSOT-23 5-lead W: SOIC 8-lead For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard plated finish is NiPdAu. (3) The device used in the above example is a CAT24AA04TDI-GT3 (TSOT-23 5-lead, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). (4) The 10,000/Reel option is only available for the TSOT-23 5-lead package. (5) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. Doc. No. MD-1132 Rev. B 12 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT24AA04, CAT24AA08 REVISION HISTORY Date Revision Description 19-Sept-08 A Initial Issue 23-Oct-08 B Change logo and fine print to ON Semiconductor ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-1132 Rev. B