CAT24C208WI-GT3

CAT24C208 EEPROM Serial 8-Kb I2C Dual Port Description The CAT24C208 is an EEPROM Serial 8−Kb I2C Dual Port internally organized as 4 segments of 256 bytes each. The CAT24C208 features a 16−byte page write buffer and can be accessed from either of two separate I2C compatible ports, DSP (SDA, SCL) and DDC (SDA, SCL). Arbitration between the two interface ports is automatic and allows the appearance of individual access to the memory from each interface. www.onsemi.com SOIC−8 W SUFFIX CASE 751BD Features • • • • • • • • • • Supports Standard and Fast I2C Protocol 2.5 V to 5.5 V Operation 16−Byte Page Write Buffer Schmitt Triggers and Noise Protection Filters on I2C Bus Input Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range SOIC 8−lead Package This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant PIN CONFIGURATION DSP VCC 1 DDC VCC DSP SCL EDID SEL DSP SDA DDC SCL VSS DDC SDA SOIC (W) (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DSP VCC DDC VCC ARBITRATION LOGIC DISPLAY CONTROL LOGIC DSP SCL DSP SDA VSS D E C O D E R S 1K X 8 MEMORY ARRAY CONFIGURATION REGISTER D E C O D E R S DDC CONTROL LOGIC DDC SCL DDC SDA EDID SEL Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2009 May, 2018 − Rev. 7 1 Publication Order Number: CAT24C208/D CAT24C208 Table 1. PIN DESCRIPTION Pin Number Pin Name Function 1 DSP VCC Device power from display controller 2 DSP SCL The CAT24C208 DSP serial clock bidirectional pin is used to clock all data transfers into or out of the device DSP SDA pin and is also used to block DSP Port access when DDC Port is active. 3 DSP SDA DSP Serial Data/Address. The bidirectional DSP serial data/address pin is used to transfer data into and out of the device from a display controller. The DSP SDA pin is an open drain output and can be wireOR’ed with other open drain or open collector outputs. 4 VSS 5 DDC SDA Device ground. DDC Serial Data/Address. The bidirectional DDC serial data/address pin is used to transfer data into and out of the device from a DDC host. The DDC SDA pin is an open drain output and can be wire− OR’ed with other open drain or open collector outputs. 6 DDC SCL The CAT24C208 DDC serial clock bidirectional pin is used to clock all data transfers into or out of the device DDC SDA pin, and is used to block DDC Port for access when DSP Port is active. 7 EDID SEL EDID select. The CAT24C208 EDID select input selects the active bank of memory to be accessed via the DDC SDA/SCL interface as set in the configuration register. 8 DDC VCC Device power when powered from a DDC host. Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias –55 to +125 °C Storage Temperature –65 to +150 °C –2.0 to +VCC +2.0 V –2.0 to +7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 °C Output Short Circuit Current (Note 2) 100 mA Voltage on Any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 3. RELIABILITY CHARACTERISTICS Symbol Reference Test Method Min Units Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 3) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 3) ESD Susceptibility JEDEC Standard JESD 22 2000 Volts JEDEC Standard 17 100 mA NEND (Note 3) ILTH (Notes 3 and 4) Parameter Latch−up 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. Table 4. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V) Symbol Parameter Conditions Min Typ Max Units CI/O (Note 5) Input/Output Capacitance (Either DSP or DDC SDA) VI/O = 0 V 8 pF CIN (Note 5) Input Capacitance (EDID, Either DSP or DDC SCL) VIN = 0 V 6 pF 5. This parameter is tested initially and after a design or process change that affects the parameter. www.onsemi.com 2 CAT24C208 Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Units fSCL = 100 KHz 3 mA ICC Power Supply Current ISB Standby Current (VCC = 5.0 V) VIN = GND or either DSP or DDC VCC 50 mA ILI Input Leakage Current VIN = GND to either DSP or DDC VCC 10 mA ILO Output Leakage Current 10 mA VIL Input Low Voltage −1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOUT = GND to either DSP or DDC VCC VHYS Input Hysteresis 0.05 VOL1 Output Low Voltage (VCC = 3 V) VCCL1 VCCL2 V IOL = 3 mA 0.4 V Leakage DSP VCC to DDC VCC ±100 mA Leakage DDC VCC to DSP VCC ±100 mA Max Units Clock Frequency 400 kHz Noise Suppression Time Constant at SCL, SDA Inputs 100 ns SCL Low to SDA Data Out and ACK Out 0.9 ms Table 6. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.) Symbol Parameter Min READ & WRITE CYCLE LIMITS FSCL TI (Note 6) tAA tBUF (Note 6) Time the Bus Must be Free Before a New Transmission Can Start 1.3 ms Start Condition Hold Time 0.6 ms tLOW Clock Low Period 1.3 ms tHIGH Clock High Period 0.6 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 ms tHD:DAT Data In Hold Time 0 ns tSU:DAT Data In Setup Time 100 tHD:STA ns tR (Note 6) SDA and SCL Rise Time 300 ns tF (Note 6) SDA and SCL Fall Time 300 ns tSU:STO tDH Stop Condition Setup Time 0.6 ms Data Out Hold Time 100 ns Table 7. POWER−UP TIMING (Notes 6 and 7) Symbol Parameter tPUR tPUW Min Typ Max Units Power−up to Read Operation 1 ms Power−up to Write Operation 1 ms Max Units 5 ms 6. This parameter is tested initially and after a design or process change that affects the parameter. 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 8. WRITE CYCLE LIMITS Symbol Parameter Min tWR Write Cycle Time Typ The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. www.onsemi.com 3 CAT24C208 Functional Description The CAT24C208 has a total memory space of 1K bytes which is accessible from either of two I2C interface ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and DDC_SCL), and with the use of segment pointer at address 60h. On power up and after any instruction, the segment pointer will be in segment 00h for DSP and in segment 00h of the bank selected by the configuration register for DDC. The entire memory appears as contiguous memory space from the perspective of the display interface (DSP_SDA and DSP_SCL), see Figure 4, and Figures 14 to Figure 21 for a complete description of the DSP Interface. A configuration register at addresses 62/63h is used to configure the operation and memory map of the device as seen from the DDC interface, (DDC_SDA and DDC_SCL). Read and write operations can be performed on any location within the memory space from the display DSP interface regardless of the state of the EDID SEL pin or the activity on the DDC interface. From the DDC interface, the memory space appears as two 512 byte banks of memory, 28 +5V DC (SUPPLIED BY DISPLAY) DDC +5V 47.5K M1−DA CONNECTOR TO HOST CONTROLLER with 2 segments each 00h and 01h in the upper and lower bank, see Figure 3. Each bank of memory can be used to store an E−EDID data structure. However, only one bank can be read through the DDC port at a time. The active bank of memory (that is, the bank that appears at address A0h on the DDC port) is controlled through the configuration register at 62/63h and the EDID_SEL pin. No write operations are possible from the DDC interface unless the DDC Write Enable bit is set (WE = 1) in the device configuration register at device address 62h. The device automatically arbitrates between the two interfaces to allow the appearance of individual access to the memory from each interface. In a typical E−EDID application the EDID_SEL pin is usually connected to the “Analog Cable Detect” pin of a VESA M1 compliant, dual−mode (analog and digital) display. In this manner, the E−EDID appearing at address A0h on the DDC port will be either the analog or digital E−EDID, depending on the state of the “Analog Cable Detect” pin (pin C3 of the M1−DA connector). See Figure 2. C3 27 26 10K 8 7 E−EDID 6 EEPROM 5 DDC CLK DDC DATA 1 2 3 4 I2C TO PROJECTOR/MONITOR DISPLAY CONTROLLER Fuse, Resistor or Other Current Limiting Device Required in All M1 Displays 8 HPD RELAY CONTACTS SHOWN IN DE−ENERGIZED POSITION 2A MAX Figure 2. MEMORY ARRAY MEMORY ARRAY Upper Bank 01 Segment 1 256 Bytes 00 Segment 0 256 Bytes 01 Lower Bank 00 11 00 01 Segment 1 256 Bytes 00 Segment 0 256 Bytes Segment Pointer Address by Configuration Register (see Table 10) 10 00 Segment 3 256 Bytes Segment 2 256 Bytes Segment 1 256 Bytes Segment 0 256 Bytes Segment Pointer No Segment Pointer No Segment Pointer Figure 3. DDC Interface Figure 4. DSP Interface www.onsemi.com 4 00 CAT24C208 I2C Bus Protocol Acknowledge The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the respective SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24C208 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT24C208 is in a READ mode it transmits 8 bits of data, releases the respective SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24C208 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. After an unsuccessful data transfer an acknowledge will not be issued (NACK) by the slave (CAT24C208), and the master should abort the sequence. If continued the device will read from or write to the wrong address in the two instruction format with the segment pointers. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of either SDA when the respective SCL is HIGH. The CAT24C208 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP START ACK DELAY Figure 5. Acknowledge Timing Device Addressing DDC Interface determines which of the 256 bytes within segment 00h is being read. Here the segment 00h can be at the lower or upper bank depending on the configuration register. Sequential reads can be done in much the same manner by reading successive bytes after each acknowledge without generating a stop condition. See Figure 7. The device automatically increments the word offset value (8−bit value) and with wraparound in the same segment 00h to read maximum of 256 bytes. Both the DDC and DSP interfaces to the device are based on the I2C bus serial interface. All memory space operations are done at the A0/A1 DDC address pair. As such, all write operations to the memory space are done at DDC address A0h and all read operations of the memory space are done at DDC address A1h. Figure 6 shows the bit sequence of a random read from anywhere within the memory space. The word offset www.onsemi.com 5 CAT24C208 WORD OFFSET START 1010 0000 ACK A7 − A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP Figure 6. Random Access Read (Segment 00h only) WORD OFFSET START 1010 0000 ACK A7 − A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP Figure 7. Sequential Read (Segment 00h only) Figures 8 and 9 show the byte and page write respectively. The configuration register must have the WE bit set to 1 prior to any write on DDC Port. Only the segment 00h can be accessed of either lower or upper bank. WORD OFFSET START 1010 0000 ACK A7 − A0 ADDRESS ACK DATA ACK STOP Figure 8. Byte Write (Segment 00h only) WORD OFFSET START 1010 0000 ACK A7 − A0 ADDRESS ACK DATA0 ACK ......... DATA15 ACK STOP Figure 9. Page Write (Segment 00h only) segment. Note that if the segment pointer is set to 00h then the device will behave like a standard DDC2B EEPROM. Read and write with segment pointer can expand the addressable memory to 512 bytes in each bank with wraparound to the next segment in the same bank only. The two banks can be individually selected by the configuration register and EDID Sel pin, as shown in Table 10. The segments are selected by the two bits S1S0 = 00 or 01 in the segment address. Figures 10 to 13 show the random read, sequential read, byte write and page write. The segment pointer is at the address 60h and is write−only. This means that a memory access at 61h will give undefined results. The segment pointer is a volatile register. The device configuration register at 62/63 (hex) is a non−volatile register. The configuration register will be shipped in the erased (set to FFh) state. The segment pointer is used to expand the available DDC address space while maintaining backward compatibility with older DDC interfaces such as DDC2B. For each value of the 8−bit segment pointer one segment (256 bytes) is available at the A0/A1 pair. The standard DDC 8−bit address is sufficient to address each of the 256 bytes within a START 0110 0000 ACK xxxx xxS1S0 Segment ADDRESS ACK START 1010 0000 ACK A7 − A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP Figure 10. Random Access Read START 0110 0000 ACK START 1010 0000 ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP Figure 11. Sequential Read START 0110 0000 ACK START 1010 0000 ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK ACK DATA ACK STOP Figure 12. Byte Write START 0110 0000 ACK START 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK DATA0 ACK Figure 13. Page Write www.onsemi.com 6 ......... DATA15 ACK STOP CAT24C208 DSP Interface The DSP interface is similar to I2C bus serial interface. Without the segment pointer, the maximum accessible memory space is 256 bytes of segment 00h only. In the START 1010 0000 ACK A7 − A0 ADDRESS sequential mode the wrap around will be in the same segment also. Figures 14 to 17 show the read and write on the DSP Port. ACK START 1010 0001 ACK DATA NOACK STOP Figure 14. Random Access Read START 1010 0000 ACK A7 − A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP Figure 15. Sequential Read START 1010 0000 ACK A7 − A0 ADDRESS ACK DATA ACK STOP Figure 16. Byte Write START 1010 0000 ACK A7 − A0 ADDRESS ACK DATA0 ACK ......... DATA15 ACK STOP Figure 17. Page Write The segment pointer is used to expand the available DSP port addressable memory to 1 k bytes, divided into four segments of 256 bytes each. The four segments are selected START 0110 0000 ACK START 1010 0000 ACK by two bits S1S0 = 00, 01, 10, 11 in the segment address. Figures 18 to 21 show the random read, sequential read, byte write and page write. ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP Figure 18. Random Access Read START 0110 0000 ACK xxxx xxS1S0 Segment ADDRESS START 1010 0000 ACK A7 − A0 ADDRESS ACK ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP Figure 19. Sequential Read START 0110 0000 ACK START 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK DATA ACK STOP Figure 20. Byte Write START 0110 0000 ACK START 1010 0000 ACK ACK xxxx xxS1S0 Segment ADDRESS A7 − A0 ADDRESS ACK DATA0 ACK Figure 21. Page Write www.onsemi.com 7 ......... DATA15 ACK STOP CAT24C208 Arbitration The device performs a simplistic arbitration between the DDC and DSP ports. While the arbitration scheme described is not foolproof, it does prevent most errors. Arbitration logic within the device monitors activity on DDC_SCL and DSP_SCL. When both I2C ports are idle, DDC_SCL and DSP_SCL are both high and the arbitration logic is inactive. When a START condition is detected on either port, the opposite port SCL line is pulled low, holding off activity on that port. When the initiating SCL line has remained high for one full second, the arbitration logic assumes that the initiating devices is finished and releases the other SCL line. If the non−initiating device has been waiting for access, it can now read or write the device. Table 9. CONFIGURATION REGISTER Register Function MSB Configuration Register LSB 7 6 5 4 3 2 1 0 X X X X WE AB1 AB0 NB Function Description NB: Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank AB0: Active Bank Control Bit 0 (See Table 10) AB1: Active Bank Control Bit 1 (See Table 10) WE DDC: Write Enable 0 = Write Disabled, 1= Write Enabled (Note 8) 8. WE affects only write operations from the DDC port, not the display port. The display port always has write access. Table 10. CONFIGURATION REGISTER TRUTH TABLE AB1 AB0 NB EDID Select Pin Active Bank 0 X 0 0 Lower Bank 0 X 0 1 Upper Bank 1 0 0 X Lower Bank 1 1 0 X Upper Bank X X 1 X Lower (only) Bank The configuration register is a non−volatile register and is available from either DSP or DDC port at address 62h / 63h for write and read resp. Table 11. READ CONFIGURATION REGISTER START 0110 0011 ACK DATA NO ACK STOP Table 12. WRITE CONFIGURATION REGISTER START 0110 0010 ACK DUMMY ADDRESS ACK XXXX WE AB1 AB0 NB ACK STOP ORDERING INFORMATION Device Order Number CAT24C208WI−GT3 Specific Device Marking Package Type Temperature Range Lead Finish Shipping† 24C208WI SOIC−8 Industrial NiPdAu Tape & Reel, 3,000 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: DESCRIPTION: 98AON34272E SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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