DATA SHEET
www.onsemi.com
EEPROM Serial 256-Kb I2C
CAT24C256
SOIC−8
W SUFFIX
CASE 751BD
Description
The CAT24C256 is a EEPROM Serial 256−Kb I2C, internally
organized as 32,768 words of 8 bits each.
It features a 64−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to eight
CAT24C256 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
TSSOP−8
Y SUFFIX
CASE 948AL
UDFN−8
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0
1
VCC
Features
A1
WP
•
•
•
•
•
A2
SCL
VSS
SDA
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
64−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC, TSSOP and UDFN 8−Pad Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
PIN FUNCTION
Pin
Name†
A0, A1, A2
Function
Device Address
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
VCC
Power Supply
VSS
Ground
†The exposed pad for the UDFN packages can be left
floating or connected to Ground.
SCL
CAT24C256
A2, A1, A0
SOIC (W, X), TSSOP (Y), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
SDA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
WP
VSS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2014
February, 2022 − Rev. 16
1
Publication Order Number:
CAT24C256/D
CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Notes 3, 4)
TDR
Endurance
Min
Units
1,000,000
Program/Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
4. The product uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Parameter
Symbol
ICCR
Read Current
ICCW
Write Current
ISB
IL
Standby Current
I/O Pin Leakage
Test Conditions
Min
Max
Units
1
mA
3
mA
TA = −40°C to +85°C
2
mA
TA = −40°C to +125°C
5
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
Read, fSCL = 400 kHz/1 MHz
All I/O Pins at GND or VCC
Pin at GND or VCC
mA
VIL1
Input Low Voltage
2.5 V ≤ VCC ≤ 5.5 V
−0.5
0.3 VCC
V
VIL2
Input Low Voltage
1.8 V ≤ VCC < 2.5 V
−0.5
0.25 VCC
V
VIH1
Input High Voltage
2.5 V ≤ VCC ≤ 5.5 V
0.7 VCC
VCC + 0.5
V
VIH2
Input High Voltage
1.8 V ≤ VCC < 2.5 V
0.75 VCC
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
8
pF
CIN (Note 5)
SDA I/O Pin Capacitance
VIN = 0 V
CIN (Note 5)
Input Capacitance (other pins)
VIN = 0 V
6
pF
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
75
mA
VIN < VIH, VCC = 3.3 V
50
VIN < VIH, VCC = 1.8 V
25
VIN > VIH
2
IWP, IA (Note 6)
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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2
CAT24C256
Table 5. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF
Table 6. A.C. CHARACTERISTICS (Note 7)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Standard
VCC = 1.8 V − 5.5 V
Symbol
FSCL
tHD:STA
Parameter
Min
Max
Clock Frequency
START Condition Hold Time
Fast
VCC = 1.8 V − 5.5 V
Min
100
Max
Fast−Plus
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Min
400
Max
Units
1,000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
tHIGH
High Period of SCL Clock
4
0.6
0.40
ms
4.7
0.6
0.25
ms
0
0
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 8)
SDA and SCL Rise Time
1,000
300
100
ns
tF (Note 8)
SDA and SCL Fall Time
300
300
100
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between
STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti (Note 8)
4
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
50
0.9
50
Noise Pulse Filtered at SCL
and SDA Inputs
50
0.40
50
50
ms
ns
50
ns
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
tPU
(Notes 8, 9)
Write Cycle Time
5
5
Power-up to Ready Mode
1
1
7. Test conditions according to “A.C. Test Conditions” table.
8. Tested initially and after a design or process change that affects this parameter.
9. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
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3
0.1
5
ms
1
ms
CAT24C256
Power-On Reset (POR)
The device will power up into Standby mode after VCC
exceeds the POR trigger level and will power down into
Reset mode when VCC drops below the POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
signal generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A2, A1 and A0, select one of 8 possible Slave
devices. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
Functional Description
The CAT24C256 supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C256 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A0, A1,
and A2.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
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4
CAT24C256
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY (RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
SDA OUT
Figure 5. Bus Timing
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5
tBUF
CAT24C256
WRITE OPERATIONS
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be written
(Figure 6). The Slave acknowledges all 4 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Acknowledge Polling
Page Write
Hardware Write Protection
The CAT24C256 contains 32,768 bytes of data, arranged
in 512 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the first byte to be
written. The most significant bit of the address word is ‘don’t
care’, the next 9 bits identify the page and the last 6 bits
identify the byte within the page. Up to 64 bytes can be
written in one Write cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C256. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C256 will not acknowledge the data byte
and the Write request will be rejected.
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT24C256 will not acknowledge the Slave address,
as long as internal Write is in progress.
Delivery State
The CAT24C256 is shipped erased, i.e., all bytes are FFh.
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6
CAT24C256
S
T
BUS ACTIVITY: A
MASTER R
T
SLAVE
ADDRESS
BYTE ADDRESS
A7 − A0
A15 − A8
SDA LINE S
S
T
O
P
DATA
P
*
A
C
K
A
C
K
* = Don’t Care Bit
A
C
K
A
C
K
Figure 6. Byte Write Timing
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
S
BUS
T
ACTIVITY: A
MASTER R
T
BYTE ADDRESS
A15 − A8
A7 − A0
SLAVE
ADDRESS
SDA LINE S
DATA
DATA n
S
T
O
P
DATA n+63
P
*
* = Don’t Care Bit
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
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7
A
C
K
A
C
K
CAT24C256
READ OPERATIONS
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Immediate Address Read
In standby mode, the CAT24C256 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If that ‘previous’
byte was the last byte in memory, then the address counter
will point to the 1st memory byte, etc.
When, following a START, the CAT24C256 is presented
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24C256, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
S
T
BUS ACTIVITY: A
MASTER R
T
S
T
O
P
SLAVE
ADDRESS
SDA LINE S
P
A
C
K
SCL
8
SDA
N
O
A
C
K
DATA
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
S
T
BUS ACTIVITY: A
MASTER R
T
S
T
A
R
T
BYTE ADDRESS
A15 − A8
A7 − A0
SLAVE
ADDRESS
SDA LINE S
S
T
O
P
DATA
P
S
*
A
C
K
* = Don’t Care Bit
SLAVE
ADDRESS
A
C
K
A
C
K
N
O
A
C
K
A
C
K
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
S
T
O
P
DATA n+x
DATA n+2
P
SDA LINE
A
C
K
A
C
K
A
C
K
Figure 12. Sequential Read Timing
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8
A
C
K
N
O
A
C
K
CAT24C256
ORDERING INFORMATION
Device Order Number
Device
Marking
Package
Type
CAT24C256WI−GT3
24256E
CAT24C256YI−GT3
CAT24C256HU4IGT3
Temperature Range
Lead Finish
Shipping†
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
C56E
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
C8U
UDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10. All packages are RoHS-compliant (Lead-free, Halogen-free).
11. The standard lead finish is NiPdAu.
12. For additional package and temperature options, please contact your nearest onsemi Sales office.
13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14. For detailed information and a breakdown of device nomenclature and numbering systems, please see the onsemi Device Nomenclature
document, TND310/D, available at www.onsemi.com
onsemi is licensed by Philips Corporation to carry the I2C Bus Protocol.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
1
SCALE 2:1
PIN ONE
REFERENCE
0.10 C
B
A
D
L1
ÇÇ
ÇÇ
ÇÇ
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
EXPOSED Cu
DETAIL B
A
0.10 C
0.08 C
1
D2
ÉÉ
ÉÉ
ÇÇ
C
MOLD CMPD
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
1
L
4
5
8X
e
XXXXX
A
WL
Y
W
G
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
2.00 BSC
1.35
1.45
3.00 BSC
1.25
1.35
0.50 BSC
0.25
0.35
−−−
0.15
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
E2
8
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
DETAIL B
A3
A1
SIDE VIEW
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
0.10 C TOP VIEW
NOTE 4
DATE 23 MAR 2015
XXXXX
AWLYWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
1.56
8X
0.68
1.45 3.40
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON42552E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
UDFN8, 2X3 EXTENDED PAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
DATE 19 DEC 2008
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
A
θ
c
e
b
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX
Y
WW
A
G
= Specific Device Code
= Year
= Work Week
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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